JP2008103011A - Semiconductor nonvolatile memory circuit and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory circuit and the device, in which the storage information can be optically set and electrically written without necessitating an excess interface circuit, etc. <P>SOLUTION: This nonvolatile memory circuit is equipped with: a flip-flop 20 consisting of a first inverter 21 and a second inverter 22; a first MIS transistor 11 connected between a non-inverted output terminal C of the flip-flop and a grounding wire GND; a second MIS transistor 12 connected between an inverted output terminal C_ of the flip-flop and the grounding wire GND; and a write-in word line WLW connected to gates of the first MIS transistor and the second MIS transistor, and it includes a first photodiode 41 connected between the non-inverted output terminal of the flip-flop and the grounding wire, and a second photodiode 42 connected between the inverted output terminal of the flip-flop and the grounding wire. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory circuit and device capable of holding stored information without applying a power supply voltage. More specifically, the present invention does not require an extra interface circuit or the like, and sets the stored information optically. The present invention relates to an electrically writable nonvolatile memory circuit and device.

  Nonvolatile memories that can be written electrically and can retain the stored data even when the power is turned off include EEPROM, ferroelectric memory (FeRAM), and ferromagnetic tunnel magnetoresistive elements. A memory (MRAM) or the like is known.

  FIG. 8 shows a circuit diagram of an EEPROM memory cell. The drain / source terminals of a special transistor 90 constituting the memory cell are connected to the bit line BL and the plate line PL. The gate terminal of the transistor 90 is connected to the word line WL. The transistor 90 constituting the EEPROM memory cell has a special structure as shown in FIG. FIG. 9 is a cross-sectional view showing the basic structure of the transistor 90. An electrically insulated floating gate FG is provided between a normal gate G and a substrate.

  When electrons are accumulated in the floating gate FG, information is stored by increasing the threshold voltage of the transistor. That is, the memory cells that store electrons in the floating gate and the memory cells that do not store electrons have different threshold voltages, so that the stored information H, L ( 1,0) can be identified.

  When information is written in the memory cell of the EEPROM, the following is performed. First, as shown in FIG. 10, a voltage of 0 V is applied to the plate line PL of the memory cell in which information is written, a voltage of 12 V is applied to the word line WL, a voltage of 6 V is applied to the bit line BL, and the source and drain are connected. Apply current. Then, electrons generated by the hot carrier effect are accumulated in the floating gate FG.

  To erase the information stored in the memory cell of the EEPROM, conversely, the electrons accumulated in the floating gate FG are removed. For this purpose, as shown in FIG. 11, a voltage of 12V is applied to the plate line PL, and a voltage of 0V is applied to the word line WL. The bit line BL is opened. Electrons accumulated in the floating gate flow out to the plate line PL side by a tunnel current and are removed from the floating gate.

  Since such an EEPROM has a special memory cell structure as shown in FIG. 9, it is necessary to add many steps to the manufacturing process of the general-purpose logic integrated circuit. Further, since data retention depends on the electrical insulation of the floating gate, more accurate manufacturing process management has been required. For these reasons, the logic integrated circuit in which the EEPROM is embedded has a problem that the yield is not stable and the manufacturing cost is increased.

  Similar problems have been encountered in FeRAM and MRAM. Ferroelectric materials used in FeRAM and magnetic materials used in MRAM are materials that are not used in normal semiconductor manufacturing. Therefore, when manufacturing a logic integrated circuit in which a memory composed of FeRAM or MRAM is mixed, logic is used. It is necessary to add a special process for forming the memory to the manufacturing process of the integrated circuit. There is also a great difficulty in stabilizing the yield.

  In view of this, a device for manufacturing a non-volatile memory circuit has been made only by a manufacturing process of a general-purpose logic integrated circuit. Specifically, a nonvolatile memory as described in Patent Document 1 below has been proposed. Patent Document 1 describes a nonvolatile memory that can be manufactured only by a general CMOS process without adding a special process.

  FIG. 12 is a diagram illustrating an example of a circuit configuration of the nonvolatile memory circuit described in Patent Document 1. In FIG. The nonvolatile memory circuit 9 includes a flip-flop 20 including two inverters 21 and 22. A MIS transistor 11 is connected between the non-inverting output terminal C of the flip-flop 20 and the ground line GND. Further, another MIS type transistor 12 is connected between the inverting output terminal C_ of the flip-flop 20 and the ground line GND. Information of the flip-flop 20 can be read and written by the bit lines BL and BL_ as in a normal SRAM circuit.

  The nonvolatile memory is written, held, and read as follows. First, in a first step, the flip-flop 20 latches the H level (high voltage) or L level (low voltage) state corresponding to the data to be written. In the case of a memory array configuration, the input / output of this data selects the bit lines BL and BL_ and the word line WL, and the H / L level state of the bit lines BL and BL_ is transferred to the flip-flop 20. Note that the bit line BL and the bit line BL_ are set in an inverted state, and the transistors 31 and 32 are transfer gates.

  In the second step, the power supply voltage of the flip-flop 20 is raised from a normal voltage (for example, 1.8 V) to a higher voltage (for example, 3.3 V). Subsequently, the potential of the write word line WLW commonly connected to the gates of the transistors 11 and 12 is set to 1.5 V, for example. At this time, the drain voltage of one of the transistor 11 and the transistor 12 is 3.3V, and the other drain voltage is 0V. Therefore, a large current flows through one transistor and a hot carrier effect is generated, and no hot carrier effect is generated in the other transistor. The stored information is permanently stored as non-volatile information as a difference in threshold voltage of the transistor depending on the presence or absence of the hot carrier effect.

Next, a non-volatile data re-reading operation (for example, an operation when the power is turned on from the power-off state) will be described. In this case, the power supply voltage of the flip-flop 20 increases from 0V to the normal 1.8V. At this time, the write word line WLW is set to 1.8 V, and the transistors 11 and 12 are kept conductive. The flip-flop 20 transitions from the indefinite state to the definite state, but the definite state is determined reflecting the difference in threshold voltages of the transistors 11 and 12 due to the hot carrier effect as described above. That is, the final state of the flip-flop 20 is set according to the nonvolatile information stored by the transistors 11 and 12. Thereby, the non-volatile data can be read again. Nonvolatile information can be stored by the above operation.
International Publication No. WO2004 / 057621 Pamphlet

  As described above, conventional nonvolatile memories such as EEPROM, FeRAM, and MRAM require a special process in the manufacturing process, and the manufacturing cost increases when a logic integrated circuit in which the nonvolatile memory is embedded is manufactured. There was a problem. It is also difficult to stabilize the product yield.

  According to the non-volatile memory described in Patent Document 1 (see FIG. 12), the problems of the conventional non-volatile memories such as EEPROM, FeRAM, and MRAM can be solved. However, the nonvolatile memory circuit shown in FIG. 12 has the following problems.

  Since information to be stored in the nonvolatile memory needs to be given as an electrical signal from the outside of the memory circuit, it must be routed through an input / output circuit of the integrated circuit device. This creates a constraint on the placement of the non-volatile memory circuit. That is, the position of the nonvolatile memory circuit is limited to a position close to the input / output circuit of the integrated circuit device or a position where the data line can be arranged.

  In addition, since the number of terminals connected to the input / output circuit is limited, storage information given from the outside must necessarily be serial data in which data is distributed in time series. For this reason, an interface circuit for distributing serial data to each memory cell is required, which complicates the configuration of the integrated circuit and increases costs.

  On the other hand, there is a case where information stored in a nonvolatile memory used inside the integrated circuit device cannot be easily determined from the outside. For example, there is a case where the fluctuation of the manufacturing process of the integrated circuit device is corrected by the information stored in the nonvolatile memory. Since the correction information to be stored is spatially distributed within the chip of the integrated circuit device, it is necessary to change the correction information according to the position information and store it in the nonvolatile memory. Furthermore, since it is necessary to dispose the nonvolatile memories in the chip, it is difficult to make a large-scale memory array. In such a case, it is difficult to input stored information from the outside.

  Accordingly, an object of the present invention is to provide a non-volatile memory circuit and a device capable of optically setting and storing stored information without requiring an extra interface circuit or the like.

  In order to achieve the above object, a semiconductor nonvolatile memory circuit according to the present invention is connected between a flip-flop including a first inverter and a second inverter, and a non-inverting output terminal of the flip-flop and a ground line. A first MIS transistor, a second MIS transistor connected between the inverting output terminal of the flip-flop and the ground line, the first MIS transistor, and the second MIS transistor. A non-volatile memory circuit including a write word line connected to a gate of the flip-flop, the first photodiode connected between the non-inverting output terminal of the flip-flop and the ground line, And a second photodiode connected between the inverting output terminal of the flip-flop and the ground line.

  In the above nonvolatile memory circuit, the first photodiode and the second photodiode receive light of different intensities when writing nonvolatile data.

  In the above nonvolatile memory circuit, the first MIS transistor and the second MIS transistor are capable of irreversibly changing the threshold voltage due to a hot carrier effect when writing nonvolatile data. Is preferred.

  According to another aspect of the present invention, there is provided a semiconductor nonvolatile memory device including a driver circuit that reads and writes information by selecting an arbitrary memory cell, and a first bit line and a second bit line provided in the driver circuit. A word line provided in the driver circuit; a write word line provided in the driver circuit; and a plurality of non-volatile memory circuits, the first bit line, the second bit line, A semiconductor nonvolatile memory device comprising a word line and a memory cell array connected to the write word line, wherein the nonvolatile memory circuit includes a flip-flop comprising a first inverter and a second inverter, a source A first MIS type having a drain connected to the non-inverting output terminal of the flip-flop and a ground line, and a gate connected to the write word line; A transistor, a second MIS transistor having a source-drain connected to the inverting output terminal of the flip-flop and the ground line, a gate connected to the write word line, and the non-inverting output terminal of the flip-flop And a first photodiode connected between the ground line and a second photodiode connected between the inverted output terminal of the flip-flop and the ground line.

  In the semiconductor nonvolatile memory device described above, the first photodiode and the second photodiode receive light of different intensities when writing nonvolatile data.

  In the semiconductor nonvolatile memory device, the first MIS transistor and the second MIS transistor are capable of irreversibly changing a threshold voltage due to a hot carrier effect when writing nonvolatile data. It is preferable.

  Since this invention is comprised as mentioned above, there exist the following effects.

  According to the semiconductor nonvolatile memory circuit and apparatus of the present invention, it is possible to write arbitrarily stored information optically without writing a dedicated interface circuit or the like for writing nonvolatile data. . Thereby, it is possible to write nonvolatile data at high speed in the manufacturing process of the memory device. For this reason, the manufacturing cost of the semiconductor nonvolatile memory circuit and device and the writing cost of nonvolatile data can be reduced.

  In addition, the semiconductor nonvolatile memory circuit and device of the present invention do not require a special process in the manufacturing process, and can reduce the manufacturing cost of a nonvolatile memory device or a logic integrated circuit in which a nonvolatile memory is embedded. it can.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a nonvolatile memory circuit 1 of the present invention. The nonvolatile memory circuit 1 has flip-flop type memory cells like the conventional nonvolatile memory circuit 9, and the elements and terminals corresponding to the nonvolatile memory circuit 9 are denoted by the same reference numerals. That is, the nonvolatile memory circuit 1 includes the flip-flop 20, the transistor 11, the transistor 12, the photodiode 41, and the photodiode 42.

  The transistors 11 and 12 are MIS type FETs. The flip-flop 20 includes an inverter 21 and an inverter 22, and has a configuration in which the output terminal of the inverter 21 is connected to the input terminal of the inverter 22 and the output terminal of the inverter 22 is connected to the input terminal of the inverter 21. It is preferable that the inverter 21 and the inverter 22 have a CMIS configuration. Here, the output terminal of the inverter 21 is a non-inverting output terminal C of the flip-flop 20, and the output terminal of the inverter 22 is an inverting output terminal C_ of the flip-flop 20.

  The source and drain of the transistor 11 are connected to the non-inverting output terminal C of the flip-flop 20 and the ground line GND, and the source and drain of the transistor 12 are connected to the inverted output terminal C_ of the flip-flop 20 and the ground line GND. The gates of the transistors 11 and 12 are connected to the write word line WLW. The cathode of the photodiode 41 is connected to the non-inverting output terminal C of the flip-flop 20, and the cathode of the photodiode 42 is connected to the inverting output terminal C_ of the flip-flop 20. The anodes of the photodiodes 41 and 42 are connected to the ground line GND.

  Next, the operation of the nonvolatile memory circuit 1 will be described. First, an operation for taking in data to be stored as nonvolatile data will be described. FIG. 2 is a timing chart during this data capturing operation. The output (non-inverted output) of the non-inverted output terminal C of the flip-flop 20 is represented by the same symbol C as the terminal, and the output (inverted output) of the inverted output terminal C_ is represented by the same symbol C_ as the terminal.

  FIG. 2 shows an operation of taking the H level into the non-inverted output C and the L level into the inverted output C_. The current flowing through the photodiode 41 is IPD1, and the current flowing through the photodiode 42 is IPD2. As an initial procedure of the capturing operation, light is first incident only on the photodiode 42. At this time, a photocurrent flows as the current IPD2 of the photodiode 42 as illustrated. Since no light is incident on the photodiode 41, the current IPD1 of the photodiode 41 is only a minute dark current.

  Specifically, IPD2 = 5 μA and IPD1 = 0.1 μA. That is, IPD2> IPD1. Next, with the state of the photodiodes 41 and 42 maintained, the power supply voltage applied to the flip-flop 20 is set to VDD, and the power supply voltage VDD is increased from 0V to 1.8V. When this voltage rises, the non-inverted output C and the inverted output C_ are latched at the H level and the L level, respectively. Due to the presence of the current IPD2, the inverted output C_ is pulled to the lower potential side (GND side), and the inverted output C_ is set to the L level when the flip-flop 20 changes from the indefinite state to the stable state. The Thereby, the non-volatile data is taken into the flip-flop 20.

  Although light is incident on only one of the photodiodes 41 and 42 here, light having different intensities may be incident on both. Generally, since light is incident on the two photodiodes 41 and 42 in the memory cell having a fine structure, it is difficult to allow light to be incident on only one of them. However, if there is a difference in intensity between the incident lights of the photodiodes 41 and 42, the nonvolatile data can be taken into the flip-flop 20 as described above.

  Next, the operation of writing nonvolatile data will be described. By the above-described nonvolatile data capturing operation, nonvolatile data is captured and held in the flip-flop 20. From this state, a nonvolatile data write operation is performed. FIG. 3 is a timing chart at the time of nonvolatile data write operation.

  First, at the timing of time T1, the power supply voltage VDD of the entire circuit is increased from 1.8V to 3.3V. At this time, the potential of the non-inverted output C rises from 1.8 V to 3.3 V in synchronization with the power supply voltage VDD. Next, the potential of the write word line WLW is held at 1.5 V during the period from time T2 to time T3. During other periods, it is held at 0V. In the period from time T2 to time T3, the hot carrier effect is strongly generated in the transistor 11. That is, a drain voltage of 3.3 V, which is approximately twice the normal voltage, is applied, and a gate voltage is applied that is about ½ of the drain voltage. On the other hand, a drain voltage of 0 V is applied to the transistor 12, and the hot carrier effect hardly occurs.

  Since the hot carrier effect causes irreversible fluctuations in the transistor characteristics, the state is maintained without applying a power supply voltage. That is, the data held in the flip-flop 20 in the above-described nonvolatile data capturing operation is nonvolatilely stored in the differential pair of the transistors 11 and 12 as a difference in hot carrier effect.

  Next, nonvolatile data read operation will be described. Non-volatile data is stored in the transistors 11 and 12 as a difference of the hot carrier effect. The operation of reading the nonvolatile data stored in the transistors 11 and 12 and holding the data in the flip-flop 20 is the nonvolatile data reading operation. FIG. 4 is a timing chart at the time of nonvolatile data read operation.

  First, the potential of the write word line WLW is held at 1.8 V, and both the transistors 11 and 12 are turned on. Next, as the power supply voltage VDD supplied to the flip-flop 20, the power supply voltage VDD is raised from 0V to 1.8V at the timing of time T1. When this voltage rises, the non-inverted output C and the inverted output C_ are latched at the H / L level, respectively.

  Due to the hot carrier effect, the drain current of the transistor 11 becomes smaller than that of the transistor 12. Therefore, the inverted output C_ is pulled to the lower potential side (GND side), and the inverted output C_ is set to the L level when the flip-flop 20 transitions from the indefinite state to the stable state. As a result, the state of the non-inverted output C and the inverted output C_ of the flip-flop 20 when the nonvolatile data capturing operation is performed is reproduced. That is, non-volatile data has been read.

  As a more specific embodiment, a nonvolatile memory circuit 1 to which a transfer gate is added is shown. FIG. 5 is a circuit diagram showing a configuration of the nonvolatile memory circuit 2 to which a transfer gate is added. Transistors 31 and 32 are provided as transfer gates. Except for the transistors 31 and 32 as transfer gates, the configuration is the same as that of the nonvolatile memory circuit 1, and the operation as a nonvolatile memory is also the same.

  The source-drain of the transistor 31 is connected between the non-inverting output terminal C and the bit line BL, and the source-drain of the transistor 32 is connected between the inverting output terminal C_ and the bit line BL_. The gates of the transistors 31 and 32 are connected to the word line WL. Note that inverter 21 and inverter 22 preferably have a CMIS configuration in which an nMIS transistor and a pMIS transistor are complementarily combined.

  The nonvolatile memory circuit 2 as described above can be integrated and mounted as the nonvolatile memory device 3. FIG. 6 shows a block diagram of a nonvolatile memory device 3 including the nonvolatile memory circuit 2 of the present invention.

  The nonvolatile memory device 3 includes an input buffer, an output buffer, a column decoder, a write amplifier, a sense amplifier / column selector 4, a mode selector, a row decoder, a row signal driver 5, and a memory cell array 2A. The memory cell array 2A includes a large number of nonvolatile memory circuits 2 shown in FIG. 5 arranged in rows (rows) and columns (columns).

  Of the nonvolatile memory circuits 2, all the nonvolatile memory circuits 2 arranged in the same row (row) are connected to a common word line WL. In addition, among the nonvolatile memory circuits 2, all the nonvolatile memory circuits 2 arranged in the same column are connected to the common bit lines BL and BL_.

  The mode selector receives a mode switching signal from the outside, controls the write amplifier, the low signal driver 5 and the like according to the received mode switching signal, and switches operation modes such as a read operation mode and a write operation mode.

  The column decoder receives a column address from the outside, and enables the nonvolatile memory circuit 2 in the column corresponding to the column address via the write amplifier and the sense amplifier / column selector 4. The row decoder inputs a row address from the outside and enables the nonvolatile memory circuit 2 in the row corresponding to the row address via the row signal driver 5.

  The storage data input to the nonvolatile memory device 3 is supplied to the write amplifier via the input buffer, and is written to the memory cell array 2A via the sense amplifier / column selector 4. The stored data written in the memory cell array 2A is output to the output buffer via the sense amplifier / column selector 4 and output as read data.

  FIG. 7 is a diagram illustrating a configuration of a main part of the nonvolatile memory device 3. The write amplifier / sense amplifier / column selector 4 is provided with a pair of bit lines BL and BL_ for each column. The same bit lines BL and BL_ are connected to the non-volatile memory circuits 2 arranged in the same column. The bit line BL is connected to the non-inverting output terminal C of the flip-flop 20 through the transistor 31 (see FIG. 5) of the nonvolatile memory circuit 2, and the bit line BL_ is flip-flopped through the transistor 32 of the nonvolatile memory circuit 2. 20 inverting output terminals C_.

  The low signal driver 5 is provided with a word line WL and a write word line WLW for each row. The same word line WL and write word line WLW are connected to the nonvolatile memory circuits 2 arranged in the same row. In the nonvolatile memory device 3 configured as described above, an arbitrary nonvolatile memory circuit 2 in the memory cell array 2A can be selected by a column address and a row address to perform a write operation and a read operation.

  The operation of writing nonvolatile data can be performed once or a limited number of times, but can be performed simultaneously on all the memory cells (nonvolatile memory circuit 2). The content of the non-volatile data can also be freely set according to the pattern of light applied to the non-volatile memory device 3. The nonvolatile data read operation can be performed any number of times, and can be performed simultaneously on all the memory cells (nonvolatile memory circuit 2).

  As described above, according to the semiconductor nonvolatile memory circuit and device of the present invention, no special process is required in the manufacturing process, and the manufacturing cost of the nonvolatile memory device or the logic integrated circuit in which the nonvolatile memory is embedded is reduced. Can be made. In addition, for writing non-volatile data, any storage information can be optically set and electrically written without requiring a dedicated interface circuit or the like.

  Thereby, it is possible to write nonvolatile data at high speed in the manufacturing process of the memory device. An optical exposure apparatus can be used for optical setting of nonvolatile data. For this reason, the manufacturing cost of the semiconductor nonvolatile memory circuit and device and the writing cost of nonvolatile data can be reduced.

  Needless to say, the present invention is not limited to the above-described embodiment, and can be applied to various modifications without departing from the scope of the claims.

  According to the semiconductor nonvolatile memory circuit and apparatus of the present invention, it is possible to write arbitrarily stored information optically without writing a dedicated interface circuit or the like for writing nonvolatile data. . For this reason, the manufacturing cost of the semiconductor nonvolatile memory circuit and device and the writing cost of nonvolatile data can be reduced.

It is a circuit diagram which shows the structure of the non-volatile memory circuit 1 of this invention. It is a timing chart at the time of taking in nonvolatile data. 6 is a timing chart at the time of nonvolatile data writing operation. 6 is a timing chart during a nonvolatile data read operation. It is a circuit diagram which shows the structure of the non-volatile memory circuit 2 which added the transfer gate. 2 is a block configuration diagram of a nonvolatile memory device 3 including a nonvolatile memory circuit 2. FIG. 3 is a diagram showing a main part of a nonvolatile memory device 3. FIG. It is a circuit diagram of a memory cell of a conventional EEPROM. It is a figure which shows the structure of the transistor 90 of EEPROM. It is a figure which shows the operation | movement which writes information in the memory cell of EEPROM. It is a figure which shows the operation | movement which erase | eliminates the memory information of the memory cell of EEPROM. 6 is a diagram illustrating a circuit configuration of a nonvolatile memory circuit disclosed in Patent Document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Non-volatile memory circuit 3 Non-volatile memory device 4 Sense amplifier / column selector 5 Low signal driver 9 Non-volatile memory circuit 20 Flip-flop 21, 22 Inverter 2A Memory cell array 41, 42 Photodiode 11, 12, 31, 32 Transistor

Claims (6)

A flip-flop (20) comprising a first inverter (21) and a second inverter (22);
A first MIS transistor (11) connected between a non-inverting output terminal (C) of the flip-flop (20) and a ground line (GND);
A second MIS transistor (12) connected between the inverting output terminal (C_) of the flip-flop (20) and the ground line (GND);
A nonvolatile memory circuit comprising a write word line (WLW) connected to the gates of the first MIS transistor (11) and the second MIS transistor (12),
A first photodiode (41) connected between the non-inverting output terminal (C) of the flip-flop (20) and the ground line (GND);
A semiconductor nonvolatile memory circuit comprising: a second photodiode (42) connected between the inverting output terminal (C_) of the flip-flop (20) and the ground line (GND). A semiconductor nonvolatile memory circuit according to claim 1,
The semiconductor nonvolatile memory circuit, wherein the first photodiode (41) and the second photodiode (42) receive light of different intensities when writing nonvolatile data. A semiconductor nonvolatile memory circuit according to claim 2,
The first MIS transistor (11) and the second MIS transistor (12) are capable of irreversibly changing a threshold voltage due to a hot carrier effect when writing nonvolatile data. Semiconductor non-volatile memory circuit. A driver circuit (4, 5) for reading and writing information by selecting an arbitrary memory cell;
A first bit line (BL) and a second bit line (BL_) provided in the driver circuit (4, 5);
A word line (WL) provided in the driver circuit (4, 5);
A write word line (WLW) provided in the driver circuit (4, 5);
A plurality of nonvolatile memory circuits (2) are arranged and connected to the first bit line (BL), the second bit line (BL_), the word line (WL), and the write word line (WLW). A semiconductor non-volatile memory device comprising the memory cell array (2A),
The nonvolatile memory circuit (2)
A flip-flop (20) comprising a first inverter (21) and a second inverter (22);
A first MIS transistor (11) whose source-drain is connected to the non-inverting output terminal (C) of the flip-flop (20) and the ground line (GND) and whose gate is connected to the write word line (WLW). )When,
A second MIS transistor (12) whose source-drain is connected to the inverting output terminal (C_) of the flip-flop (20) and the ground line (GND) and whose gate is connected to the write word line (WLW). )When,
A first photodiode (41) connected between the non-inverting output terminal (C) of the flip-flop (20) and the ground line (GND);
A non-volatile semiconductor comprising the second photodiode (42) connected between the inverting output terminal (C_) of the flip-flop (20) and the ground line (GND) Memory device. A semiconductor nonvolatile memory device according to claim 4,
The semiconductor nonvolatile memory device, wherein the first photodiode (41) and the second photodiode (42) receive light of different intensities when writing nonvolatile data. A semiconductor nonvolatile memory device according to claim 5,
The first MIS transistor (11) and the second MIS transistor (12) are capable of irreversibly changing a threshold voltage due to a hot carrier effect when writing nonvolatile data. Semiconductor non-volatile memory device.

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