WO2009119658A1 - Nonvolatile semiconductor memory element and semiconductor device - Google Patents

Abstract

Disclosed is a semiconductor device provided with: a storage part which stores one bit of information by means of a first nonvolatile semiconductor memory element and a second nonvolatile semiconductor memory element which stores the logical inverse of the bit of information stored in the first nonvolatile semiconductor memory element; and a sensor which, through a first signal wire and second signal wire which form a pair, reads the bit stored in the first and second nonvolatile semiconductor memory elements. The semiconductor device is characterized in that the first and second nonvolatile semiconductor memory elements each comprise at least a floating gate, a drain, and a source formed on top of a semiconductor substrate. The semiconductor device is further characterized by being configured so that: writing is performed by applying a voltage between the source and the drain, thereby injecting and accumulating charge in the floating gate; and erasure is performed by applying a voltage between the semiconductor substrate and either the source or the drain, thereby generating band-band hot carriers in the semiconductor substrate, and erasing the charge accumulated in the floating gate by means of the hot carriers.

Description

Nonvolatile semiconductor memory device and semiconductor device

The present invention relates to a nonvolatile semiconductor memory element and a semiconductor device which can be rewritten with a single-layer polysilicon cell structure which can be manufactured by a standard CMOS (complementary metal-oxide semiconductor) process.
This application claims priority on March 25, 2008 based on Japanese Patent Application No. 2008-079058 filed in Japan, the contents of which are incorporated herein by reference.

Nonvolatile semiconductor memories represented by EEPROM (Electrically-Erasable-Programmable-Read-Only Memory) have been used in many applications because information does not disappear even when the power is turned off. For example, a typical application of an EEPROM is an IC card. Also, EEPROM and flash memory are used as a replacement for the mask ROM in the microcomputer because it can be rewritten at any time according to the application. Furthermore, in recent years, there has been a need for a so-called embedded memory (embedded memory) in which a nonvolatile semiconductor memory is incorporated in a part of a system LSI or logic IC. Furthermore, a small-sized non-volatile semiconductor memory of about several hundred bits to several K bits is also required as an adjustment switch that is incorporated in an analog circuit and performs tuning and the like of a high-precision analog circuit.

However, a non-volatile semiconductor memory generally has a cell structure using two-layer polysilicon or three-layer polysilicon, and the manufacturing process is more complicated and requires more manufacturing processes than the standard CMOS logic process. Attempting to embed them in the chip at the same time has caused many problems in the manufacturing process, yield decreases, and the product price (cost) increases.

As one means for solving this problem, an EEPROM using one-layer polysilicon has been proposed. (Patent Document 1). If this one-layer polysilicon EEPROM is used, the number of manufacturing steps can be reduced as compared with the conventional two-layer polysilicon process.
JP-A-10-289959

However, in the above technique, since the second-layer polysilicon used as the control gate is omitted, it is necessary to embed a control gate made of a diffusion layer under the floating gate, which is more complicated than the standard CMOS process used in logic. It becomes a difficult manufacturing process. Furthermore, if the diffusion layer embedded at a high concentration is oxidized, an oxide film of poor quality is formed, and the probability of occurrence of a defect is high, and reliability is also a problem. In addition, writing and erasing are complicated, such as requiring a high voltage for writing.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-volatile semiconductor memory element having a single-layer polysilicon cell structure that can be manufactured by a standard CMOS process and a semiconductor device using the same.

In order to solve the above-described problems, the present invention provides a first nonvolatile semiconductor memory element, a second nonvolatile semiconductor memory element that stores information on a logic state opposite to the first nonvolatile semiconductor memory element, and , And a sense unit for reading out information stored in the first and second nonvolatile semiconductor memory elements via a pair of first signal line and second signal line. Each of the first and second nonvolatile semiconductor memory elements includes at least a floating gate, a drain, and a source formed on a semiconductor substrate, and the source is set in a write state. -A voltage is applied between the drain and the charge is injected into the floating gate and stored, and in the erased state, the charge is stored in the floating gate. When erasing the charged charge, a voltage is applied between the semiconductor substrate and the drain or source to generate hot carriers between the bands, and the charge accumulated in the floating gate is erased by the hot carriers. The semiconductor device is configured as described above.

According to the present invention, the first nonvolatile semiconductor memory element has a drain connected to the second signal line, a source connected to the first control signal terminal, and the second nonvolatile semiconductor memory element A drain connected to the first signal line, a source connected to a second control signal terminal, and a source of the first and second nonvolatile semiconductor memory elements connected to the first control signal terminal; The second control signal terminals are configured independently of each other, have different potentials at the time of writing and erasing, and respectively have a reference potential at the time of reading.

According to the present invention, the first nonvolatile semiconductor memory element has a drain connected to the second signal line, a source connected to the first control signal terminal, and the second nonvolatile semiconductor memory element The drain is connected to the first signal line, the source is connected to the first control signal terminal, and the first control signal terminal connected in common takes a predetermined potential at the time of erasing and writing to read Sometimes connected to a reference potential.

The present invention further includes first and second transistors, wherein the first nonvolatile semiconductor memory element has a drain connected to a source of the first transistor and a source connected to the first control signal terminal. The second nonvolatile semiconductor memory element has a drain connected to the source of the second transistor, a source connected to the first control signal terminal, and a gate connected to the activation signal input terminal of the first transistor. , The drain is connected to the second signal line, the source is connected to the drain of the first nonvolatile semiconductor memory element, the second transistor has a gate connected to the activation signal input terminal and a drain connected to the first signal line. The first control signal terminal connected in common to the signal line is connected to the drain of the second nonvolatile semiconductor memory element, and is connected during erasing and writing The first and second non-volatile transistors are turned on by the activation signal input to the activation signal input terminal, and the first and second transistors are turned on by the activation signal input to the activation signal input terminal. When the charge stored in the floating gate is erased with the conductive semiconductor memory device in the erased state, a voltage is applied between the semiconductor substrate and the drain or source to generate hot carriers between the bands between the semiconductor substrate and the semiconductor substrate. The electric charge accumulated in the floating gate is erased by the hot carriers.

The present invention further includes first and second resistors, wherein the first nonvolatile semiconductor memory element has a drain connected to the second signal line and a source connected to the first resistor via the first resistor. The second nonvolatile semiconductor memory element has a drain connected to the first signal line and a source connected to the first control signal terminal via a second resistor, The control signal terminal S has a predetermined potential at the time of erasing and writing, and is a reference potential at the time of reading.

The present invention further includes first and second transistors, wherein the first nonvolatile semiconductor memory element has a drain connected to the second signal line and a source connected to the drain of the first transistor, In the second nonvolatile semiconductor memory element, a drain is connected to the first signal line, a source is connected to a drain of the second transistor, and a gate of the first transistor is connected to an input terminal of an activation signal. The source is connected to the first control signal terminal, and the second transistor has a gate connected to an input terminal of an activation signal, a source connected to the first control signal terminal, and an input of the activation signal. The first and second transistors are activated, and the first control signal terminal takes a predetermined potential during erasing and writing, and becomes a reference potential during reading. The features.

In the present invention, the sense unit includes a flip-flop circuit in which a power supply line is connected via a power transistor and holds a signal, and the flip-flop circuit includes an on state and an off state of the power transistor. Is controlled so that a voltage is applied to the power supply to hold output signals from the first and second nonvolatile semiconductor memory elements.

According to the present invention, the sense unit is connected to a power source through a power transistor, and is connected to a reference potential through a ground transistor, and the memory unit and the pair of first and second signal lines And a signal amplifier for amplifying an output signal from the flip-flop circuit.

The present invention is a semiconductor device including a memory cell in which the storage unit and the sense unit are combined, and includes at least a matrix array in which the memory cells are arranged in a row and a column direction, and a sense amplifier. Each of the memory cells is connected to a power supply through a power supply transistor, and a storage unit including first and second nonvolatile semiconductor memory elements including at least a floating gate, a drain, and a source formed on a semiconductor substrate. A flip-flop circuit for holding a signal, and the first and second nonvolatile semiconductor memory elements are arranged between the semiconductor substrate and the drain or source when erasing charges accumulated in the floating gate. A voltage is applied to generate hot carriers between the bands in the semiconductor substrate. And the charge stored in the floating gate is erased by the hot carriers, and the flip-flop circuit controls the on / off state of the power supply transistor by an activation signal. A sense unit configured to apply power to the circuit; a source line connecting the sources of the first and second nonvolatile semiconductor memory elements for each row; a selection signal for the sense unit and the activation signal; And a bit line for transmitting information of the sense unit for each column, and the sense amplifier connects a signal output from the sense unit to the bit line for each column. And the charge accumulated in the floating gate of the nonvolatile semiconductor memory device specified by the bit line and the row line. Characterized in that it comprises a reading means for reading information stored me.

The present invention is a semiconductor device including a memory cell in which the storage unit and the sense unit are combined, and includes at least a matrix array in which the memory cells are arranged in a row and a column direction, and a sense amplifier. Each of the memory cells includes a first and second nonvolatile semiconductor memory elements each including at least a floating gate, a drain, and a source formed on a semiconductor substrate, and each of the first and second nonvolatile semiconductor memory elements. A storage unit including a first transistor and a second transistor which are connected in series to control selection or non-selection of the first and second nonvolatile semiconductor memory elements by being turned on or off, and a power source A sense unit comprising a sense unit for holding a signal by a flip-flop circuit connected to a power supply via a transistor The first and second transistors are turned on, a voltage is applied between the source and drain of the first and second nonvolatile semiconductor memory elements to inject charges into the floating gate and accumulate, When erasing charges accumulated in the floating gates of the first and second nonvolatile semiconductor memory elements, a voltage is applied between the semiconductor substrate and the drains or sources of the first and second nonvolatile semiconductor memory elements. A non-volatile semiconductor memory device configured to generate hot carriers between bands in the semiconductor substrate and erase charges accumulated in the floating gate by the hot carriers, and the flip-flop circuit has power control To control the on / off state of the power supply transistor to control the flip-flop. A sense unit configured to apply power to a logic circuit, a source line connecting the sources of the first and second nonvolatile semiconductor memory elements for each row, and gates of the first and second transistors A control signal that controls the activation signal, a row line that transmits the selection signal of the sense unit for each row, and a bit line that transmits the information of the sense unit for each column, and the sense amplifier includes: A signal output from a sense unit is connected to the bit line for each column, and the nonvolatile semiconductor memory element and the sense unit can be selectively cut off by a signal input to the row line. Readout means for reading out information stored in accordance with the state of electric charge accumulated in the floating gate of the nonvolatile semiconductor memory element designated by the row line is provided.

According to another aspect of the present invention, there is provided a storage unit including a first nonvolatile semiconductor memory element and a second nonvolatile semiconductor memory element having a logic state opposite to the first nonvolatile semiconductor memory element; A signal holding unit having a signal input terminal and comprising a sense circuit that reads information from the storage unit by an input activation signal, and a flip-flop circuit that holds and outputs the information read by the sense circuit; A precharge unit that charges the signal holding unit when reading information from the storage unit; and an amplification detection unit that amplifies and outputs a signal output from the signal holding unit, and the first and second The nonvolatile semiconductor memory element includes a floating gate, a drain, and a source formed on a semiconductor substrate, each source being the first control signal terminal. In a transistor configuration to be connected, a voltage is applied between the source and the drain in a writing state to inject and accumulate charges in the floating gate, and an erasing state erases the charges accumulated in the floating gate. Sometimes, a voltage is applied between the semiconductor substrate and the drain or source, hot carriers between bands are generated in the semiconductor substrate, and charges accumulated in the floating gate are erased by the hot carriers. It is characterized by being.

In addition, the present invention provides a first nonvolatile semiconductor memory element, a storage unit including a second nonvolatile semiconductor memory element having a logic state opposite to the first nonvolatile semiconductor memory element, and a pair of A signal holding unit that is connected to the storage unit via first and second signal lines and holds and outputs information read from the storage unit by a flip-flop circuit having an activation circuit, and The first and second nonvolatile semiconductor memory elements have a transistor configuration including a floating gate, a drain, and a source formed on a semiconductor substrate, and each source is connected to the first control signal terminal. As a state, a voltage is applied between the source and drain to inject charges into the floating gate for accumulation, and an erase state is set. When erasing charges accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source to generate hot carriers between bands between the semiconductor substrate and the floating gate by the hot carriers. The first nonvolatile semiconductor memory element has a drain connected to the first signal line, a source connected to the first control signal terminal, and the second nonvolatile semiconductor memory element. In the nonvolatile semiconductor memory device, the drain is connected to the second signal line, the source is connected to the first control signal terminal, and the control signal terminal S connected in common is predetermined when erasing and writing. The potential is taken and becomes a reference potential at the time of reading, and the signal holding unit is connected to the power supply side of the flip-flop circuit. Providing the activating circuit comprises a static, characterized.

The present invention also provides a first nonvolatile semiconductor memory element, a second nonvolatile semiconductor memory element having a logic state opposite to the first nonvolatile semiconductor memory element, and a first nonvolatile semiconductor memory. The memory unit includes a first transistor connected in series with the element and a second transistor connected in series with the second nonvolatile semiconductor memory element, and a flip-flop circuit including an activation circuit. And the first and second nonvolatile semiconductor memory elements include a floating gate, a drain, and a source formed on a semiconductor substrate, each source being the first control signal terminal In the writing state, a voltage is applied between the source and drain to charge the float. A voltage is applied between the semiconductor substrate and the drain or source when erasing charges stored in the floating gate as an erased state while being injected into the gate and accumulated, and hot carriers due to band-to-band are transferred to the semiconductor substrate. The storage unit is configured to erase the electric charge generated in the floating gate by the hot carriers, and the storage unit includes a first nonvolatile semiconductor memory element, and a drain is connected via the second signal line. The high-speed sense amplifier has a source connected to the drain of the first transistor, and the second nonvolatile semiconductor memory element has a drain connected to the high-speed sense amplifier via the first signal line and a source connected to the second transistor. The first transistor has a gate connected to an activation signal input terminal and a source connected to the first transistor. The second transistor has a gate connected to an activation signal input terminal, a source connected to the first control signal terminal, and the first control signal terminal at the time of erasing and It takes a predetermined potential during writing and becomes a reference potential during reading. The signal holding unit includes an activation circuit including a power transistor connected to the power source side of the flip-flop circuit, and the signal holding unit includes the activation potential The information stored in the non-volatile semiconductor memory element is amplified and detected by a control signal supplied to the control circuit, and the read information is held and output.

According to the present invention, in the semiconductor device according to the present invention, a first nonvolatile semiconductor memory element and a second nonvolatile semiconductor memory element having a logic state opposite to the first nonvolatile semiconductor memory element are provided. The first and second nonvolatile semiconductor memory elements include at least a floating gate, a drain, and a source formed on a semiconductor substrate, and a voltage is applied between the source and drain in a writing state. Apply and inject charge into the floating gate for accumulation, and in the erased state, when erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source, and band-to-band Generated in the semiconductor substrate, and the flow by the hot carrier Information stored in the first and second nonvolatile semiconductor memory elements via a pair of first signal line and second signal line configured to erase charges accumulated in the scanning gate It was decided to provide a sense unit for reading out.

Thereby, in order to omit the process of embedding the control gate by the diffusion layer below the floating gate, which is required by eliminating the need for the second-layer polysilicon process by not providing a gate signal input, A voltage is applied between the source and drain to inject and accumulate charges in the floating gate, and in the off state, a voltage is applied between the semiconductor substrate and the drain or source when erasing the charges accumulated in the floating gate. A non-volatile semiconductor memory device can be configured to generate hot carriers between bands in a semiconductor substrate and to erase charges accumulated in the floating gate by the hot carriers, using a standard logic CMOS process. And a semiconductor device using the same, The logic embedded memory easily, also can be realized inexpensively.

It is a figure which shows embodiment of the non-volatile semiconductor memory element by this invention. It is a figure which shows embodiment of the non-volatile semiconductor memory element by this invention. It is a figure which shows embodiment of the non-volatile semiconductor memory element by this invention. FIG. 2 is a diagram showing an equalization circuit according to the embodiment of FIGS. 1A to 1C. FIG. 2 is a diagram for explaining characteristics of the embodiment of FIGS. 1A to 1C. FIG. 2 is a diagram for explaining the operation of the embodiment of FIGS. 1A to 1C. FIG. 2 is a diagram for explaining the operation of the embodiment of FIGS. 1A to 1C. FIG. 2 is a diagram showing a configuration of an embodiment (Embodiment 1) of the nonvolatile semiconductor memory element of FIGS. 1A to 1C. FIG. 2 is a diagram showing a configuration of an embodiment (Embodiment 1) of the nonvolatile semiconductor memory element of FIGS. 1A to 1C. FIG. 6 is a diagram for explaining the operation of the embodiment of FIGS. 5A and 5B in the first embodiment. 6 is a diagram showing a configuration of an application example of a nonvolatile semiconductor memory element in Embodiment 2. FIG. 6 is a diagram showing a configuration of an application example of a nonvolatile semiconductor memory element in Embodiment 2. FIG. 6 is a diagram showing a configuration of an application example of a nonvolatile semiconductor memory element in Embodiment 2. FIG. 7 is a diagram showing a case where a matrix array is configured using the embodiment of FIGS. 7A to 7C in Embodiment 3. FIG. 6 is a diagram showing a configuration of an application example of a nonvolatile semiconductor memory element in Embodiment 4. FIG. It is a figure which shows the case where a matrix array is comprised using Embodiment of FIG. 9 in Embodiment 5. FIG. FIG. 16 is a diagram illustrating a configuration of an application example of a nonvolatile semiconductor memory element in a sixth embodiment. It is a figure for demonstrating the operation | movement of embodiment of FIG. 11 in Embodiment 6. FIG. FIG. 16 is a diagram illustrating a configuration of an application example of a nonvolatile semiconductor memory element in a seventh embodiment. It is a figure for demonstrating the operation | movement of embodiment of FIG. 13 in Embodiment 7. FIG. FIG. 16 is a diagram illustrating a configuration of an application example of a nonvolatile semiconductor memory element in an eighth embodiment. FIG. 25 is a diagram showing a configuration of an application example of a nonvolatile semiconductor memory element in Embodiment 9. It is a figure for demonstrating the operation | movement of embodiment of FIG. 16 in Embodiment 9. FIG. FIG. 32 is a diagram illustrating a configuration of an application example of a nonvolatile semiconductor memory element in a tenth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... SRAM part 200 ... Memory | storage part 101,102,103 ... PMOS transistor 104,105 ... NMOS transistor 106,107 ... Transfer gate NMOS transistor

Embodiments of the present invention will be described below with reference to the drawings.
[Operating principle]
1A is a plan view of one transistor constituting the nonvolatile semiconductor memory element used in the embodiment of the present invention, FIG. 1B is a cross-sectional view of FIG. 1A, and FIG. 1C is an equivalent circuit diagram of FIG. 1A. Indicates. 1A to 1C includes a floating gate FG, a drain D, and a source S formed on a semiconductor substrate SUB (potential Vsub) using a single-layer polysilicon cell structure. This floating gate FG serves as a charge holding region, no electrode is provided, and a floating gate FG made of polysilicon is formed on a gate insulating layer formed on the substrate SUB.
The drain D and the source S are diffusion regions formed on the substrate SUB, and electrodes are provided through contacts.

FIG. 2 shows an equivalent circuit of the coupling system of the nonvolatile semiconductor memory device shown in FIGS. 1A to 1C. If there is a charge Q in the floating gate FG, the total charge of this system is Q.

It becomes. However, VFG, VD, VS, and Vch are the potential of the floating gate FG, the potential of the drain D, the potential of the source S, and the potential of the channel CH, respectively. C (FB) is a capacitance between the floating gate FG and the substrate SUB, C (FD) is a capacitance between the floating gate FG and the drain D, C (FS) is a capacitance between the floating gate FG and the source S, and C (FC ) Is a capacitance between the floating gate FG and the channel CH. If the total capacity is defined as CT (total),

And

It becomes. However, Q / CT represents a potential when charge is injected into the floating gate. Here, when Vsub = 0V (reference potential, the same applies hereinafter),

It becomes. Here, the ratio of the capacities varies somewhat depending on the process, but is roughly about C (FD): C (FS): C (FC) = 0.1: 0.1: 0.8.
Here, if the charge amount in the floating gate FG is Q / CT = −ΔVFG, CT = 1,

It becomes.

Here, erasing of the nonvolatile semiconductor memory device of FIGS. 1A to 1C will be described. The threshold value of the channel CH of the transistor constituting this nonvolatile semiconductor memory element is 0.5V. Erasing is performed with VD = 8V and VS = open (open). Since the source is open, a depletion layer spreads in the channel CH portion of this transistor, and the capacitance between the floating gate FG and the substrate SUB becomes very small. If neglected, the floating gate potential VFG (Erase) at the time of erasing is ΔVFG = 0,

It becomes. When a voltage is applied to the drain D, as shown in FIG. 4A, first, an electric field concentration in the depletion layer occurs in the vicinity of the drain D, and a so-called high energy band-to-band (BtoB) current flows. The pair occurs. When some holes with high energy (hot carriers) are taken into the floating gate FG and the voltage is further increased, if the oxide film is relatively thick, before the tunnel current of Fowler-Nordheim flows A junction breakdown occurs and a large current flows through the substrate SUB. This breakdown voltage is assumed to be VBD.

For details of the band-to-band (BtoB) current, refer to “Reference:“ Flash Memory Technology Handbook ”, Editor: Fujio Takaoka, Publisher: Science Forum Inc., August 15, 1993, 1st edition, 1st edition issued. See Chapter 5, Section 2, Analysis of Band-to-Band Tunneling in Nonvolatile Memory Cells, pages 206-215. FIG. 4A schematically shows the change in the drain current ID when the drain potential VD is changed with the horizontal axis being the drain potential VD and the vertical axis being the drain current ID, using the floating gate potential VFG as a parameter. .

Here, since BtoB and breakdown occur in a certain electric field, it depends on the potential of the floating gate FG. As shown in FIG. 4A, VBD is low when VFG is low, and VBD is high when VFG is high.

Deletion of charge accumulated in the floating gate will be described.
Assuming that the limit potential at which BtoB occurs in the potential difference between the gate and drain is 5V, when VD = 8V, the floating gate potential VFG is erased until it reaches 3V. In other words, hot carriers are injected. Since the initial VFG is 0.8V, when it becomes 3V after erasure, the change amount ΔVFG (E) at the time of erasure becomes + 2.2V.

On the other hand, writing is performed with VD = 5V and VS = 0V. At this time, if the state before writing is a normal erasing state and a hole is in the floating gate FG, this transistor is in an on state, so that the channel operates in the saturation region. Therefore, assuming that the channel area is about half, the floating gate potential VFG (Program) at the time of writing is calculated from (Equation 1):

Thus, hot electrons are generated and writing is performed. Here, since the threshold value of this transistor is 0.5V, when the potential VFG of the floating gate FG becomes 0.5V, no current flows and writing is completed. At this time, since the gate voltage changes from 2.5 V to 0.5 V, the change amount ΔVFG (P) at the time of writing becomes −2.0 V.

With reference to FIG. 3, the transistor characteristics in the erased and written states will be described.
In this figure, the horizontal axis is the floating gate potential VFG, the vertical axis is the current ID of the drain D, and the change of the gate current ID when the floating gate potential VFG is changed in the three states of erase, neutral and write is schematically shown. It is a representation.

Next, reading will be described. Reading is performed with VD = 1V and VS = 0V. At this time, if the charge of ΔVFG is in the floating gate FG, the floating gate potential VFG (Read) at the time of reading is

It becomes. In the case of “0” reading, since the channel is off, Vch = 0V, and the floating gate potential VFG (“0”) at the time of “0” reading is

It becomes. On the other hand, in the case of “1” reading, since the channel is on, Vch = 1V, and the floating gate potential VFG (“1”) at the time of “1” reading is

It becomes.
In the case of “0” reading, since electrons are injected into the floating gate FG by −Δ2.0 V at the time of writing, the floating gate potential VFG (“0”) at the time of “0” reading is calculated from (Equation 4-1). )

It becomes. On the other hand, in the case of “1” reading, the floating gate FG includes Δ2.2V in the floating gate FG at the time of erasing, so that the floating gate potential VFG at the time of “1” reading (“1”) )

It becomes. FIG. 4B summarizes the operation of this nonvolatile semiconductor memory element. Note that the operations of the drain and the source can be reversed.

[Embodiment 1]
5A and 5B show Embodiment 1 which is an application example of the nonvolatile semiconductor memory element described with reference to FIGS. 1A, 1B, and 1C.
The memory cell includes a storage unit 200 including an SRAM unit 100 (sense unit), a nonvolatile semiconductor memory element 201 (first nonvolatile semiconductor memory element), and 202 (second nonvolatile semiconductor memory element). Prepare.
The SRAM unit 100 is for sensing and latching data in the storage unit 200, and the storage unit 200 is a writable / erasable storage unit.
The SRAM unit 100 activates the SRAM unit 100 and receives an activation signal (SET) for sensing / determining data in the storage unit 200, and PMOS transistors 102 and 103 constituting a latch unit. NMOS transistors 104 and 105, and transfer gate NMOS transistors 106 and 107 for reading data of the memory cells to the outside.
The storage unit 200 includes nonvolatile semiconductor memory elements 201 and 202, and stores data indicating the opposite logic.

The connection between the SRAM unit 100 and the storage unit 200 will be described.
In the SRAM unit 100, the transistor 102 and the transistor 104, and the transistor 103 and the transistor 105 are connected as inverters, respectively. The two inverters are connected to form a flip-flop circuit.
That is, the transistor 102 has a gate connected to the gate of the transistor 104 and a source connected to the drain of the transistor 104.
The source of the transistor 104 is connected to the reference potential.
The transistor 103 has a gate connected to the gate of the transistor 105 and a source connected to the drain of the transistor 105.
The transistor 105 has a gate connected to the source of the transistor 102, a drain connected to the gate of the transistor 102, and a source connected to a reference potential.

A power supply terminal of the flip-flop circuit formed by the combination of the inverters is connected to the power supply via the transistor 101. That is, the transistor 101 has a gate connected to the input terminal of the activation signal SET, a drain connected to the power supply, and a source connected to the drains of the transistors 102 and 103.
Further, the transistor 106 and the transistor 107 are connected to the word line WL, the data line DL, and the data line inversion signal line DLB.
The transistor 106 has a gate connected to the word line WL, a drain connected to the data line DL, and a source connected to the source of the transistor 102.
The transistor 107 has a gate connected to the word line WL, a drain connected to the data line inversion signal line DLB, and a source connected to the source of the transistor 103.

Nonvolatile semiconductor memory elements 201 and 202 of the storage unit 200 are connected to the SRAM unit 100 via signal lines Bit and BitB.
The nonvolatile semiconductor memory element 201 has a source connected to the control signal terminal S and a drain connected to the gate terminal of the transistor 102 of the SRAM unit 100 via the signal line BitB.
The nonvolatile semiconductor memory element 202 has a source connected to the control signal terminal SB and a drain connected to the gate terminal of the transistor 103 of the SRAM unit 100 via the signal line Bit.

The operation of the storage unit 200 will be described with reference to FIG. 5B.
FIG. 5B shows a write operation, an erase operation, and a read operation in order.
During a write operation, when a 2 V potential is input to the word line WL, the input terminal for the activation signal SET, and the data line DL, and a 0 V potential is input to the data line inversion signal line DLB, the transfer transistors 106 and 107 are used. The potential of the data line DL and the data line inversion signal line DLB is transmitted to the signal lines Bit and BitB, the potential of the signal line Bit is about 1V, and the potential of the signal line BItB is 0V.
At this time, when potentials of S = 5 V and SB = 8 V are applied to the control signal terminal S and the control signal terminal SB, respectively, the nonvolatile semiconductor memory element 201 is in a writing state and the nonvolatile semiconductor memory element 202 is in an erasing state. Electrons are injected into the floating gate of the volatile semiconductor memory device 201, and holes are injected into the floating gate of the nonvolatile semiconductor memory device 202.

On the other hand, during the erase operation, when a potential of 0V is applied to the data line DL and a potential of 2V is applied to the data line inversion signal line DLB, the potential of the signal line Bit is set to 0V via the transfer transistors 106 and 107. The potential of BitB becomes 1V.
At this time, when potentials of S = 8V and SB = 5V are applied to the control signal terminal S and the control signal terminal SB, respectively, the nonvolatile semiconductor memory element 201 is in an erased state and the nonvolatile semiconductor memory element 202 is in a written state. .

With reference to FIG. 6, the operation of reading data set in the storage unit 200 will be described.
FIG. 6 is a timing chart showing a read operation of the storage unit 200.
FIG. 6 shows the change in voltage of each signal line of the activation signal SET, the word line WL, the signal line Bit, BitB, the data line DL, and the data line inversion signal line DLB with time.

An example of the case where writing to the storage unit 200 is performed, that is, the case of reading “0” data is shown.
First, the voltage of the data line DL and the data line inversion signal line DLB is charged (precharged) to 2V in advance.
The terminal voltage of the input terminals of the control signal terminal S and the control signal terminal SB is S = SB = 0V.
When the terminal voltage of the input terminal of the activation signal SET is gradually changed from 2V to 0V from time t11, the potential of the activation signal SET gradually changes from 2V to 0V. Thereby, the SRAM unit 100 is activated, the signal lines Bit and BitB are charged, and the voltages of the signal lines Bit and BitB gradually increase.
Since “0” data is written in the storage unit 200, the nonvolatile semiconductor memory element 201 is in an off state and the nonvolatile semiconductor memory element 202 is in an on state. Thereby, the potential of the signal line Bit is pulled to the “L (Low)” level side, the potential of the signal line BitB is charged, the signal line Bit is “0”, and the B signal line BitB is “1”. "(Time t12).
When the voltage of the word line WL is set to 2V at time t13, the transfer transistors 106 and 107 are turned on, the voltage of the data line DL is set to 0V, the voltage of the data line inversion signal line DLB is set to 2V, and the read operation is finished.

When the storage unit 200 is erased, that is, when “1” data is read, the signal indicating the state indicates the reverse operation, the voltage of the signal line Bit is 2 V, and the voltage of the signal line BitB Is 0V, the voltage of the data line DL is 2V, the voltage of the data line inversion signal line DLB is 0V, and the read operation is completed.

The sense period is from the time when the terminal voltage of the input terminal of the activation signal SET starts to change from “H” to “L” until the voltage of the data line DL and the data line inversion signal line DLB is determined, that is, from time t11 to t13. It becomes.

The merit of this configuration is that the configuration can be simplified. The high voltage is applied to the portions connected to the control signal terminal S and the control signal terminal SB of the nonvolatile semiconductor memory elements 201 and 202, and the high voltage is applied to the SRAM unit 100 (sense unit). Therefore, a fine process can be adopted for the sense portion.
For example, the SRAM unit 100 (sense unit) uses a 65 μm process in the logic standard process, and the nonvolatile semiconductor memory elements 201 and 202 use an I / O transistor process (usage voltage 3 to 5 V, actual withstand voltage 8 V in the logic standard process). By adopting (˜9V), a simple and minute non-volatile memory can be provided.

[Embodiment 2]
7A, 7B, and 7C show a second embodiment that is a modified form of the first embodiment.
FIG. 7A is a block diagram according to the second embodiment.
The parts changed in the second embodiment will be described, and parts not changed are denoted by the same reference numerals and the description thereof will be omitted.
The SRAM unit 100 (sense unit) shown in the first embodiment is the same, but the storage unit 200 includes a nonvolatile semiconductor memory element 201 (first nonvolatile semiconductor memory element) and 202 (second nonvolatile semiconductor memory). The source of the element) is set separately for the control signal terminal S and the control signal terminal SB. However, in the storage unit 200a of the present embodiment, the sources of the nonvolatile semiconductor memory elements 201 and 202 are the common control signal. Connect to terminal S.

When using a common source, it is necessary to optimize the control signal terminal voltage VS to achieve both the write operation and the erase operation.

FIGS. 7B and 7C show an example in which the applied voltage of the control signal terminal voltage VS is changed.
FIG. 7B shows a case where the control signal terminal voltage VS is 7V.
Again, (Formula 2), (Formula 3), (Formula 4-1), and (Formula 4-2) are confirmed. Here, since the drain and the source are interchanged, VS enters instead of VD.

The initial state of the floating gate FG at the time of erasing is from (Equation 2)

Thus, the final state of the floating gate FG is 7V-5V = 2V, and the amount of change is + 1.3V.
Also, the initial state of the floating gate FG at the time of writing is from (Equation 3):

In the final state, erasure starts with FG = 2V. Therefore, when FG = 2V, the amount of change is + 1.5V.
Therefore, the initial state of the “0” read floating gate FG is as follows:

It becomes.
Further, the initial state of the floating gate FG for “1” reading is expressed by (Equation 4-2):

It becomes.
As a result, the threshold value of the nonvolatile semiconductor memory elements 201 and 202 is 0.5 V, so that it can operate sufficiently.

FIG. 7C shows a case where the control signal terminal voltage VS is 6V.
The initial state of the floating gate FG at the time of erasing is from (Equation 2)

Thus, since the final state of the floating gate FG is 6V-5V = 1V, the amount of change is + 0.4V.
Also, the initial state of the floating gate FG at the time of writing is from (Equation 3):

In the final state, erasure starts with FG = 1V. Therefore, when FG = 1V is reached, the amount of change is −2.0V.
Therefore, the initial state of the “0” read floating gate FG is as follows:

It becomes.
Further, the initial state of the floating gate FG for “1” reading is expressed by (Equation 4-2):

It becomes.
As a result, the threshold value as the nonvolatile semiconductor memory elements 201 and 202 is 0.5 V, so that the margin for the “1” read operation becomes strict (the permissible read range is narrow). However, in this case, reading is possible if the threshold values of the nonvolatile semiconductor memory elements 201 and 202 are set to around 0V.
Thus, when the source is shared, there is an optimum voltage in the vicinity of VS = 6V to 7V.

[Embodiment 3]
FIG. 8 shows still another embodiment 3.
In the present embodiment, a plurality of memory cells of the second embodiment are arranged in a matrix to form a memory array cell. That is, each of the memory cells M11 to Mmn is a memory cell including the SRAM unit 100 (sense unit) and the storage unit 200a, and the details of the inside are as described in the second embodiment. Parts that are not changed are denoted by the same reference numerals, and description thereof is omitted with reference to the second embodiment.

The memory cell array includes (m × n) memory cells M11 to Mmn and n sense amplifiers 800-1 to 800-n.

Memory cells M11 to M1n are arranged with the word line WL1 in common, and memory cells Mm1 to Mmn are arranged with the word line WLm in common. Further, the data lines DL1 and DLB1 of M11 to Mm1 are connected in common, and the data lines DLn and DLBn of M1n to Mmn are connected in common.
Further, the sources are commonly connected in the word line direction, and become source lines S1 to Sm, respectively.
The terminal of the activation signal SET for activating the SRAM unit 100 is also connected by the gate lines SET1 to SETm in the word line direction.
The data lines DL1, DLB1 to DLn, DLBn are connected to sense amplifiers 800-1 to 800-n, respectively.

The word lines WL1 to WLm (row lines) are signal lines for supplying a selection signal for selecting each SRAM unit 100 connected to each row for each row of the SRAM unit 100.
Gate lines SET1 to SETm (row lines) are signal lines for supplying an activation signal SET for activating the SRAM unit 100 for each row of the SRAM unit 100.
The data lines DL1, DLB1 to DLn, DLBn are signal lines that transmit information read from the SRAM unit 100 or information to be written for each column.
The source lines S1 to Sm (lines) are signal lines that supply control signals for writing, erasing, and reading information in the storage unit 200a for each row.
In this array configuration, for example, the memory cells M11 to M1n selected by the word line WL1, the gate line SET1, and the source line S1 can be simultaneously written / erased or read, so-called page rewrite, page read is possible, and high-speed rewrite is possible. High-speed reading is possible.

[Embodiment 4]
FIG. 9 shows a fourth embodiment which is a modified form from the first embodiment.
The parts changed in the fourth embodiment will be described, and the same parts are denoted by the same reference numerals, and the description thereof will be omitted.
The SRAM unit 100 (sense unit) shown in the first embodiment is the same, but the storage unit 200 includes a nonvolatile semiconductor memory element 201 (first nonvolatile semiconductor memory element) and 202 (second nonvolatile semiconductor memory). In this embodiment, the source of the device is that the control signal terminal S and the control signal terminal SB are set separately, and the nonvolatile semiconductor memory devices 201 and 202 are directly connected to the SRAM unit 100. The storage unit 200b is different.
For the point of connecting the sources of the nonvolatile semiconductor memory elements 201 and 202 to the common control signal terminal S, refer to the description in the storage unit 200a shown in the second embodiment.

The storage unit 200b includes NMOS transistors 203 and 204 for data transfer between the SRAM unit 100 and the nonvolatile semiconductor memory elements 201 and 202.

The nonvolatile semiconductor memory element 201 has a drain connected to the source of the transistor 203 and a source connected to the control signal terminal S.
The nonvolatile semiconductor memory element 202 has a drain connected to the source of the transistor 204 and a source connected to the control signal terminal S.
The transistor 203 has a gate connected to the input terminal of the transfer signal TRF, and a drain connected to the SRAM unit 100 via the signal line BitB.
The transistor 204 has a gate connected to the input terminal of the transfer signal TRF, and a drain connected to the SRAM unit 100 via the signal line Bit.

A transfer signal TRF selected as “H” is input to the gates of the transistors 203 and 204 at the time of writing, erasing, and transferring data of the nonvolatile semiconductor memory elements 201 and 202 to the SRAM.
In this configuration, although the size of the memory cell is slightly increased, after the storage data is transferred to the SRAM unit, the transfer signal TRF is inputted with “L”, and the nonvolatile semiconductor memory elements 201 and 202 are transferred from the SRAM unit 100. Since they are disconnected, there is an advantage that no voltage is supplied to the drain, unnecessary voltage is not applied, and reliability is improved.

[Embodiment 5]
FIG. 10 shows still another embodiment 5.
The parts changed in the fifth embodiment will be described, and the parts that are not changed are denoted by the same reference numerals and the description thereof will be omitted by referring to the fourth embodiment.
In the present embodiment, memory cells MA11 to MAmn are used instead of the memory cells M11 to Mmn in the memory cell array shown in the third embodiment.
The memory cell array includes (m × n) memory cells MA11 to MAmn and n sense amplifiers 800-1 to 800-n.
The difference between the memory cells M11 to Mmn and the memory cells MA11 to MAmn is different in the form of the storage unit.
The memory cells M11 to Mmn include the SRAM unit 100 (sense unit) and the storage unit 200a. However, the memory cells MA11 to MAmn include the SRAM unit 100 (sense unit) and the storage unit 200b. That is, the memory cells included in the memory cells MA11 to MAmn have the same form as the memory cell shown in the fourth embodiment.

The parts changed in the fifth embodiment will be described, and the same parts are denoted by the same reference numerals, and the description thereof will be omitted by referring to the third and fourth embodiments.

In this mode, data stored in the memory cells MA11 to MAmn can be read at once.
For example, by setting the transfer signals TRF1 to TRFm for data transfer to “L”, the memory cells connected to the row line in which “L” is input to the transfer signals TRF1 to TRFm can be deselected. Thus, if the memory cell is separated from the SRAM unit 100, the memory can operate in the same manner as the SRAM unit 100 thereafter.
If data is transferred to all the memory cells at the same time, excessive current may flow due to excessive concentration of current flowing in the SRAM unit 100. In this case, the peak current can be suppressed by shifting the activation timings of the memory cells MA11 to MAmn by sequentially shifting the input timing of the activation signal SET to the input terminal of the activation signal SET.

[Embodiment 6]
FIG. 11 shows a sixth embodiment which is a modification of the second embodiment.
The parts changed in the sixth embodiment will be described, and the parts that are not changed are denoted by the same reference numerals and the description thereof will be omitted.
Instead of the SRAM unit 100 shown in the second embodiment, a high-sensitivity sense amplifier 300 (sense unit) is provided. The storage unit 200a is the same, and is connected to the high-sensitivity sense amplifier 300 via the signal lines Bit and BitB.

A high-sensitivity sense amplifier 300 provided instead of the SRAM unit 100 will be described.
The high-sensitivity sense amplifier 300 transfers (reads) precharge PMOS transistors 301 and 302, sense NMOS transistors 303 and 304, sense amplifier activation NMOS transistor 305, and sensed data to a data line. Transfer transistors 306 and 307 are provided.

The transistor 301 has a gate connected to the input terminal of the precharge signal PRE, a drain connected to the power supply, and a source connected to the signal line Bit.
The transistor 302 has a gate connected to the input terminal of the precharge signal PRE, a drain connected to the power supply, and a source connected to the signal line BitB.
The transistor 303 has a gate connected to the signal line BitB and the drain of the transistor 304, and a source connected to the drain of the transistor 305.
The transistor 304 has a gate connected to the signal line Bit and the drain of the transistor 303, and a source connected to the drain of the transistor 305.
The transistor 305 has a gate connected to an input terminal of a sense amplifier activation signal (hereinafter referred to as “sense signal SEN”), and a source connected to a reference potential.
The transistor 306 has a gate connected to the word line WL, a drain connected to the data line DL, and a source connected to the drain of the transistor 303.
The transistor 307 has a gate connected to the word line WL, a drain connected to the data line inversion signal line DLB, and a source connected to the drain of the transistor 304.

The operation will be described with reference to FIG.
This figure is a timing chart showing the operation of the configuration shown in FIG.
First, when “L” is input to the input terminal of the precharge signal PRE at time t21 and the precharge signal PRE becomes “L”, the transistors 301 and 302 are activated and the signal lines Bit and BitB are gradually charged. , “H”.
At this time, “L” is input to the input terminal of the sense signal SEN and the input terminal of the word line WL of the selection signal for transferring the sense data to the data line DL and the data line inversion signal line DLB, and the sense signal SEN and the word line The selection signal input to WL is “L”.
The data line DL and the data line inversion signal line DLB are also gradually charged to “H” in accordance with the signal lines Bit and BitB charged by the transistors 301 and 302.
The data line DL and the data line inversion signal line DLB are precharged at the same timing as the precharge signal PRE by a separately provided data line precharge circuit. As the data line precharge circuit, the precharge circuit 600 shown in the following embodiment can be applied. Details will be described later.

At time t22, “H” is input to the input terminal of the precharge signal PRE, and the precharge signal PRE becomes “H”. The charging by the transistors 301 and 302 is stopped, and the precharging is finished. Here, a signal that gradually changes from “L” to “H” is input to the input terminal of the sense signal SEN, and the sense signal SEN gradually changes from “L” to “H”. The sense amplifier is activated.

If the data written in the storage unit 200 at this time is “0” data, the nonvolatile semiconductor memory element 201 is in the off state, 202 is in the on state, and the common source S is the reference potential (0 V). A current flows to the common source S through the semiconductor memory element 202, and a minute voltage difference between the signal lines Bit and BitB cannot be detected, and there is a possibility of causing a malfunction.
In order to avoid malfunction, the rising waveform of the sense signal SEN needs to rise relatively slowly as shown in the figure.
Ideally, it is desirable that the voltage of the input terminal of the sense signal SEN is set near the threshold value of the transistor 305 so that the transistor 305 operates at a low current. However, the operating current of the transistor 305 has a relationship with the sensing speed, and the sensing speed becomes slow when the current is limited by operating the transistor 305 at a low current.

At time t23, “H” is input to the input terminal of the sense signal SEN, and the sense signal SEN becomes “H”. During this time, the potentials of the signal lines Bit and BitB are determined. When “H” is input to the word line WL while the potentials of the signal lines Bit and BitB are fixed at time t24, the word line WL becomes “H”. When the word line WL becomes “H”, the transistors 306 and 307 are activated, and the potentials of the data line DL and the data line inversion signal line DLB are determined according to the state in which the signal lines Bit and BitB are charged. Ends.

[Embodiment 7]
FIG. 13 shows a seventh embodiment which is a modified form from the sixth embodiment.
The parts changed in the seventh embodiment will be described, and the parts that are not changed are denoted by the same reference numerals and the description thereof will be omitted by referring to the sixth embodiment.
A high-sensitivity sense amplifier 400 (signal holding unit) that replaces the high-sensitivity sense amplifier 300 shown in the sixth embodiment, a precharge circuit 600 (precharge unit), and an amplifier unit 700 (amplification detection unit) are provided. The storage unit 200a is the same, and is connected to the high-sensitivity sense amplifier 400 via the signal lines Bit and BitB.

The high-speed sense amplifier 400 transfers (reads) the sense NMOS transistors 401 and 402, the sense amplifier activation NMOS transistors 403 and 404, and the sensed data to the data line DL and the data line inversion signal line DLB. Transfer transistors 405 and 406 are provided.

The transistor 401 has a gate connected to the signal line BitB and the drain of the transistor 402, and a source connected to the drains of the transistors 403 and 404.
The transistor 402 has a gate connected to the signal line Bit and the drain of the transistor 401, and a source connected to the drains of the transistors 403 and 404.
The transistor 403 has a gate connected to the input terminal of the sense signal SEN and a source connected to the reference potential.
The transistor 404 has a gate connected to the input terminal of the sense signal SENd and a source connected to the reference potential.
The transistor 405 has a gate connected to the word line WL, a drain connected to the data line DL, and a source connected to the drain of the transistor 401.
The transistor 406 has a gate connected to the word line WL, a drain connected to the data line inversion signal line DLB, and a source connected to the drain of the transistor 402.

The precharge circuit 600 includes transistors 601, 602, and 603.
The transistor 601 has a gate connected to the input terminal of the precharge control signal PRE, a drain connected to the power supply, and a source connected to the data line DL.
The transistor 602 has a gate connected to the input terminal of the precharge control signal PRE, a drain connected to the power supply, and a source connected to the data line inversion signal line DLB.
The transistor 603 has a gate connected to the input terminal of the precharge control signal PRE, a drain connected to the data line DL, and a source connected to the data line inversion signal line DLB.

In this embodiment, a high-sensitivity sense amplifier 400 is provided instead of the high-sensitivity sense amplifier 300.
The high-sensitivity sense amplifier 400 is different from the sixth embodiment shown in FIG. 11 in that the precharge transistors 301 and 302 provided in the high-speed sense amplifier 300 are deleted and the activation transistors are newly separated into 403 and 404. It is to have done.
Further, the precharge circuit 600 is provided only on the data line DL and the data line inversion signal line DLB side.

In the precharge circuit 600, when “L” is input to the input terminal to which the precharge control signal PRE is input, the precharge control signal PRE becomes “L”. Thus, the data line DL and the data line inversion signal line DLB can be charged through the transistors 601 and 602. The transistor 603 is activated together with the transistors 601 and 602 and functions to balance the potential charged in the data line DL and the data line inversion signal line DLB.

The amplifier unit 700 is an amplifier that reads data transmitted via the data line DL and the data line inversion signal line DLB at a higher speed and a circuit for latching the read data.

The activation transistor in the high-speed sense amplifier 400 includes a transistor 403 that performs an initial sense operation (sense 1) and a transistor 404 that performs this sense operation (sense 2).

Next, the operation will be described with reference to FIG.
This figure is a timing chart showing the operation of the configuration shown in FIG.
First, at the time of precharge starting at time t31, “L” is input to the input terminal of the precharge signal PRE, the input terminals of the sense signals SEN and SENd, and “H” is input to the word line WL, and the precharge signal PRE, The sense signals SEN and SENd are “L” and the word line WL is “H”.
Accordingly, the transistors 405 and 406 are turned on, and the precharge circuit 600 also performs a charge state operation. The precharge circuit 600 precharges the data line DL and the data line inversion signal line DLB, and the signal lines Bit and BitB are also charged through the transistors 405 and 406.

At time t32, “H” is input to the input terminal of the precharge signal PRE and the input terminal of the sense signal SEN, and the precharge signal PRE and the sense signal SEN are set to “H”.
The precharge circuit 600 ends the precharge. Further, a potential slightly lowered from the “H” level is input to the word line WL, and the potential of the word line WL is slightly decreased from the “H” level, so that the transistors 405 and 406 are turned off. Become. Further, an “H” level potential is input to the input terminal of the sense signal SEN, and the sense signal SEN becomes “H”.

At this time, the transistor 403 is operated at a constant current, or the capacity of the transistor is small and the drain current is reduced. Thereby, the sensitivity of the sensing operation is improved, and a minute potential difference between the signal lines Bit and BitB is expanded.

“H” is input to the input terminal of the sense signal SEN, and the sense signal SEN becomes “H”.
After the potential difference between the signal lines Bit and BitB has increased to some extent, when “H” is input to the input terminal of the sense signal SENd at time t33 and the sense signal SENd becomes “H”, the potentials of the signal lines Bit and BitB are Confirm quickly.
Here, when “H” is input to the input terminal of the word line WL and the potential of the word line WL becomes “H”, the transistors 405 and 406 are completely turned on. Thereby, the potentials of the data line DL and the data line inversion signal line DLB are determined. The determined potential is input to the amplifier unit 700. The amplifier unit 700 determines at high speed, latches the data, and finishes reading.

[Embodiment 8]
FIG. 15 shows an eighth embodiment which is a modified form from the seventh embodiment.
The parts changed in the eighth embodiment will be described, and the parts that are not changed are denoted by the same reference numerals and the description thereof will be omitted by referring to the seventh embodiment.
The high-speed sense amplifier 400 and the precharge circuits 600 and 700 shown in the seventh embodiment are the same except that the storage unit 200c is used instead of the storage unit 200a.
In the storage unit 200a, the sources of the nonvolatile semiconductor memory elements 201 and 202 are directly connected to the common control signal terminal S. However, in the storage unit 200c, each source is connected to the common control signal terminal S via a resistor. .

The storage unit 200c further includes resistors 205 (first resistor) and 206 (second resistor), and the sources of the nonvolatile semiconductor memory elements 201 and 202 are connected to the control signal terminal S via the resistors 205 and 206, respectively. Connected.
By providing the resistors 205 and 206, even if the control signal terminal S is shared, a wide operation margin (reading allowable range) can be secured.
As described in the second embodiment, when the control signal terminal S is shared, the write / erase voltage needs to be set to about 6V to 7V. Therefore, depending on the case, the injection amount of electrons or holes may be reduced, and the read margin may be reduced, so care must be taken in voltage optimization.
In the present embodiment, for example, a case where 8 V is applied to the control signal terminal S is considered, in which the nonvolatile semiconductor memory element 201 performs writing (electron injection) and the nonvolatile semiconductor memory element 202 performs erasing (hole injection). . Since the current due to hot electrons flows through the nonvolatile semiconductor memory element 201 to be written about 100 μA, 6 V is applied to the source of the nonvolatile semiconductor memory element 201.

On the other hand, since no current flows through the nonvolatile semiconductor memory element 202 that performs erasing, 8 V is applied to the source of the nonvolatile semiconductor memory element 202.
Therefore, as shown in the case of 6V in FIG. 7C, the voltage at the time of writing is −1.9V at the time of reading “0”, and the voltage at the time of erasing is the case of 8V in FIG. 4B. As shown, at the time of reading “1”, the floating gate FG becomes + 2.7V. A sufficient margin can be secured for both “0” reading and “1” reading.

[Embodiment 9]
FIG. 16 shows a ninth embodiment which is a modified form from the second embodiment.
The parts changed in the ninth embodiment will be described, and parts not changed will be denoted by the same reference numerals and the description thereof will be omitted.
A high-sensitivity sense amplifier 500 (signal holding unit) is provided instead of the SRAM unit 100 (sense unit) shown in the second embodiment. The storage unit 200a is the same, and is connected to the high-sensitivity sense amplifier 500 via the signal lines Bit and BitB.

This is an embodiment in which a high-sensitivity sense amplifier 500 is provided in place of the SRAM unit 100.

The form shown in this figure is a form using a high-sensitivity / high-speed sense amplifier as the high-sensitivity sense amplifier 500, and has a latch function in accordance with the high-sensitivity / high-speed sense amplifier function. The high sensitivity sense amplifier 500 includes PMOS transistors 501, 502, 503, 504, and 505.

The transistor 501 (power supply transistor) has a gate connected to the terminal of the activation signal SET, a drain connected to the power supply, and a source connected to the drains of the transistors 502 and 503.
The gate of the transistor 502 is connected to the signal line Bit and the source of the transistor 503.
The gate of the transistor 503 is connected to the signal line BitB and the source of the transistor 502.
The transistor 504 has a gate connected to the word line WL, a drain connected to the data line DL, and a source connected to the source of the transistor 502.
The transistor 505 has a gate connected to the word line WL, a drain connected to the data line inversion signal line DLB, and a source connected to the drain of the transistor 503.

The PMOS transistor 501 receives an activation signal SET for setting and activating the sense amplifier at the gate. The PMOS transistors 502 and 503 are sense and latch transistors, and the transistors 504 and 505 are transfer transistors for reading data to the data line DL and the data line inversion signal line DLB.

FIG. 17 shows operation waveforms of the form shown in FIG.
Data line DL and data line inversion signal line DLB are precharged in advance. It is assumed that the nonvolatile semiconductor memory element 201 is written and the nonvolatile semiconductor memory element 202 is erased.
At time t41, when “L” is input to the input terminal of the activation signal SET and the activation signal SET becomes “L”, the high sensitivity sense amplifier 500 is activated. Thereby, the potential of the signal line Bit is kept almost “L” and the signal line BitB is charged, so that the potentials of the signal lines Bit and BitB are determined at high speed.
After that, when “H” is input to the word line WL at time t42 and the potential of the word line WL becomes “H”, the potentials of the data line DL and the data line inversion signal line DLB are determined, and reading can be completed.

[Embodiment 10]
FIG. 18 shows a tenth embodiment which is a modified form from the ninth embodiment.
The parts changed in the tenth embodiment will be described, and parts not changed will be given the same reference numerals and the description will be omitted by referring to the ninth embodiment.
The high-speed sense amplifier 500 shown in the ninth embodiment is the same, but includes a storage unit 200d instead of the storage unit 200a. Further, the storage unit 200c shown in the eighth embodiment is similar to the storage unit 200d.
The description of the storage unit 200d will be described in comparison with the storage unit 200c.

The storage unit 200d includes nonvolatile semiconductor memory elements 201 and 202 and transistors 207 and 208.
The nonvolatile semiconductor memory element 201 has a drain connected to the high speed sense amplifier 500 via a signal line BitB, and a source connected to the drain of the transistor 207.
The nonvolatile semiconductor memory element 202 has a drain connected to the high speed sense amplifier 500 via a signal line Bit and a source connected to the drain of the transistor 208.
The transistor 207 has a gate connected to the input terminal of the signal SEL and a source connected to the control signal terminal S.
The transistor 208 has a gate connected to the input terminal of the signal SEL and a source connected to the control signal terminal S.

The memory unit 200d is replaced with transistors 207 and 208 that can pass an appropriate current instead of the resistors 205 and 206 provided in the memory unit 200c. The transistors 207 and 208 are operated at a constant current, or the drain current is reduced by reducing the capacity of the transistor. A signal SEL that also serves as a selection signal is input to the gate terminals of the transistors 207 and 208.
The transistor configuration has an advantage that the layout area can be made smaller than that of the resistor and that the memory cell activated by the signal SEL can be selected. For example, the control signal terminal S of all the memory cells can be made common in the matrix configuration of FIG. 8 or FIG. 10, and selection by the signal SEL is performed.

As described above, according to each embodiment of the present invention, a nonvolatile semiconductor memory (that is, a nonvolatile semiconductor memory element and a semiconductor device using the same) can be realized by a standard logic CMOS process. Therefore, by mounting the nonvolatile semiconductor memory of the present invention on the standard logic, a logic embedded memory can be realized easily and inexpensively.

The present invention is not limited to the above-described embodiments, and can be changed without departing from the spirit of the present invention. The number of active elements in the semiconductor device of the present invention and the connection form are not particularly limited.

According to the present invention, a non-volatile semiconductor memory element having a single-layer polysilicon cell structure and a semiconductor device using the same can be realized by a standard logic CMOS process, and a logic-embedded memory can be easily and inexpensively realized.

Claims (13)

1. A first nonvolatile semiconductor memory element; and a second nonvolatile semiconductor memory element that stores information on a logic state that is opposite to the first nonvolatile semiconductor memory element; and a storage unit that stores one piece of information ,
   A sense unit that reads information stored in the first and second nonvolatile semiconductor memory elements via a pair of first signal line and second signal line;
   A semiconductor device comprising:
   Each of the first and second nonvolatile semiconductor memory elements includes:
   Including at least a floating gate, a drain and a source formed on the semiconductor substrate;
   As a writing state, a voltage is applied between the source and drain to inject charges into the floating gate and accumulate,
   As an erased state, when erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source, and hot carriers between bands are generated in the semiconductor substrate. A semiconductor device configured to erase charges accumulated in the floating gate.
2. The first nonvolatile semiconductor memory element has a drain connected to the second signal line and a source connected to the first control signal terminal,
   The second nonvolatile semiconductor memory element has a drain connected to the first signal line and a source connected to a second control signal terminal,
   The first control signal terminal and the second control signal terminal to which the sources of the first and second nonvolatile semiconductor memory elements are respectively connected are configured independently of each other, and have different potentials at the time of writing and erasing. 2. The semiconductor device according to claim 1, wherein each of the semiconductor devices has a reference potential during reading.
3. The first nonvolatile semiconductor memory element has a drain connected to the second signal line, and a source connected to the first control signal terminal,
   The second nonvolatile semiconductor memory element has a drain connected to the first signal line and a source connected to the first control signal terminal,
   2. The semiconductor device according to claim 1, wherein the first control signal terminals connected in common take a predetermined potential at the time of erasing and writing, and become a reference potential at the time of reading.
4. Further comprising first and second transistors;
   The first nonvolatile semiconductor memory element has a drain connected to a source of the first transistor and a source connected to the first control signal terminal,
   The second nonvolatile semiconductor memory element has a drain connected to a source of a second transistor, a source connected to the first control signal terminal,
   The first transistor has a gate connected to an activation signal input terminal, a drain connected to the second signal line, and a source connected to the drain of the first nonvolatile semiconductor memory element,
   The second transistor has a gate connected to the activation signal input terminal, a drain connected to the first signal line, and a source connected to the drain of the second nonvolatile semiconductor memory element,
   The first control signal terminal connected in common takes a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading,
   In response to an activation signal input to the activation signal input terminal, the first and second transistors are turned on, the first or second nonvolatile semiconductor memory element is erased, and the floating gate is supplied to the floating gate. When erasing the accumulated charge, a voltage is applied between the semiconductor substrate and the drain or source to generate hot carriers between bands between the semiconductor substrate, and the charges accumulated in the floating gate by the hot carriers are generated. The semiconductor device according to claim 1, wherein the semiconductor device is configured to erase the data.
5. A first resistor and a second resistor;
   The first nonvolatile semiconductor memory element has a drain connected to the second signal line and a source connected to the first control signal terminal via a first resistor,
   The second nonvolatile semiconductor memory element has a drain connected to the first signal line and a source connected to the first control signal terminal via a second resistor,
   2. The semiconductor device according to claim 1, wherein the first control signal terminal takes a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading.
6. Further comprising first and second transistors;
   The first nonvolatile semiconductor memory element has a drain connected to the second signal line and a source connected to the drain of the first transistor,
   The second nonvolatile semiconductor memory element has a drain connected to the first signal line and a source connected to the drain of the second transistor,
   The first transistor has a gate connected to an input terminal of an activation signal and a source connected to the first control signal terminal,
   The second transistor has a gate connected to an activation signal input terminal and a source connected to the first control signal terminal.
   The first and second transistors are activated by the input of the activation signal,
   2. The semiconductor device according to claim 1, wherein the first control signal terminal takes a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading.
7. The sense part is
   A power supply line is connected via a power transistor, and includes a flip-flop circuit that holds a signal,
   In the flip-flop circuit, a voltage is applied to the power supply by controlling the on / off state of the power transistor,
   7. The semiconductor device according to claim 1, wherein the semiconductor device is configured to hold output signals from the first and second nonvolatile semiconductor memory elements.
8. The sense part is
   A flip-flop circuit connected to a power source via a power transistor, connected to a reference potential via a ground transistor, and connected to the memory unit via the pair of first and second signal lines;
   A signal amplifier for amplifying an output signal from the flip-flop circuit;
   The semiconductor device according to claim 1, further comprising:
9. A semiconductor device comprising a memory cell in which the storage unit and the sense unit are combined,
   A matrix array in which the memory cells are arranged in the row and column directions, and a sense amplifier;
   Each of the memory cells
   A storage unit including first and second nonvolatile semiconductor memory elements including at least a floating gate, a drain, and a source formed on a semiconductor substrate;
   A sense unit for holding a signal by a flip-flop circuit connected to a power supply via a power transistor;
   Including
   The first and second nonvolatile semiconductor memory elements are:
   When erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source to generate hot carriers between bands between the semiconductor substrate and accumulate in the floating gate by the hot carriers. Configured to erase the generated charge,
   The flip-flop circuit is
   A sense unit configured to apply power to the flip-flop circuit by controlling an on state and an off state of the power transistor by an activation signal;
   Source lines connecting the sources of the first and second nonvolatile semiconductor memory elements for each row;
   A row line for transmitting the selection signal of the sense unit and the activation signal for each row;
   A bit line for transmitting the information of the sense part for each column;
   With
   The sense amplifier connects the signal output from the sense unit to the bit line for each column,
   A semiconductor device, comprising: a reading unit that reads information stored in accordance with a state of electric charge accumulated in a floating gate of a nonvolatile semiconductor memory element designated by the bit line and the row line.
10. A semiconductor device comprising a memory cell in which the storage unit and the sense unit are combined,
    A matrix array in which the memory cells are arranged in the row and column directions, and a sense amplifier;
    Each of the memory cells
    First and second nonvolatile semiconductor memory elements including at least a floating gate, a drain, and a source formed on a semiconductor substrate, and each of the first and second nonvolatile semiconductor memory elements connected in series and turned on Or a first and a second transistor for controlling selection or non-selection of the first and second nonvolatile semiconductor memory elements by turning them off, and a storage unit including:
    A sense unit for holding a signal by a flip-flop circuit connected to a power supply via a power transistor;
    Including
    The first and second transistors are turned on, a voltage is applied between the source and drain of the first and second nonvolatile semiconductor memory elements to inject charges into the floating gate and accumulate,
    A voltage is applied between the semiconductor substrate and the drains or sources of the first and second nonvolatile semiconductor memory elements when erasing charges accumulated in the floating gates of the first and second nonvolatile semiconductor memory elements. A non-volatile semiconductor memory device configured to generate hot carriers between bands in the semiconductor substrate and to erase charges accumulated in the floating gate by the hot carriers;
    The flip-flop circuit is configured to control the on / off state of the power transistor by an activation signal and apply power to the flip-flop circuit;
    Source lines connecting the sources of the first and second nonvolatile semiconductor memory elements for each row;
    A control signal for controlling the gates of the first and second transistors, the activation signal, and a row line for transmitting a selection signal of the sense unit for each row;
    A bit line for transmitting the information of the sense part for each column;
    The nonvolatile semiconductor memory element and the sense unit can be selectively cut off by a signal input to the row line,
    A semiconductor device, comprising: a reading unit that reads information stored in accordance with a state of electric charge accumulated in a floating gate of a nonvolatile semiconductor memory element designated by the bit line and the row line.
11. A storage unit comprising: a first nonvolatile semiconductor memory element; and a second nonvolatile semiconductor memory element having a logic state opposite to the first nonvolatile semiconductor memory element;
    A signal holding unit having an activation signal input terminal and comprising a sense circuit that reads information from the storage unit by an input activation signal, and a flip-flop circuit that holds and outputs information read by the sense circuit When,
    A precharge unit that charges the signal holding unit when reading information from the storage unit;
    An amplification detector that amplifies and outputs the signal output from the signal holding unit;
    With
    The first and second nonvolatile semiconductor memory elements are:
    A transistor structure comprising a floating gate, a drain and a source formed on a semiconductor substrate, each source connected to the first control signal terminal,
    As a writing state, a voltage is applied between the source and drain to inject charges into the floating gate and accumulate,
    As an erased state, when erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source, and hot carriers between bands are generated in the semiconductor substrate. A semiconductor device configured to erase charges accumulated in the floating gate.
12. A storage unit comprising: a first nonvolatile semiconductor memory element; and a second nonvolatile semiconductor memory element having a logic state opposite to the first nonvolatile semiconductor memory element;
    A signal holding unit that is connected to the storage unit via a pair of first and second signal lines and holds and outputs information read from the storage unit by a flip-flop circuit having an activation circuit;
    With
    The first and second nonvolatile semiconductor memory elements are:
    A transistor structure comprising a floating gate, a drain and a source formed on a semiconductor substrate, each source connected to the first control signal terminal,
    As a writing state, a voltage is applied between the source and drain to inject charges into the floating gate and accumulate,
    As an erased state, when erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source, and hot carriers between bands are generated in the semiconductor substrate. Configured to erase charges accumulated in the floating gate;
    The first nonvolatile semiconductor memory element has a drain connected to the first signal line, a source connected to the first control signal terminal, and the second nonvolatile semiconductor memory element has a drain connected to the second signal line. The first control signal terminal is connected to the first control signal terminal, and the first control signal terminal connected in common takes a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading,
    The semiconductor device according to claim 1, wherein the signal holding unit includes an activation circuit including a power transistor connected to a power source side of the flip-flop circuit.
13. A first non-volatile semiconductor memory element; a second non-volatile semiconductor memory element having a logic state opposite to the first non-volatile semiconductor memory element; and the first non-volatile semiconductor memory element connected in series. A storage unit, and a second transistor connected in series with the second nonvolatile semiconductor memory element;
    A signal holding unit configured by a flip-flop circuit including an activation circuit;
    With
    The first and second nonvolatile semiconductor memory elements are:
    A transistor structure comprising a floating gate, a drain and a source formed on a semiconductor substrate, each source connected to the first control signal terminal,
    As a writing state, a voltage is applied between the source and drain to inject charges into the floating gate and accumulate,
    As an erased state, when erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source, and hot carriers between bands are generated in the semiconductor substrate. Configured to erase charges accumulated in the floating gate;
    The storage unit
    The first nonvolatile semiconductor memory element has a drain connected to a high-speed sense amplifier via a second signal line, and a source connected to the drain of the first transistor.
    The second nonvolatile semiconductor memory element has a drain connected to the high-speed sense amplifier via the first signal line, and a source connected to the drain of the second transistor,
    The first transistor has a gate connected to an input terminal of an activation signal and a source connected to the first control signal terminal,
    The second transistor has a gate connected to an activation signal input terminal and a source connected to the first control signal terminal.
    The first control signal terminal takes a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading,
    The signal holding unit includes an activation circuit including a power transistor connected to a power source side of the flip-flop circuit,
    The signal holding unit amplifies and detects information stored in the nonvolatile semiconductor memory element according to a control signal applied to the activation circuit, holds and outputs the read information. .

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