JP2015207326A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of writing SRAM data of SRAM in a nonvolatile memory unit, and capable of realizing a high-speed operation in the SRAM.SOLUTION: In a nonvolatile semiconductor memory device 1, since voltage required for writing SRAM data at a nonvolatile memory unit 16 can be lowered, a film thickness of each gate insulation film of a first access transistor 21a, a second access transistor 21b, a first load transistor 22a, a second load transistor 22b, a first drive transistor 23a, and a second drive transistor 23b, constituting SRAM 15 connected to the nonvolatile memory unit 16 is formed to be 4 nm or less. The SRAM 15 can be operated at a high speed at a lower power source voltage, corresponding to that, thus, SRAM data of the SRAM 15 can be written in the nonvolatile memory unit 16 and a high speed operation of the SRAM 15 is realized.

Description

  The present invention relates to a nonvolatile semiconductor memory device, and is suitable for application to, for example, a nonvolatile semiconductor memory device having an SRAM (Static Random Access Memory).

  In recent years, with the widespread use of electrical devices such as smartphones, the importance of SRAM for processing high-capacity signals such as voice and images at high speed has increased (for example, see Non-Patent Document 1). In general, in SRAMs, it is important to increase speed, reduce area, and reduce power, and in recent years, new circuit configurations have been developed. In addition, since the SRAM is a volatile memory, it is also desired to store the external data written in the storage node even after the power supply is stopped. The nonvolatile memory unit can retain the data even after the power is stopped. It is also desired to write the SRAM data to the memory, and to read the data from the nonvolatile memory unit again to the storage node after the power is turned on again.

"Wikipedia Static Random Access Memory", [online], March 24, 2014 search, Internet (URL: http://en.wikipedia.org/wiki/Static_Random_Access_Memory)

  By the way, in a general non-volatile memory portion, a voltage difference between a voltage value required during a data write operation and a voltage value required during a non-write operation in which no data is written is large. For this reason, the SRAM that exchanges data with the conventional nonvolatile memory unit also has a large voltage applied to the SRAM in accordance with the voltage required for the data write operation or non-write operation to the nonvolatile memory unit. Therefore, the gate insulating film of the transistor constituting the SRAM is also thickened, and there is a problem that it is difficult to realize high-speed operation in the SRAM.

  Therefore, the present invention has been made in consideration of the above points, and an object thereof is to propose a nonvolatile semiconductor memory device capable of writing SRAM data of SRAM into a nonvolatile memory section and realizing high-speed operation in the SRAM. And

  In order to solve such a problem, the nonvolatile semiconductor memory device of the present invention has a first storage node between one first load transistor and one drive transistor connected at one end, and the other one connected at one end. A second storage node between the two load transistors and the second drive transistor; the other ends of the first load transistor and the second load transistor are connected to a power line; the first drive transistor and the second drive transistor One end of the first storage node or the second storage node is connected to one end of an SRAM (Static Random Access Memory) having the other end connected to the reference voltage line and a first switch transistor connected in series with the first memory transistor. A first memory cell to which a voltage can be applied from either one and a second memory transistor A non-volatile memory unit having a second memory cell to which a voltage can be applied from the remaining second storage node or the other of the first storage nodes is provided at one end of a second switch transistor connected in series with a register The SRAM has a nonvolatile SRAM memory cell, and one end of the SRAM is connected to the gates of the other second load transistor and the second drive transistor and one first storage node, and the other A first access transistor having an end connected to a complementary first bit line and a gate connected to a word line; the gate of one of the first load transistor and the first drive transistor; and the other second storage node And one end connected to the complementary second bit line and the gate connected to the word line. Each of the gates of the first access transistor, the second access transistor, the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor. The thickness of the film is 4 [nm] or less.

  In the nonvolatile semiconductor memory device having such a configuration, when writing the SRAM data represented by the voltage difference between the first storage node and the second storage node of the SRAM to the nonvolatile memory unit, Due to the voltage difference between the first storage node and the second storage node, only one of the first switch transistor or the second switch transistor is turned on, and the first switch transistor and the first switch that are turned on The source-side injection in which a charge accelerated by a voltage and a secondarily generated charge are injected between the memory transistors or between the second switch transistor and the second memory transistor that are turned on, First memory transistor or the second memory transistor It is possible to inject charge into the charge storage region of the data.

  According to the present invention, SRAM data can be written by source side injection in the nonvolatile memory portion, and a voltage required for a program operation for writing data to the nonvolatile memory portion or a program blocking operation for not writing data can be reduced. Therefore, the film of each gate insulating film of the first access transistor, the second access transistor, the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor constituting the SRAM connected to the nonvolatile memory unit The thickness can be reduced to 4 [nm] or less, and accordingly, the SRAM can be operated at high speed with a low power supply voltage. Thus, the SRAM data of the SRAM can be written into the nonvolatile memory unit, and high speed operation in the SRAM can be realized.

It is the schematic which shows the circuit structure of the non-volatile semiconductor memory device of this invention. It is the schematic which shows the circuit structure of a non-volatile SRAM memory cell. FIG. 3 is a schematic diagram showing a layout pattern of a circuit configuration of the nonvolatile SRAM memory cell shown in FIG. 2. FIG. 4A is a schematic diagram illustrating a cross-sectional configuration of the second memory cell. FIG. 4B illustrates a SRAM operation from the outside during a program operation for writing SRAM data from the SRAM to the nonvolatile memory portion, a memory data erasing operation in the nonvolatile memory portion. 6 is a table showing voltage values of respective parts during a write operation for writing external data to the memory and a read operation for reading SRAM data from the SRAM to the outside. FIG. 5A is a flowchart showing a program operation procedure for writing SRAM data of the SRAM to the nonvolatile memory unit, and FIG. 5B is a flowchart showing a memory data write operation procedure for writing the memory data of the nonvolatile memory unit to the SRAM. FIG. 6A is a table summarizing data states in the SRAM and the nonvolatile memory unit in the program operation procedure and the memory data writing operation procedure, and FIG. 6B is a nonvolatile memory used for explaining the memory data writing operation procedure in FIG. 5B. 1 is a schematic diagram of a volatile SRAM memory cell. FIG. 7A is a flowchart showing a program operation procedure according to another embodiment, and FIG. 7B is a flowchart showing a memory data write operation procedure according to another embodiment. FIG. 8A is a table summarizing data states in the SRAM and the nonvolatile memory unit in the program operation procedure and the memory data writing operation procedure according to another embodiment, and FIG. 8B is a memory data writing operation in FIG. 7B. It is the schematic of the non-volatile SRAM memory cell with which it uses for description of a procedure. FIG. 9A is a schematic diagram showing the circuit configuration of two types of SRAM power supply control circuits, and FIG. 9B is a schematic diagram when a power supply control transistor is provided for each nonvolatile SRAM memory cell. It is a timing chart which shows the voltage state in each part at the time of memory data writing operation. It is a circuit diagram with which it uses for description of a threshold voltage monitor. It is a timing chart which shows the voltage state in each location at the time of threshold voltage monitoring. It is a graph which shows the relationship between the measurement voltage Vmonitor, the memory current Imem, and the reference current Iref. It is the schematic which shows the circuit structure of the non-volatile SRAM memory cell by other Embodiment by which the some non-volatile memory part is arrange | positioned in parallel. FIG. 15 is a schematic diagram showing a state of a first switch gate line and a second switch gate line when a plurality of nonvolatile SRAM memory cells shown in FIG. 14 are arranged. FIG. 16A is a schematic diagram showing a conventional circuit configuration in which a nonvolatile memory unit, an SRAM, and a CPU are connected via a bus, and FIG. 16B shows a nonvolatile SRAM of the present invention in which the nonvolatile memory units are arranged in parallel. It is the schematic where it uses for description of a memory cell. FIG. 15 is a schematic diagram for explaining a program operation using the nonvolatile SRAM memory cell of FIG. 14 and a memory data erasing operation. It is the schematic which shows the circuit structure of the non-volatile semiconductor memory device by other embodiment. 19A is a schematic diagram showing a cross-sectional configuration (1) of a second memory cell according to another embodiment. FIG. 19B shows a program operation, a memory data erase operation, an external data write operation, and an SRAM. It is a table | surface which shows the voltage value of each site | part at the time of the data read-out operation | movement. FIG. 20A is a schematic diagram showing a cross-sectional configuration (2) of a second memory cell according to another embodiment, and FIG. 20B is a table showing voltage values of respective parts during a program operation and a memory data erase operation. It is. FIG. 21A is a schematic diagram showing a cross-sectional configuration (3) of a second memory cell according to another embodiment, and FIG. 21B is a table showing voltage values of respective parts during a program operation and a memory data erase operation. It is. FIG. 22A is a schematic diagram showing a circuit configuration of a nonvolatile SRAM memory cell in which the connection configuration of the first switch transistor and the second switch transistor is changed with respect to the first storage node and the second storage node, and FIG. It is the schematic which shows the circuit structure of the non-volatile SRAM memory cell which provided the mechanism.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(1) Overall Configuration of Nonvolatile Semiconductor Memory Device In FIG. 1, reference numeral 1 denotes a nonvolatile semiconductor memory device of the present invention, which has a configuration in which a plurality of nonvolatile SRAM memory cells 2 are arranged in a matrix. In the nonvolatile semiconductor memory device 1, an address input and a control signal can be input to the input / output interface circuit 3, and data input / output can be performed between the input / output interface circuit 3 and an external circuit. The input / output interface circuit 3 generates a predetermined operation signal based on the address input, data input, and control signal, the data inversion circuit 4, the bit line control circuit 5, the row decoder 6, the column decoder 7, and the SRAM power source. The operation signal can be appropriately transmitted to the control circuit 8, the input / output control circuit 10, and the nonvolatile memory unit control circuit 11. As a result, the data inversion circuit 4, the bit line control circuit 5, the row decoder 6, the column decoder 7, the SRAM power supply control circuit 8, the input / output control circuit 10, and the nonvolatile memory unit control circuit 11 operate from the input / output interface circuit 3. Controlled by a signal, a predetermined operation can be performed.

  In practice, the row decoder 6 is provided with a plurality of word lines WL0, WL1, WL2, WL3, and a plurality of nonvolatile SRAM memory cells 2 are connected to each word line WL0, WL1, WL2, WL3. Yes. Thereby, the row decoder 6 can apply a predetermined voltage to the nonvolatile SRAM memory cell 2 in units of word lines WL0, WL1, WL2, WL3 based on the row address included in the operation signal. . The column decoder 7 is connected to the input / output control circuit 10 via wirings YG0 and YG1, and can turn on / off the transistor 9a provided in the input / output control circuit 10.

  The input / output control circuit 10 turns on or off a pair of transistors 9a provided for each column of the nonvolatile SRAM memory cells 2 to turn on or off a predetermined nonvolatile memory cell among the nonvolatile SRAM memory cells 2 arranged in a matrix. The read bit voltage from the static SRAM memory cell 2 can be detected by the sense amplifier / data input circuit 9b. For example, when the transistor 9a connected to the pair of complementary first bit line BLT1 and the complementary second bit line BLB1 is turned on, the sense amplifier / data input circuit 9b turns on the complementary first bit line BLT1 and the complementary first bit line BLT1. The voltage difference between the two bit lines BLB1 is detected, one complementary first bit line BLT1 (or complementary second bit line BLB1) having a higher voltage is determined as a high level voltage, and the other complementary first bit line BLT1 having a higher voltage is determined. The 2-bit line BLB1 (or the complementary first bit line BLT1) can be determined as a low level voltage.

  The bit line control circuit 5 is connected to a pair of complementary first bit lines BLT0 (BLT1, BLT2, BLT3) and complementary second bit lines BLB0 (BLB1, BLB2, BLB3). A predetermined voltage can be applied to nonvolatile SRAM memory cell 2 in units of columns by 1 bit line BLT0 (BLT1, BLT2, BLT3) and complementary second bit line BLB0 (BLB1, BLB2, BLB3). Yes.

  In addition to such a configuration, the nonvolatile semiconductor memory device 1 according to the present invention is provided with a data inversion circuit 4, and a complementary first bit line BLT0 (BLT1, BLT2, BLT3) and a complementary second bit are formed in pairs. The line BLB0 (BLB1, BLB2, BLB3) is connected to the data inversion circuit 4. The data inversion circuit 4 reads the high level and low level of the SRAM (described later in FIG. 2) constituting the nonvolatile SRAM memory cell 2, inverts the logic, sets the high level to low level, and sets the low level to high level. This is written in the SRAM as inverted data. Note that the logic inversion processing of the SRAM by the data inversion circuit 4 will be described in detail in “(2-5-2) Memory data write operation according to the second embodiment” described later.

  Incidentally, in the case of this embodiment, the case where the data inverting circuit 4 and the sense amplifier / data input circuit 9b are provided separately has been described, but the present invention is not limited to this, for example, the data inverting circuit 4 is provided. The data is arranged in the sense amplifier / data input circuit 9b, and after reading the high level and low level information of the nonvolatile SRAM memory cell 2 with the sense amplifier, the logic is inverted, and this is inverted into the SRAM as inverted data. A writing method may be used.

  On the other hand, a plurality of power supply lines VSp0, VSp1, VSp2, and VSp3 and a plurality of reference voltage lines VSn0, VSN1, VSn2, and VSn3 are connected to the SRAM power supply control circuit 8, and one power supply line VSp0 (VSp1, VSp2, VSp3) and one reference voltage line VSn0 (VSn1, VSn2, VSn3) as a pair. Memory cell 2 is connected. Thereby, the SRAM power supply control circuit 8 applies the power supply voltage VDD to the power supply lines VSp0, VSp1, VSp2, and VSp3, respectively, so that the non-volatile SRAM memory cell 2 is applied to the power supply lines VSp0, VSp1, VSp2, and VSp3. Thus, the power supply voltage VDD can be applied uniformly. The reference voltage lines VSn0, VSn1, VSn2, and VSn3 can uniformly apply a voltage of 0 [V] to the nonvolatile SRAM memory cell 2 in units of the reference voltage lines VSn0, VSn1, VSn2, and VSn3. ing.

  The nonvolatile memory unit control circuit 11 includes a plurality of memory gate lines MG0, MG1, MG2, MG3, a plurality of memory source lines MS0, MS1, MS2, MS3, and a plurality of first switch gate lines CGT0, CGT1, CGT2, CGT3 and a plurality of second switch gate lines CGB0, CGB1, CGB2, and CGB3 are connected. For example, one memory gate line MG0 (MG1, MG2, MG3) and one memory source line MS0 (MS1, MS1) Non-volatile SRAM memory cell 2 by row by MS2, MS3), one first switch gate line CGT0 (CGT1, CGT2, CGT3) and one second switch gate line CGB0 (CGB1, CGB2, CGB3) A predetermined voltage can be applied to the.

(2) Configuration of Nonvolatile SRAM Memory Cell Next, the nonvolatile SRAM memory cell 2 provided in the nonvolatile semiconductor memory device 1 will be described. Since all the nonvolatile SRAM memory cells 2 arranged in a matrix have the same configuration, only one nonvolatile SRAM memory cell 2 will be described below. As shown in FIG. 2, the nonvolatile SRAM memory cell 2 includes an SRAM 15 and a nonvolatile memory unit 16, and the nonvolatile memory unit 16 is connected to the first storage node SNT and the second storage node SNB of the SRAM 15. Have a configuration.

  The SRAM 15 includes a first access transistor 21a and a second access transistor 21b made of an N-type MOS (Metal-Oxide-Semiconductor) transistor, a first load transistor 22a and a second load transistor 22b made of a P-type MOS transistor, and an N-type transistor. A first drive transistor 23a and a second drive transistor 23b made of MOS transistors are provided, and a total of six MOS transistors are formed.

  In this case, the SRAM 15 has a configuration in which one end of the first load transistor 22a and one end of the first drive transistor 23a are connected, and the first load transistor 22a and the first drive transistor 23a connected in series are connected. Has a first storage node SNT. The SRAM 15 has a configuration in which one end of the other second load transistor 22b and one end of the second drive transistor 23b are connected to each other, and is connected between the second load transistor 22b and the second drive transistor 23b connected in series. It has a second storage node SNB. The other ends of the first load transistor 22a and the second load transistor 22b are connected to the power supply line VSp1, and the other ends of the first drive transistor 23a and the second drive transistor 23b are connected to the reference voltage line VSn1.

  The first access transistor 21a has one end connected to one first storage node SNT and the other second load transistor 22b and the gate of the second drive transistor 23b, and the other end connected to a complementary first bit line. Connected to BLT1. The second access transistor 21b has one end connected to the other second storage node SNB and one gate of the first load transistor 22a and the first drive transistor 23a, and the other end being a complementary second Connected to bit line BLB1. The gates of the first access transistor 21a and the second access transistor 21b are connected to the common word line WL1, and the voltage between the complementary first bit line BLT1 or the complementary second bit line BLB1 and the word line WL1 An ON / OFF operation can be performed depending on the difference.

  In the SRAM 15 having such a configuration, external data is written by applying external data to the first storage node SNT and the second storage node SNB as high level and low level voltages by an external data write operation described later. The external data can be held in the first storage node SNT and the second storage node SNB as SRAM data.

  The non-volatile memory unit 16 connected to the SRAM 15 includes a first memory cell 17a and a second memory cell 17b, and the first memory cell 17a and the second memory cell 17b are used to form a 2-cell / 1-bit complementary cell. Is configured. In practice, in the nonvolatile memory unit 16, one first storage node SNT of the SRAM 15 is connected to one end of the first switch transistor 18a of the first memory cell 17a, and the other second storage node SNB of the SRAM 15 is connected. Is connected to one end of the second switch transistor 18b of the second memory cell 17b.

  In this embodiment, the first memory cell 17a includes a first switch transistor 18a made of an N-type MOS transistor, and a first memory transistor made of an N-type MOS transistor having a floating gate FGa as a first charge storage region. 19a, and the other end of the first switch transistor 18a is connected to one end of the first memory transistor 19a. Similarly to the first memory cell 17a, the second memory cell 17b is also composed of an N-type MOS transistor having a second switch transistor 18b made of an N-type MOS transistor and a floating gate FGb as a second charge storage region. A second memory transistor 19b, and the other end of the second switch transistor 18b is connected to one end of the second memory transistor 19b.

  In the nonvolatile memory unit 16, the first switch gate line CGT1 is connected to the gate of the first switch transistor 18a, and another second switch gate line CGB1 different from the first switch gate line CGT1 is connected to the second switch It is connected to the gate of the transistor 18b. Thereby, the nonvolatile memory unit 16 can apply different switch gate voltages to the first switch transistor 18a and the second switch transistor 18b by the first switch gate line CGT1 and the second switch gate line CGB1, The first switch transistor 18a and the second switch transistor 18b can be independently turned on / off by the voltage difference between the first switch transistor 18a and the second switch transistor 18b.

  In such a nonvolatile SRAM memory cell 2, since the electrical connection state between the SRAM 15 and the nonvolatile memory unit 16 can be cut off by the first switch transistor 18 a and the second switch transistor 18 b, external data to the SRAM 15 can be transferred from the outside. During the write operation or the data read operation, the nonvolatile memory section 16 is electrically disconnected from the SRAM 15 by the first switch transistor 18a and the second switch transistor 18b, and can be used as a general SRAM 15.

  The first memory transistor 19a and the second memory transistor 19b have a gate connected to the memory gate line MG1 and the other end connected to the memory source line MS1, and the memory gate line MG1 and the memory source line MS1 A predetermined voltage can be applied. For example, when a high voltage is applied to the memory gate line MG1 and the memory source line MS1, in the first memory transistor 19a, the high voltage of the memory source line MS1 reaches the end of the channel region on the first switch transistor 18a side. obtain. At this time, also in the second memory transistor 19b, similarly, the high voltage of the memory source line MS1 can reach the channel region end on the second switch transistor 18b side.

  For example, when a low level voltage is applied to the first storage node SNT of the SRAM 15 and a high level voltage is applied to the second storage node SNB, the first switch transistor 18a of the first memory cell 17a has the first switch When a high level voltage is applied to the gate line CGT1, the gate line CGT1 is turned on due to a voltage difference between one end connected to the first storage node SNT and the gate. As a result, in the first memory cell 17a, the channel region of the first switch transistor 18a can be lowered by the low level voltage of the first storage node SNT. Thus, in the first memory cell 17a, a high potential difference is generated at the boundary between the floating gate FGa of the first memory transistor 19a and the first switch transistor 18a, and a current flows, and a strong electric field generated by the voltage drop is generated. By using this, charge can be injected into the floating gate FGa by source side injection (SSI).

  At this time, in the second memory cell 17b, since the second storage node SNB is at a high level voltage, even if a high level voltage is applied to the second switch gate line CGB1, the second switch transistor 18b is turned off. Can do. Thereby, in the second memory cell 17b, the electrical connection between the second memory transistor 19b and the second storage node SNB is cut off by the off operation of the second switch transistor 18b, the floating gate FGb of the second memory transistor 19b, Since no on-current flows at the boundary with the second switch transistor 18b, charge is not accelerated and charge is not injected into the floating gate FGb.

  As described above, the nonvolatile SRAM memory cell 2 stores the SRAM data (high level or low level voltage state) held in the first storage node SNT and the second storage node SNB of the SRAM 15 by writing external data into the nonvolatile memory unit. The 16 first memory cells 17a and the second memory cells 17b can be written, and the SRAM data can be held in the nonvolatile memory unit 16 as memory data.

  In such a nonvolatile SRAM memory cell 2, data write operation (hereinafter referred to as a program operation) in the nonvolatile memory unit 16 or non-write without data writing is performed by source side injection performed in the nonvolatile memory unit 16. Since the voltage required for the operation (hereinafter referred to as the program blocking operation) can be lowered, the program is applied to the nonvolatile memory unit 16 in order to perform the program operation and the program blocking operation in the nonvolatile memory unit 16 accordingly. The voltage at the first storage node SNT and the second storage node SNB can also be lowered.

  Thus, in the nonvolatile SRAM memory cell 2, the program operation and the program block operation in the nonvolatile memory unit 16 can be performed even with the power supply voltage VDD (for example, 1.8 [V] or less) in the SRAM 15. Therefore, the SRAM 15 includes the film thicknesses of the gate insulating films of the first access transistor 21a and the second access transistor 21b, the first load transistor 22a and the second load transistor 22b, and the first drive transistor 23a and the second drive transistor 23b. Can be formed to 4 nm or less that can withstand the power supply voltage VDD.

  Incidentally, in hot carrier injection on the drain side performed in a general memory transistor, it is necessary to further increase the voltage applied to the gate with respect to the voltage applied to the drain. For this reason, conventionally, a potential lower than the power supply voltage VDD of the first storage node SNT and the second storage node SNB as in the present invention is applied to the source side of the memory transistor, and data is written in the memory transistor. It is difficult to execute a program operation or a program block operation without writing data.

  Also, in the case of carrier injection using a band-to-band tunnel current performed in a conventional memory transistor, it is necessary to apply a voltage of about 5 [V] to 10 [V] between the gate and the substrate for carrier injection. Therefore, it is difficult to perform a program operation or a program block operation in the memory transistor at a potential of the power supply voltage VDD.

  On the other hand, in the nonvolatile SRAM memory cell 2 of the present invention, in the nonvolatile memory unit 16, the first switch transistor 18a and the second switch transistor that determine on / off of the current flowing through the first memory transistor 19a and the second memory transistor 19b. The gate electrode of 18b and the memory gate electrodes in the first memory transistor 19a and the second memory transistor 19b that apply a voltage necessary for injecting charges into the floating gates (charge storage regions) FGa and FGb are independent of each other. Therefore, it is possible to reduce the voltage required for the program operation and the program blocking operation performed in the nonvolatile memory unit 16.

  Further, since the potential of the first storage node SNT and the second storage node SNB is 0 [V] or the power supply voltage VDD during the program operation in the nonvolatile memory unit 16, the first switch transistor 18a and the second switch transistor 18b The gate voltage required for the on / off operation may be equal to or lower than the power supply voltage VDD, and a voltage higher than the power supply voltage VDD is not required for the on / off operation of the first switch transistor 18a and the second switch transistor 18b. The gate insulating films of 18a and the second switch transistor 18b can also be formed to 4 [nm] or less.

  Further, in the nonvolatile semiconductor memory device 1, when a program operation for writing SRAM data from the SRAM 15 to the nonvolatile memory unit 16 is performed in the plurality of nonvolatile SRAM memory cells 2, a relatively small on-current is generated in each nonvolatile memory unit 16. Since the source side injection that can inject charges into the floating gates FGa and FGb of either the first memory cell 17a or the second memory cell 17b is used, the power consumption of the program operation can be suppressed, and the write potential control can be performed in mat units. Can be done at once.

  In the case of this embodiment, the film thicknesses of the gate insulating films of the first switch transistor 18a and the second switch transistor 18b in the nonvolatile memory section 16 are the first access transistor 21a and the second access transistor 21b that constitute the SRAM 15. The gate insulating films of the first load transistor 22a, the second load transistor 22b, the first drive transistor 23a, and the second drive transistor 23b can be formed to have the same thickness.

  Here, FIG. 3 is a schematic diagram showing an example of a layout pattern for realizing the circuit configuration of the nonvolatile SRAM memory cell 2 shown in FIG. In this case, the nonvolatile SRAM memory cell 2 includes, for example, the first load transistor 22a and the second load transistor 22b of the SRAM 15 formed in the N-type first semiconductor region ER1 (also expressed as “n-well” in FIG. 3). Has been. Further, the nonvolatile SRAM memory cell 2 has a conductivity type different from that of the first semiconductor region ER1, for example, a P-type second semiconductor region ER2 (also expressed as “p-well” in FIG. 3), and the nonvolatile memory portion 16 (That is, a first switch transistor 18a, a second switch transistor 18b, a first memory transistor 19a, and a second memory transistor 19b (not shown)) are formed.

  In the second semiconductor region ER2, in addition to the nonvolatile memory unit 16, the first drive transistor 23a and the second drive transistor 23b of the SRAM 15, and the first access transistor 21a and the second access transistor 21b are also formed. . As described above, the nonvolatile SRAM memory cell 2 includes the first drive transistor 23a and the second drive transistor 23b, the first access transistor 21a, and the second access transistor 21b having the same conductivity type as the nonvolatile memory unit 16 among the transistors constituting the SRAM 15. The access transistor 21b is formed in the second semiconductor region ER2 in which the nonvolatile memory unit 16 is formed. For this reason, when the SRAM 15 is formed, the nonvolatile SRAM memory cell 2 diverts the second semiconductor region forming the nonvolatile memory unit 16 and does not need to separately form a semiconductor region dedicated to the SRAM 15 as a whole. Miniaturization can be realized.

  Actually, the first load transistor 22a and the second load transistor 22b of the SRAM 15 are formed side by side in one direction in the first semiconductor region ER1, and the second semiconductor region ER2 includes the first load transistor 22a and the first load transistor 22a. The two load transistors 22b are disposed adjacent to each other. In the second semiconductor region ER2, the first drive transistor 23a and the second drive transistor 23b of the SRAM 15 are formed side by side in a region adjacent to the first semiconductor region ER1, and further away from the first semiconductor region ER1. One of the other second access transistor 21b of the SRAM 15, the non-volatile memory unit 16, and the SRAM 15 in the other direction (in this case, the other direction orthogonal to the one direction in which the first drive transistor 23a and the second drive transistor 23b are arranged) The first access transistors 21a are formed in this order.

  In FIG. 3, reference numeral 28 denotes a metal layer, 29 denotes a first layer polysilicon, 30 denotes a second layer polysilicon, 31 denotes an active region in which a MOS transistor and a diffusion layer are formed, 32 Indicates a contact. In this embodiment, the metal layer 28 is connected as the power supply line VSp1 to the first load transistor 22a and the second load transistor 22b in the first semiconductor region ER1. The other metal layer 28 connected to the first load transistor 22a is connected in order of the first drive transistor 23a, the nonvolatile memory unit 16, and the first access transistor 21a formed in the second semiconductor region ER2. Some may function as the first storage node SNT. The other metal layer 28 connected to the second load transistor 22b is connected in the order of the second drive transistor 23b, the second access transistor 21b, and the nonvolatile memory unit 16 formed in the second semiconductor region ER2. Some of them can function as the second storage node SNB.

  In the second semiconductor region ER2, in the direction away from the first semiconductor region ER1, the complementary second bit line BLB1 is matched to the arrangement order of the second access transistor 21b, the nonvolatile memory unit 16, and the first access transistor 21a. The word line WL1, the second switch gate line CGB1, the memory gate line MG1, the first switch gate line CGT1, the word line WL1, and the complementary first bit line BLT1 are sequentially arranged. In addition, in the second semiconductor region ER2, there are two memory gate lines MG1 between the second switch gate line CGB1 and the first switch gate line CGT1, and the memory source line MS1 is between these two memory gate lines MG1. Can be placed. By adopting such an arrangement configuration, the nonvolatile SRAM memory cell 2 can efficiently arrange and form the SRAM 15 and the nonvolatile memory unit 16 with a minimum area.

  Next, a cross-sectional configuration of the nonvolatile memory unit 16 will be described below. Here, since the first memory cell 17a and the second memory cell 17b have the same configuration, the following description will be given focusing on the second memory cell 17b. In the case of this embodiment, as shown in FIG. 4A, the second memory cell 17b has a configuration in which source / drain regions 36 and 37 are formed in the active region on the second semiconductor region ER2 at a predetermined interval. Of these, the second storage node SNB of the SRAM 15 is connected to one source / drain region 37 which is one end of the second switch transistor 18b. The memory source line MS1 is connected to the other source / drain region 36 which is the other end of the second memory transistor 19b.

  A channel region of the second switch transistor 18b and a channel region of the second memory transistor 19b are formed on the upper surface of the second semiconductor region ER2 between the source / drain regions 36 and 37. The second switch transistor 18b and the second memory transistor 19b is arranged in series. In the second switch transistor 18b, a switch gate electrode 40 is formed on the channel region via a gate insulating film, and the second switch gate line CGB1 is connected to the switch gate electrode 40. In the second memory transistor 19b, a floating gate FGb is formed on the channel region via a gate insulating film, and a memory gate electrode 39 to which the memory gate line MG1 is connected is formed on the floating gate FGb via an insulating film. Has been. The second memory transistor 19b having such a configuration is large between the high-voltage memory source line MS1 and the memory gate line MG1 and the low-voltage second storage node SNB during the program operation for writing the SRAM data of the SRAM 15. Due to the voltage difference, the largest potential drop occurs at the boundary with the second switch transistor 18b, and charges can be injected into the floating gate FGb by source side injection.

  4B shows the nonvolatile memory unit 2 in the nonvolatile SRAM memory cell 2 during a program operation (indicated as “Program (sram to flash)” in FIG. 4B) for writing SRAM data from the SRAM 15 to the nonvolatile memory unit 16. 16 data erase operation (indicated as “Erase (reset data in flash)” in FIG. 4B) and external data write operation for writing external data to the SRAM 15 from the outside (in FIG. 4B, “Write (extemal data to sram ) ”And the voltage value at each part during the read operation for reading data from the SRAM 15 (indicated as“ Read (output sram data) ”in FIG. 4B). In FIG. 4B, a portion that can be set to an arbitrary voltage value is indicated as “Don't care”. Hereinafter, the external data write operation, read operation, program operation, and data erase operation will be described, and the memory data write operation for writing the memory data held in the nonvolatile memory unit 16 to the SRAM 15 will be described in order.

(2-1) External Data Write Operation for Writing External Data to SRAM First, the external data write operation in the SRAM 15 will be described below. When external data is written to the SRAM 15 from the outside, a predetermined power supply voltage VDD is applied to the word line WL1, and both the first access transistor 21a and the second access transistor 21b connected to the word line WL1 are turned on. At this time, the power supply voltage VDD is also applied to the power supply line VSp1, and the reference voltage line VSn1 is connected to the ground. In the SRAM 15 shown in FIG. 2, for example, when the power supply voltage VDD is applied to one complementary first bit line BLT1, 0 [V] can be applied to the other complementary second bit line BLB1.

  As a result, in each of the first load transistor 22a and the first drive transistor 23a, the complementary second bit line BLB1 and each gate are electrically connected to each other through the other second access transistor 21b. Is applied with 0 [V] of the complementary second bit line BLB1. As a result, the first load transistor 22a is turned on, and the first drive transistor 23a is turned off. Thus, the first storage node SNT between the first load transistor 22a and the first drive transistor 23a is electrically connected to the power supply line VSp1 through the first load transistor 22a, and is supplied by the power supply voltage VDD flowing through the power supply line VSp1. The voltage becomes High (“1”) level.

  At this time, in the other second load transistor 22b and second drive transistor 23b, the complementary first bit line BLT1 and each gate are electrically connected to each other through the first access transistor 21a. Is supplied with the power supply voltage VDD. As a result, the second load transistor 22b is turned off and the second drive transistor 23b is turned on. Thus, the second storage node SNB between the second load transistor 22b and the second drive transistor 23b is electrically connected to the reference voltage line VSn1 via the second drive transistor 23b, and the voltage is supplied by the reference voltage line VSn1. Low (“0”) level.

  As described above, the SRAM 15 is in a state in which external data is written to the first storage node SNT and the second storage node SNB, and the external data is held in the first storage node SNT and the second storage node SNB as SRAM data. At this time, in the nonvolatile memory unit 16, the first switch transistor 18a and the second switch transistor 18b are turned off, and the electrical connection with the first storage node SNT and the second storage node SNB of the SRAM 15 is cut off. Only the SRAM 15 can be operated.

  Incidentally, when external data is not written to the SRAM 15, 0 [V] is applied to the word line WL1 to turn off the first access transistor 21a and the second access transistor 21b. Thereby, the SRAM 15 is disconnected from the complementary first bit line BLT1 and the complementary second bit line BLB1, and can prevent external data from being written to the SRAM 15.

(2-2) SRAM Data Reading Operation from SRAM Next, a reading operation for reading SRAM data held in the SRAM 15 will be described below. When reading the SRAM data of the SRAM 15, the power supply voltage VDD is applied to the word line WL1, and both the first access transistor 21a and the second access transistor 21b connected to the word line WL1 are turned on. As a result, in the nonvolatile SRAM memory cell 2, the voltage of one first storage node SNT is read via the complementary first bit line BLT1, and the other second storage node SNB via the complementary second bit line BLB1. Is read out to the first storage node SNT and the second storage node SNB by the sense amplifier / data input circuit 9b (FIG. 1) connected to the complementary first bit line BLT1 and the complementary second bit line BLB1. The held SRAM data can be determined as a low (“0”) level and high (“1”) level voltage.

  Incidentally, when the SRAM data held in the SRAM 15 is not read, 0 [V] is applied to the word line WL1 to turn off the first access transistor 21a and the second access transistor 21b. As a result, the SRAM 15 is disconnected from the complementary first bit line BLT1 and the complementary second bit line BLB1, and can prevent reading of SRAM data.

(2-3) Program Operation for Writing SRAM Data from SRAM to Non-Volatile Memory Unit In the present invention, the SRAM data held in the SRAM 15 described above is written to the non-volatile memory unit 16 based on the principle of source side injection. Can do. In the following description, it is assumed that one first storage node SNT in SRAM 15 is in a high level state with a high voltage and the other second storage node SNB is in a low level state with a low voltage.

  In this case, for example, 7 [V] may be applied to the memory gate line MG1 and 6 [V] may be applied to the memory source line MS1 in the nonvolatile memory unit 16. In the nonvolatile memory unit 16, the power supply voltage VDD can be applied to the first switch gate line CGT1 and the second switch gate line CGB2, respectively. Here, since the first switch transistor 18a of one first memory cell 17a is electrically connected to one first storage node SNT in which data is written, the nonvolatile memory unit 16 has a gate and one end. The first switch transistor 18a is turned off by the voltage difference between the first switch transistor 18a and the second switch transistor 18a. As a result, in the first memory transistor 19a, the on-current is negligible and the charge is not accelerated, so that the charge cannot be injected into the floating gate FGa.

  On the other hand, the non-volatile memory unit 16 has the second switch transistor 18b of the other second memory cell 17b electrically connected to the other second storage node SNB to which no data is written. One end of the switch transistor 18b becomes the same low level voltage as the second storage node SNB. As a result, the second switch transistor 18b can be turned on. Thus, the voltage difference between the second memory transistor 19b and the second switch transistor 18b is increased, and as a result, a strong electric field is generated to accelerate the charge that forms an on-current, and the charge generated secondarily. Can be injected into the floating gate FGb. In the nonvolatile SRAM memory cell 2, the SRAM data held in the SRAM 15 can be written in the nonvolatile memory unit 16, and the SRAM data can be held in a nonvolatile manner as memory data.

(2-4) Memory Data Erasing Operation in Nonvolatile Memory Unit Next, a data erasing operation for erasing memory data held in the nonvolatile memory unit 16 will be described. There are various memory data erasing operations in the non-volatile memory section 16, but holes are injected into the floating gates FGa and FGb by using, for example, an erasing method using hole injection caused by a band-to-band tunnel current. Can be done.

  The voltage value of each part shown in “Erase (reset data in flash)” in FIG. 4B shows the case of using hole injection caused by the band-to-band tunnel current. In this case, −7 is applied to the memory gate line MG1. While [V] is applied, 6 [V] is applied to the memory source line MS1. As described above, in the nonvolatile SRAM memory cell 2, for example, the memory source line MS1 side with respect to the floating gate FGb in which charges are accumulated by the voltage difference applied to the nonvolatile memory unit 16 from the memory gate line MG1 and the memory source line MS1. Holes can be injected from the memory to erase the memory data.

(2-5) Memory Data Writing Operation for Writing Memory Data of Nonvolatile Memory Part to SRAM Next, a memory data writing operation for writing the memory data held in the nonvolatile memory part 16 to the SRAM 15 will be described below. Here, the memory data writing operation according to the first embodiment, the memory data writing operation according to the second embodiment, and the memory data writing operation according to the third embodiment will be described in order. The memory data writing operation according to the first embodiment, the memory data writing operation according to the second embodiment, and the memory data writing operation according to the third embodiment are performed by transferring SRAM data to the nonvolatile memory unit 16. Since the operation differs depending on the writing method, the program operation for writing the SRAM data to the nonvolatile memory unit 16 will be described.

(2-5-1) Memory Data Write Operation According to First Embodiment Here, FIG. 5A is a flowchart showing a program operation procedure for writing the SRAM data held in the SRAM 15 into the nonvolatile memory unit 16. FIG. 5B is a flowchart showing a memory data writing operation procedure for writing the memory data held in the nonvolatile memory unit 16 to the SRAM 15 in accordance with the flowchart of FIG. 5A. This will be described in order below.

  In this case, as shown in FIG. 5A, when an instruction to write SRAM data to the nonvolatile memory unit 16 is given to the nonvolatile SRAM memory cell 2 in step SP1, the process proceeds to step SP2, and the memory data in the nonvolatile memory unit 16 is transferred. Erase. As a result, the nonvolatile memory unit 16 draws out the charge injected into the floating gate FGa of the first memory transistor 19a or the floating gate FGb of the second memory transistor 19b, and enters an initial state in which no memory data is written.

  Next, the process proceeds to step SP3, and the SRAM data held in the SRAM 15 is written into the nonvolatile memory unit 16. Here, as shown in FIG. 6A, as an example, the first storage node SNT of the SRAM 15 is at a low level voltage (0 [V]), and the second storage node SNB is at a high level voltage (power supply voltage VDD). A program operation for writing SRAM data to the nonvolatile memory unit 16 and a memory data writing operation for writing memory data of the nonvolatile memory unit 16 to the SRAM 15 will be described. In this case, as described above, first, the nonvolatile memory unit 16 extracts the charge accumulated in the floating gates FGa and FGb of either the first memory transistor 19a or the second memory transistor 19b, and sets the threshold voltage Vth. The memory data is erased as less than 0 [V] (threshold voltage Vth <0 [V]).

  Next, in the first memory cell 17a connected to the low-level first storage node SNT in the nonvolatile memory unit 16, the first switch transistor 18a is turned on due to the voltage difference between the gate and one end, and the floating gate is caused by source-side injection. A state in which data is written in the first memory transistor 19a by charging electric charge into FGa (threshold voltage Vth> 0 [V]) can be obtained.

  On the other hand, in the second memory cell 17b connected to the high-level second storage node SNB in the nonvolatile memory unit 16, the second switch transistor is turned off due to the voltage difference between the gate and one end, and data is transferred to the second memory transistor 19b. May not be written (threshold voltage Vth <0 [V]). In this way, the SRAM data is written into the nonvolatile memory unit 16 and the SRAM data is held as memory data.

  Next, the memory data held in the nonvolatile memory unit 16 can be written into the SRAM 15 in accordance with an instruction to write the memory data into the SRAM. When the memory data held in the nonvolatile memory unit 16 is written in the SRAM 15, the procedure shown in FIG. 5B can be performed. As shown in FIG. 5B, when there is an instruction to write memory data to the SRAM 15 in step SP4, the nonvolatile SRAM memory cell 2 moves to step SP5 and resets the SRAM data held in the SRAM 15. For example, as shown in FIGS. 5B and 6B, the SRAM 15 is reset by (i) setting the power supply line VSp1 to 0 [V] to cut off the power supply to the SRAM 15, and (i) setting the word line WL1 to the power supply voltage VDD. (I) The complementary first bit line BLT1 and the complementary second bit line BLB1 are set to 0 [V], and (i) the first access transistor 21a and the second access transistor 21b are turned on to turn on the first storage node SNT The second storage node SNB is set to 0 [V]. In this way, the SRAM 15 is reset.

  Next, (ii) the first access transistor 21a and the second access transistor 21b are turned off by setting the word line WL1 to 0 [V], and the complementary first bit line BLT1 and the complementary second bit line BLB1 are connected to the SRAM 15. Break electrical connection. Next, the process proceeds to step SP6 as shown in FIG. 5B, and the memory data held in the nonvolatile memory unit 16 is sent to the SRAM 15. In this case, as shown in FIGS. 5B and 6B, (iii) the memory source line MS1 is set to the power supply voltage VDD, and (iii) the first switch gate line CGT1 and the second switch gate line CGB1 are set to the power supply voltage VDD.

  As a result, (iV) the second memory cell 17b on the non-write side (threshold voltage Vth <0 [V] side) is electrically connected to the second storage node SNB of the SRAM 15 by the power supply voltage VDD applied to the memory source line MS1. Connect. Thereby, in the SRAM 15, the second storage node SNB becomes a high level voltage (power supply voltage VDD−threshold voltage Vth of the second switch transistor 18b) by the power supply voltage VDD applied to the memory source line MS1. Thereafter, (V) the power supply line VSp1 is set to the power supply voltage VDD, and the SRAM 15 is latched. In this way, the nonvolatile SRAM memory cell 2 can write the memory data held in the nonvolatile memory unit 16 to the SRAM 15.

(2-5-2) Memory Data Write Operation According to Second Embodiment Next, the memory data write operation according to the second embodiment will be described below. In the memory data write operation according to the first embodiment described above, since the method of sending the power supply voltage VDD of the memory source line MS1 to the second storage node SNB of the SRAM 15 is used, it is necessary to reset the SRAM 15 or the like. Therefore, the operation becomes complicated, and there is a limit to the high-speed operation. In the memory data write operation according to the first embodiment, the first switch transistor 18a or the second switch transistor 18b is used by using the power supply voltage VDD of the core MOS for the first switch gate line CGT1 and the second switch gate line CGB1. Therefore, the high level voltage of the first storage node SNT or the second storage node SNB becomes the power supply voltage VDD−the threshold voltage Vth, and there is a limit to the low voltage operation. Here, the threshold voltage Vth indicates the threshold voltage of the first switch transistor 18a or the second switch transistor 18b.

  In contrast, in the memory data write operation according to the second embodiment, a low voltage operation can be realized at a higher speed than the memory data write operation according to the first embodiment. FIG. 7A is a flowchart showing a program operation procedure for writing SRAM data from the SRAM 15 to the nonvolatile memory unit 16 in advance to perform the memory data writing operation according to the second embodiment. FIG. 7B is a flowchart showing a memory data write operation procedure according to the second embodiment in which the memory data held in the nonvolatile memory unit 16 is written in the SRAM 15 in accordance with the flowchart in FIG. 7A. In this case, as shown in FIG. 7A, when an instruction to write SRAM data to the nonvolatile memory unit 16 is given to the nonvolatile SRAM memory cell 2 in step SP11, the process proceeds to step SP12 and step SP13.

  In step SP12, the memory data in the nonvolatile memory unit 16 is erased. As a result, the nonvolatile memory unit 16 draws out the charge injected into the floating gate FGa of the first memory transistor 19a or the floating gate FGb of the second memory transistor 19b, and enters an initial state in which no data is written. In step SP13 performed together with step SP12, the SRAM data of the SRAM 15 is read, and inverted data obtained by logically inverting the SRAM data is written in the SRAM 15.

  In practice, the processing of step SP13 is performed by the data inverting circuit 4 shown in FIG. 1, and the high level or low level voltage at the first storage node SNT and the second storage node SNB of the SRAM 15 is changed to the complementary first bit. Data is read by the data inverting circuit 4 via the line BLT1 and the complementary second bit line BLB1. Next, the data inversion circuit 4 detects the high level and the low level voltage, and in accordance with the “(2-1) External data write operation for writing external data to the SRAM” described above, the complementary first bit line BLT1 and the complementary first bit line BLT1. The voltage applied to the type second bit line BLB1 may be adjusted, and a voltage obtained by inverting the logic of the high level and the low level may be applied to the first storage node SNT and the second storage node SNB of the SRAM 15. As a result, as shown in FIG. 8A, the SRAM 15 converts the first storage node SNT whose initial state before inversion was a low level voltage (0 [V]: data = 0) to a high level voltage (power supply voltage, for example). Inverted to VDD: data = 1), the second storage node SNB whose initial state before the inversion was a high level voltage (power supply voltage VDD: data = 1) is set to a low level voltage (0 [V]: data = 0) can be reversed.

  Here, the inversion processing of the SRAM data of the SRAM 15 by the data inversion circuit 4 is performed in a state in which the first switch transistor 18a and the second switch transistor 18b of the nonvolatile memory unit 16 are turned off, so that the memory of the nonvolatile memory unit 16 It can be performed simultaneously with the data erasing operation. Note that the step SP13 of the SRAM data inversion process and the step SP12 of the memory data erasing operation are not necessarily performed at the same time, and one of them may be performed first.

  Next, as shown in FIG. 7A, in step SP14, the inverted data held in the SRAM 15 is written in the nonvolatile memory unit 16. In the nonvolatile memory unit 16, the inverted data held in the SRAM 15 is written into the first memory transistor 19a and the second memory transistor 19b (step SP12) from which the memory data has been erased (threshold voltage Vth <0 [V]). Can be. In practice, in the first memory cell 17a connected to the first storage node SNT that is at a high level, for example, in the nonvolatile memory unit 16, the first switch transistor 18a is turned off due to the voltage difference between the gate and one end, 1 The memory transistor 19a can be in a state where data is not written (non-write state: threshold voltage Vth <0 [V]).

  On the other hand, in the second memory cell 17b connected to the second storage node SNB that has become the low level in the nonvolatile memory unit 16, the second switch transistor 18b is turned on by the voltage difference between the gate and one end, and the source side injection As a result, electric charge is injected into the floating gate FGb, and data can be written in the second memory transistor 19b (write state: threshold voltage Vth> 0 [V]). In this way, the inverted data of the SRAM 15 can be held in the nonvolatile memory unit 16 as memory data.

  When the memory data held in the nonvolatile memory unit 16 is written into the SRAM 15, it can be performed by a procedure as shown in FIG. 7B. As shown in FIG. 7B, when there is an instruction to write memory data from the nonvolatile memory unit 16 to the SRAM 15 in step SP15, the nonvolatile SRAM memory cell 2 moves to step SP16 and (i) connects the power supply line VSp1 to Hi-Z. Or the power supply to the SRAM 15 is cut off. Next, the process proceeds to step SP17, and the memory data of the nonvolatile memory unit 16 is written into the SRAM 15. At this time, as shown in FIGS. 7B and 8B, (i) the first switch gate line CGT1 and the second switch gate line CGB1 are set to the power supply voltage VDD, and the memory source line MS1 is set to 0 [V]. Thus, (ii) the first storage node SNT of the SRAM 15 is connected to the memory source line MS1 via the first memory cell 17a on the non-write side (threshold voltage Vth <0 [V] side), and the first storage The node SNT goes low (0 [V]: data = 0). Thereafter, (iii) the power supply line VSp1 is set to the power supply voltage VDD and latched in the SRAM 15, the first storage node SNT is set to the low level voltage, and the second storage node SNB is set to the high level voltage.

  Thus, although the low level voltage (0 [V]: data = 0) was applied to the first storage node SNT of the SRAM 15 before the inversion, the memory data held in the nonvolatile memory unit 16 is stored in the SRAM 15. By writing to, the same low level voltage (0 [V]: data = 0) as before the inversion can be applied. On the other hand, a high level voltage (power supply voltage VDD: data = 1) was applied to the second storage node SNB of the SRAM 15 before inversion, but the memory data held in the nonvolatile memory unit 16 is written into the SRAM 15. Thus, the same high level voltage (power supply voltage VDD: data = 1) as that before the inversion can be applied.

  In this manner, the nonvolatile SRAM memory cell 2 writes the memory data held in the nonvolatile memory unit 16 to the SRAM 15, so that the same high level and low level as the SRAM data held in the SRAM 15 before inversion is obtained. A voltage can be applied to the first storage node SNT and the second storage node SNB, respectively.

  That is, in the memory data write operation according to the second embodiment, before the SRAM data is written in the nonvolatile memory unit 16, the inverted data obtained by logically inverting the high level and the low level as the SRAM data is held in the SRAM 15 in advance. The inverted data is written into the nonvolatile memory unit 16. Thus, in the memory data write operation according to the second embodiment, when the memory data of the nonvolatile memory unit 16 is written to the SRAM 15, the write operation can be performed with the memory source line MS1 set to 0 [V]. It is not necessary to reset the SRAM 15 as in the memory data write operation according to the embodiment, and the operation can be simplified correspondingly, and high-speed operation is possible. Further, in the memory data write operation according to the second embodiment, the low level voltage of the nonvolatile memory unit 16 is sent to the SRAM 15, and the operation is the same as the write operation to the SRAM 15 from the outside. The operation is stable, and high-speed and low-voltage operation is possible.

  In the case of this embodiment, when the memory data of the nonvolatile memory unit 16 is written to the SRAM 15, the power supply line VSp1 is set to the Hi-Z voltage or 0 [V] to cut off the power supply to the SRAM 15. Yes. Thereby, even when the memory current flowing through the nonvolatile memory unit 16 is relatively smaller than the current (load pmos current) from the power supply line VSp1 of the SRAM 15, the power supply of the SRAM 15 is cut off by the power supply line VSp1. Therefore, the first storage node SNT or the second storage node SNB that becomes the low level in the SRAM 15 can be easily guided to the low level voltage by the memory current.

  Here, the power shutdown of the SRAM 15 by the power supply line VSp1 can be performed by the SRAM power control circuit 8 as shown in FIG. 9A. FIG. 9A shows two types of SRAM power control circuits 8 (power control transistor 43a and power control inverter 43b) having different circuit configurations as an example. One SRAM power supply control circuit 8 includes a power supply control transistor 43a made of a P-type MOS transistor, one end of the power supply control transistor 43a is connected to the power supply line VSp1, and the gate is connected to the power supply control gate line VSR. It has a configuration. In this case, the power supply control transistor 43a is applied with the power supply voltage VDD at the other end, and in this state, as shown in FIG. 10, the period shifts to the memory data write period to the SRAM 15, and the power supply control gate line VSR. When a predetermined voltage is applied from the gate to the gate, the power supply line VSp1 is turned off to set the voltage to the SRAM 15 by Hi-Z or 0 [V], and the power supply voltage of the SRAM 15 is cut off.

  In addition, in the memory data writing period to the SRAM 15, a voltage is applied to the first switch gate line CGT1 and the second switch gate line CGB1, and for example, a non-write side (threshold voltage Vth < 0 [V]), the first switch transistor 18a and the first memory transistor 19a are turned on, and the first storage node SNT of the SRAM 15 is electrically connected to the memory source line MS1. The first storage node SNT becomes the low level (0 [V]). Next, the power supply control transistor 43a is turned on by stopping the supply of voltage to the power supply control gate line VSR, and can apply the power supply voltage VDD to the power supply line VSp1 again. Thereby, in the SRAM 15, the second storage node SNB can be in a high level voltage state by the power supply voltage VDD of the power supply line VSp1.

  Incidentally, as another SRAM power control circuit 8, as shown in FIG. 9A, a power control inverter 43b may be provided on the power supply line VSp1. In this case, the power supply control inverter 43b can apply the power supply voltage VDD to the power supply line VSp1 and shut off the power supply by controlling the voltage application to the power supply control gate line VSR, and is similar to the power supply control transistor 43a described above. In addition, the memory data of the nonvolatile memory unit 16 can be written into the SRAM 15.

  Incidentally, the power supply control transistor 43a and the power supply control inverter 43b shown in FIG. 9A are provided for each power supply line VSp0, VSp1, VSp2, and VSp3, and the power supply voltage in units of the power supply lines VSp0, VSp1, VSp2, and VSp3. VDD can be applied and power can be shut off. The present invention is not limited to this, and as shown in FIG. 9B, a power supply control transistor 44 is provided for each nonvolatile SRAM memory cell 2, and the power supply control transistor 44 provides power supply lines in units of the nonvolatile SRAM memory cell 2. The power supply voltage VDD from VSp1 may be applied or the power supply may be shut off.

  In this case, the power supply control gate line VSR is provided for each of the power supply lines VSp0, VSp1, VSp2, and VSp3. For example, the nonvolatile SRAM memory cell 2 is connected to the power control gate line VSR provided on the power line VSp1 via the power control transistor 44. In practice, the power supply control transistor 44 has a gate connected to the power supply control gate line VSR, one end connected to the power supply line VSp1, and the other end in addition to the first load transistor 22a and the second load transistor 22b. Connected to the end. Thereby, the power supply control transistor 44 changes the voltage applied to the power supply control gate line VSR to apply the power supply voltage VDD of the power supply line VSp1 to the first load transistor 22a and the second load transistor 22b, or The memory data of the non-volatile memory section 16 can be written into the SRAM 15 in the same manner as the power control transistor 43a and the power control inverter 43b shown in FIG.

(2-5-3) Memory Data Write Operation According to Third Embodiment Next, a memory data write operation according to the third embodiment will be described below. In this case, as shown in FIG. 5A, in accordance with an instruction to write SRAM data to the nonvolatile memory unit 16 (step SP1), the memory data erasing operation of the nonvolatile memory unit 16 is performed (step SP2), and then the SRAM data is stored in a nonvolatile manner. Write to the memory unit 16. Thereafter, the memory data held in the nonvolatile memory unit 16 is written into the SRAM 15 according to the flowchart of FIG. 7B.

  In this state, for example, when a low level voltage is applied to the first storage node SNT of the SRAM 15 and a high level voltage is applied to the second storage node SNB in the initial state, the SRAM data is stored according to the flowchart of FIG. 5A. After writing to the nonvolatile memory unit 16, when memory data is written from the nonvolatile memory unit 16 to the SRAM 15 according to the flowchart of FIG. 7B, different high level voltages are applied to the first storage node SNT of the SRAM 15 in the initial state. Therefore, a different low level voltage is applied to the second storage node SNB in the initial state. Therefore, in this state, the SRAM 15 holds data having high and low level voltages opposite to the SRAM data in the initial state.

  Therefore, in the memory data write operation according to the third embodiment, after the SRAM 15 is latched in step SP17 shown in FIG. 7B, the SRAM data held in the SRAM 15 by writing the memory data is transferred to the data inversion circuit 4. And the inverted data obtained by logically inverting the SRAM data is written into the SRAM 15. As a result, a low level voltage can be applied to the first storage node SNT and a high level voltage can be applied to the second storage node SNB in the SRAM 15 as in the initial state.

(2-6) Threshold Voltage Monitor in Nonvolatile Memory Unit Here, the nonvolatile semiconductor memory device 1 of the present invention can monitor the threshold voltage Vth of the nonvolatile memory unit 16 in each nonvolatile SRAM memory cell 2. . In this case, as shown in FIG. 11, the bit line control circuit 5 connected to the complementary first bit line BLT1 and the complementary second bit line BLB1 includes a first transistor 45 made of a P-type MOS transistor, N A first transistor 45 and one end of the second transistor 46 are connected, and the first transistor 45 and the second transistor 46 are connected in series. have.

  A gate line Vref is connected to the gate of the first transistor 45, and the power supply voltage VDD can be applied to the other end. Further, the gate of the second transistor 46 is connected to the gate line Vreset, and the reset voltage Vss can be applied to the other end. A complementary first bit line BLT1 is connected between the first transistor 45 and the second transistor 46 via a first switching transistor 48a, and a complementary second bit line is connected via a second switching transistor 48b. BLB1 is connected. The first switching gate line VGT is connected to the gate of the first switching transistor 48a, and the second switching gate line VGB is connected to the gate of the second switching transistor 48b. The switching transistors 48b can be individually turned on / off.

  Here, for example, assuming that the first storage node SNT of the SRAM 15 is at a high level voltage and the other second storage node SNB is at a low level voltage, the second memory cell 17b on the complementary second bit line BLB1 side is assumed. The case where the threshold voltage Vth is monitored will be described below. FIG. 12 shows voltage transition of each part when the threshold voltage Vth of the second memory cell 17b in the nonvolatile memory unit 16 is monitored. In FIG. 12, the time is divided into t1 to t12 along the time axis.

  First, from t1 to t2, the application of the power supply voltage VDD by the power supply line VSp1 is cut off, and the latch function of the SRAM 15 is stopped. In practice, from t1 to t2, the voltage of the power supply control gate line VSR of the SRAM power supply control circuit 8 is raised to turn off the power supply control transistor 43a made of a P-type MOS transistor, and the power supply voltage VDD is applied by the power supply line VSp1. Shut off and stop the latch function of the SRAM 15. Next, at t2 to t4, a predetermined voltage is applied to the word line WL1, the first switching gate line VGT, the second switching gate line VGB, and the gate line Vreset, and the first access transistor 21a and the second access transistor 21b of the SRAM 15 Then, the second transistor 46, the first switching transistor 48a, and the second switching transistor 48b of the bit line control circuit 5 are turned on.

  As a result, the reset voltage Vss can be applied to the SRAM 15 to the first storage node SNT and the second storage node SNB. Next, at t4 to t5, voltage application to the first switching gate line VGT, the second switching gate line VGB, and the gate line Vreset is stopped, and the first switching transistor 48a, the second switching transistor 48b, and the second transistor 46 are stopped. Is turned off to complete the resetting operation.

  Next, from t6 to t7, the first transistor 45 is turned on by lowering the voltage of the gate line Vref, and the second switching transistor 48b is turned on by raising the voltage of the second switching gate line VGB. Prepare to supply reference current Iref to SNB. Further, from t6 to t7, the voltage of the second switch gate line CGB1 is raised to turn on the second switch transistor 18b. Further, in order to examine the threshold voltage Vth, the nonvolatile memory unit 16 applies a measurement voltage Vmonitor having a predetermined voltage value to the memory gate line MG1, and supplies the memory current Imem flowing in the second memory cell 17b and the second storage node SNB. Prepare for comparison with the reference current Iref.

  Next, from t8 to t10, the voltage of the power supply control gate line VSR of the SRAM power supply control circuit 8 is lowered, and the power supply control transistor 43a is turned on to bring the power supply line VSp1 closer to the power supply voltage VDD. As a result, the first storage node SNT and the second storage node SNB rise slightly from GND. At this time, when the voltage that allows the reference current Iref to flow through the second memory cell 17b is the threshold voltage Vth and the measurement voltage Vmonitor> threshold voltage Vth, the memory current Imem is greater than the reference current Iref in the second storage node SNB. It will be big. Therefore, when the power supply voltage VDD is applied to the power supply line VSp1 (t9 to t10), the second storage node SNB becomes a low level voltage due to the memory current Imem, and the first storage node SNT becomes a high level voltage.

  On the other hand, when the threshold voltage Vth is high and the threshold voltage Vth is larger than the current measurement voltage Vmonitor, when the power supply voltage VDD is applied to the power supply line VSp1 (t9 to t10), the second storage node SNB generates the reference current Iref As a result, the first storage node SNT is latched at a low level voltage (not shown).

  Next, from t11 to t12, the voltage of the gate line Vref is raised to turn off the first transistor 45, and the voltage of the second switching gate line VGB is lowered to turn off the second switching transistor 48b. Also, from t11 to t12, the voltage of the word line WL1 is lowered to turn off the first access transistor 21a and the second access transistor 21b, and the voltage of the second switch gate line CGB1 is lowered to turn off the second switch transistor 18b. The latch operation of the SRAM 15 is completed by operating and stopping the voltage supply to the memory gate line MG1.

  Thereafter, the voltages latched by the first storage node SNT and the second storage node SNB in the SRAM 15 are read in accordance with the “(2-2) Read operation of SRAM data from the SRAM” described above. At this time, for example, when the second storage node SNB is at a high level voltage, the reference current Iref is larger than the memory current Imem at the current voltage value of the measured voltage Vmonitor, and the second storage node SNB It indicates that the reference current Iref is at a high level. Thereby, it can be seen that the voltage value of the current measurement voltage Vmonitor used for monitoring the threshold voltage Vth is smaller than the threshold voltage Vth of the second memory cell 17b.

  On the other hand, for example, when the second storage node SNB is at a low level voltage, the memory current Imem is larger than the reference current Iref at the current measured voltage Vmonitor voltage value, and the second storage node SNB Indicates that the voltage is at the low level due to the current Imem. Thereby, it can be seen that the voltage value of the current measurement voltage Vmonitor used for monitoring the threshold voltage Vth is larger than the threshold voltage Vth of the second memory cell 17b.

  Thus, as shown in FIG. 13, when the threshold voltage Vth of the non-volatile memory section 16 is monitored, the voltage value of the measurement voltage Vmonitor applied to the memory gate line MG1 is changed. 2 By repeatedly detecting whether the storage node SNB is at the high level by the reference current Iref or the second storage node SNB is at the low level voltage by the memory current Imem, the second memory cell 17b The threshold voltage Vth can be specified.

  In the above configuration, in the non-volatile SRAM memory cell 2, when the threshold voltage Vth of the non-volatile memory unit 16 is monitored, the voltage supply of the power supply line VSp1 is cut off to stop the latch function of the SRAM 15. Regardless of the state of data held in advance, the threshold voltage Vth of the nonvolatile memory unit 16 can be monitored by taking advantage of the high-speed operability of the SRAM 15. Further, in the nonvolatile SRAM memory cell 2, the first switch transistor 18a and the second switch transistor 18b can be independently turned on / off, so that the threshold voltages Vth of the first memory cell 17a and the second memory cell 17b are independent. Can be monitored individually.

  Further, in the nonvolatile SRAM memory cell 2, since the threshold voltage Vth is monitored after the first storage node SNT and the second storage node SNB are aligned with the reset voltage Vss, the threshold voltage is utilized using the reference current Iref. When monitoring Vth, accurate monitoring can be performed without being affected by variations in the voltages of the first storage node SNT and the second storage node SNB. In the nonvolatile SRAM memory cell 2, the operation of the nonvolatile memory unit 16 and the reliability can be reliably ensured by appropriately setting the reference current Iref and the voltage of the memory gate line MG1.

  Incidentally, when the threshold voltage Vth is monitored by determining whether or not the reference current Iref flows according to the measurement voltage Vmonitor, the latch operation of the SRAM 15, the first storage node SNT and the second storage node The read operation of the storage node SNB can be performed at once for the power supply lines VSp0, VSp1, VSp2, and VSp3. In the above-described embodiment, the case where the threshold voltage Vth of the other second memory cell 17b is monitored has been described. However, the present invention is not limited to this, and the first switching transistor 48a and the first switch transistor 18a And the like, the threshold voltage Vth can be monitored in the same manner in the first memory cell 17a.

  Incidentally, in the above-described embodiment, the case where the latch function of the SRAM 15 is stopped by lowering the voltage of the power supply line VSp1 of the SRAM 15 is described. However, the present invention is not limited to this, and the reference voltage line VSn1 The latch function of the SRAM 15 may be stopped by increasing the voltage. In the above-described embodiment, the method of setting each voltage of the complementary first bit line BLT1 and the complementary second bit line BLB1 to 0 [V] when the latch function of the SRAM 15 is stopped has been described. However, the present invention is not limited to this, and the voltages of the complementary first bit line BLT1 and the complementary second bit line BLB1 may be set to the power supply voltage VDD.

  In the embodiment described above, for example, when comparing the memory current Imem in the second memory cell 17b with the reference current Iref supplied to the second storage node SNB connected to the second memory cell 17b. Although the present invention is not limited to this, for example, one storage node (one of the first storage node SNT or the second storage node SNB) and one nonvolatile memory unit 16 are electrically connected, The other storage node (the other of the remaining first storage node SNT or second storage node SNB) and the bit line control circuit 5 are electrically connected, and the memory current Imem flowing in one storage node and the other storage node A method of comparing the flowing reference current Iref may be used. The difference between the memory current Imem and the reference current Iref is compared, and the data when the SRAM 15 is latched by the magnitude thereof is used. It may be a method to confirm.

(3) Operation and Effect In the above configuration, the nonvolatile semiconductor memory device 1 of the present invention is provided with the nonvolatile SRAM memory cell 2 to which the SRAM 15 and the nonvolatile memory unit 16 are connected. The SRAM 15 has a first storage node SNT between one first load transistor 22a and the first drive transistor 23a connected at one end, and the other second load transistor 22b and second drive transistor 23b connected at the other end. The other end of the first load transistor 22a and the second load transistor 22b is connected to the power supply line VSp1, and the other end of the first drive transistor 23a and the second drive transistor 23b is a reference voltage. Connected to line VSn1.

  The SRAM 15 has one end connected to the gates of the other second load transistor 22b and the second drive transistor 23b and one first storage node SNT, and the other end to the complementary first bit line BLT1. And a first access transistor 21a having a gate connected to the word line WL1. Furthermore, one end of the SRAM 15 is connected to the gates of the first load transistor 22a and the first drive transistor 23a and the other second storage node SNB, and the other end is connected to the complementary second bit line BLB1. And a second access transistor 21b whose gate is connected to the word line WL1.

  On the other hand, in the nonvolatile memory unit 16, a first memory cell 17a in which the first storage node SNT is connected to one end of the first switch transistor 18a connected in series with the first memory transistor 19a, and a second memory transistor 19b in series. The second memory cell 17b to which the second storage node SNB is connected is provided at one end of the connected second switch transistor 18b.

  In the nonvolatile semiconductor memory device 1, the first storage node SNT and the first storage node SNT in the program operation of writing the SRAM data represented by the voltage difference between the first storage node SNT and the second storage node SNB of the SRAM 15 to the nonvolatile memory unit 16 Due to the voltage difference at the second storage node SNB, only one of the first switch transistor 18a and the second switch transistor 18b is turned on.

  In the nonvolatile memory unit 16, a voltage difference and an on-current generated between the first switch transistor 18a and the first memory transistor 19a that are turned on or between the second switch transistor 18b and the second memory transistor 19b that are turned on. Thus, charges are injected into the floating gates FGa and FGb of either the first memory transistor 19a or the second memory transistor 19b.

  As a result, in the nonvolatile SRAM memory cell 2, the voltage required for the program operation and the program blocking operation in the nonvolatile memory unit 16 can be lowered, and accordingly, the program operation and the program blocking operation in the nonvolatile memory unit 16 are performed. Therefore, the voltage at the first storage node SNT and the second storage node SNB applied to the nonvolatile memory unit 16 can also be lowered.

  Thus, in the nonvolatile SRAM memory cell 2, the first access transistor 21a, the second access transistor 21b, the first load transistor 22a, the second load transistor 22b, and the first drive transistor 23a constituting the SRAM 15 connected to the nonvolatile memory unit 16 are provided. The voltage applied to the second drive transistor 23b can be lowered by that amount, and the film thickness of each gate insulating film can be formed to 4 nm or less.

  Therefore, in the nonvolatile semiconductor memory device 1 including the nonvolatile SRAM memory cell 2, the first access transistor 21a, the second access transistor 21b, the first load transistor 22a, the second load transistor 22b, and the first drive constituting the SRAM 15 are provided. Since the gate insulating films of the transistor 23a and the second drive transistor 23b can be formed to 4 nm or less, the SRAM 15 can be operated at a high speed with a low power supply voltage. Thus, in the nonvolatile semiconductor memory device 1, the SRAM data of the SRAM 15 can be written into the nonvolatile memory unit 16, and a high-speed operation in the SRAM 15 can be realized.

  Further, since the potentials of the first storage node SNT and the second storage node SNB are 0 [V] or the power supply voltage VDD during the program operation in the nonvolatile memory unit 16, the first switch transistor 18a and the second switch transistor 18b The gate voltage required for the on / off operation of the first switch transistor 18a and the second switch transistor 18b is not required as long as it is equal to or lower than the power supply voltage VDD. The film can also be formed to 4 [nm] or less. As described above, in the nonvolatile SRAM memory cell 2, the first switch transistor 18a and the second switch transistor 18b can be formed so that the gate insulating films of the first switch transistor 18a and the second switch transistor 18b can be formed to 4 nm or less. As a result, the gate length can be reduced. Thus, it is possible to increase the speed of writing the memory data of the nonvolatile memory unit 16 to the SRAM 15 and reduce the cell size of the nonvolatile memory unit 16.

  In the nonvolatile semiconductor memory device 1, the first storage node SNT and the first storage node SNT are connected to the first storage node SNT through the complementary first bit line BLT1 and the complementary second bit line BLB1 during the program operation for writing the SRAM data of the SRAM 15 into the nonvolatile memory unit 16. (2) After detecting the voltage of the storage node SNB, the low-level voltage logically inverted is applied to the first storage node SNT or the second storage node SNB to which the high-level voltage is applied, and the low level Data in which a logically inverted high level voltage is applied to the other second storage node SNB or first storage node SNT to which the level voltage is applied, and the inverted SRAM data is written to the nonvolatile memory unit 16 An inversion circuit 4 is provided.

  As described above, in the nonvolatile SRAM memory cell 2, before the SRAM data is written in the nonvolatile memory unit 16, inverted data obtained by logically inverting the SRAM data is stored in the SRAM 15 in advance, and the inverted data is stored in the nonvolatile memory unit 16. ("(2-5-2) Memory data write operation according to the second embodiment").

  Thereby, in the nonvolatile SRAM memory cell 2, when the memory data held in the nonvolatile memory unit 16 is written to the SRAM 15, the memory source line MS1 is set to 0 [V], and no charge is accumulated (threshold voltage Vth). <0 [V]) The first storage node SNT or the second storage node SNB on the first memory transistor 19a or second memory transistor 19b side can be connected to the memory source line MS1 of 0 [V].

  Thereby, in the nonvolatile SRAM memory cell 2, the same low level voltage as before the inversion can be applied to the first storage node SNT or the second storage node SNB to which the low level voltage has been applied before the inversion. Thus, in such a program operation according to the second embodiment, the memory source line MS1 can be maintained at 0 [V], and the low-level voltage of the nonvolatile memory unit 16 is sent to the SRAM 15 by the memory source line MS1. Therefore, the operation is as simple and stable as the write operation performed on the SRAM 15 from the outside, and a high-speed and low-voltage operation is possible.

  In the above-mentioned “(2-5-3) Memory data write operation according to the third embodiment”, the SRAM data is not inverted during the program operation for writing the SRAM data of the SRAM 15 to the nonvolatile memory unit 16, and then the nonvolatile data is stored. The SRAM data is inverted after the memory data held in the memory unit 16 is written to the SRAM 15.

  Specifically, when the memory data held in the nonvolatile memory unit 16 is written to the SRAM 15, whether or not charge is injected into the floating gates FGa and FGb of the first memory transistor 19a and the second memory transistor 19b of the nonvolatile memory unit 16 is determined. After applying the low level and high level voltages to the first storage node SNT and the second storage node SNB to latch the data, the bit information (the low level and the first storage node SNT and the second storage node SNB High level state) is read to the data inverting circuit 4 via the complementary first bit line BLT1 and the complementary second bit line BLT2, and the high level and low level voltages inverted by the data inverting circuit 4 are stored in the first storage. Applied to the node SNT and the second storage node SNB to be latched.

  As a result, in the memory data write operation according to the third embodiment, in addition to the effect of the memory data write operation according to the second embodiment described above, the SRAM data during the program operation for writing the SRAM data of the SRAM 15 to the nonvolatile memory unit 16 is provided. Since the data is not inverted, the SRAM data can be quickly written into the nonvolatile memory unit 16.

  According to the above configuration, in the nonvolatile semiconductor memory device 1, a voltage (storage node voltage) required for a program operation for writing SRAM data to the nonvolatile memory unit 16 and a program blocking operation for not writing SRAM data to the nonvolatile memory unit 16. 1), the first access transistor 21a, the second access transistor 21b, the first load transistor 22a, the second load transistor 22b, the first drive transistor 23a, which constitute the SRAM 15 connected to the nonvolatile memory unit 16. The gate insulating film thickness of each of the second drive transistor 23b and the second drive transistor 23b can be formed to 4 [nm] or less, and accordingly, the SRAM 15 can be operated at a high speed with a low power supply voltage. 16 can be written, and high speed operation in the SRAM15 is realized. That.

(4) Other Embodiments (4-1) Nonvolatile SRAM Memory Cell with Plurality of Nonvolatile Memory Units Connected in Parallel Here, in the above-described embodiment, one non-volatile memory for one SRAM 15 The nonvolatile SRAM memory cell 2 to which the unit 16 is connected has been described. However, the present invention is not limited to this, and a single SRAM 15 is shown in FIG. Thus, a nonvolatile SRAM memory cell 55a in which a plurality of nonvolatile memory sections 16a, 16b, 16c, and 16d are connected in parallel may be used.

  In this embodiment, the SRAM 15 has a first common wiring 54a connected to the first storage node SNT and a second common wiring 54b connected to the second storage node SNB. In each nonvolatile memory unit 16a, 16b, 16c, 16d, one end of the first switch transistor 18a is connected to the first storage node SNT of the SRAM 15 via the first common wiring 54a, and one end of the second switch transistor 18b is The configuration is connected to the second storage node SNB of the SRAM 15 via the second common wiring 54b.

  The nonvolatile SRAM memory cell 55a is provided with memory gate lines MGa, MGb, MGc, MGd and memory source lines MSa, MSb, MSc, MSd for each nonvolatile memory unit 16a, 16b, 16c, 16d. Therefore, a voltage necessary for writing the SRAM data can be applied to the first memory transistor 19a and the second memory transistor 19b for each of the nonvolatile memory sections 16a, 16b, 16c, and 16d. Further, the nonvolatile SRAM memory cell 55a includes a first switch gate line CGTa, CGTb, CGTc, CGTd, and a second switch gate line CGBa, CGBb, CGBc, CGBd. The first switch transistor 18a and the second switch transistor 18b can be turned on / off for each nonvolatile memory unit 16a, 16b, 16c, 16d.

  Thus, the non-volatile SRAM memory cell 55a includes, for example, a non-volatile memory unit 16a arbitrarily selected from a plurality of non-volatile memory units 16a, 16b, 16c, and 16d by the on / off operation of the first switch transistor 18a and the second switch transistor 18b. Only the SRAM data is connected to the SRAM 15, and the SRAM data held in the first storage node SNT and the second storage node SNB of the SRAM 15 can be written only in the nonvolatile memory unit 16a.

  In addition, the nonvolatile SRAM memory cell 55a includes, for example, a nonvolatile memory unit 16a arbitrarily selected from a plurality of nonvolatile memory units 16a, 16b, 16c, and 16d by the on / off operation of the first switch transistor 18a and the second switch transistor 18b. Can be connected to the SRAM 15, and the memory data held in the nonvolatile memory unit 16a can be written to the first storage node SNT and the second storage node SNB of the SRAM 15.

  Here, FIG. 15 shows a schematic view when a plurality of nonvolatile SRAM memory cells 55a, 55b,..., 55z are provided. In this case, each of the nonvolatile SRAM memory cells 55a, 55b,..., 55z, for example, shares the first switch gate line CGTa and the second switch gate line CGBa in each nonvolatile memory unit 16a at the first stage, and the second stage. Each non-volatile memory unit 16b shares the first switch gate line CGTb and the second switch gate line CGBb, and each non-volatile memory unit 16c in the third stage uses the first switch gate line CGTc and the second switch gate line CGBc. The first switch gate line CGTd and the second switch gate line CGBd are shared by the nonvolatile memory units 16d in the fourth stage.

  Thereby, the nonvolatile SRAM memory cells 55a, 55b,..., 55z are connected to the first switch gate line CGTa and the second switch gate line CGBa in the first stage, and the first switch gate line CGTb and the second switch gate in the second stage. A predetermined voltage is individually applied to the line CGBb, the first switch gate line CGTc and the second switch gate line CGBc in the third stage, and the first switch gate line CGTd and the second switch gate line CGBd in the fourth stage. As a result, the first switch transistor 18a and the second switch transistor 18b in the first to fourth stages can be individually turned on and off for each stage. Thus, the nonvolatile SRAM memory cells 55a, 55b,..., 55z can write the memory data to all the SRAMs 15 in a batch for each of the first to fourth nonvolatile memory units 16a, 16b, 16c, and 16d. it can.

  Incidentally, as a conventional circuit configuration including a large-capacity nonvolatile memory unit and an SRAM, as shown in FIG. 16A, a large-capacity (for example, 8 [KByte]) nonvolatile memory unit 51, a CPU 52, and the nonvolatile circuit A configuration in which an SRAM 15 having a smaller capacity (for example, 2 [KByte]) than the memory unit 51 is connected via a bus (BUS) is known. In such a conventional circuit configuration, when the memory data of the nonvolatile memory unit 51 is written to the SRAM 15 in accordance with a command from the CPU 52, the predetermined memory data is read from the nonvolatile memory unit 51 and sent to the SRAM 15 via the BUS. There is a need to.

  When the SRAM data of the SRAM 15 is written to the nonvolatile memory unit 51, the SRAM data is sent to the nonvolatile memory unit 51 via the BUS, and the SRAM data is designated by specifying a predetermined area in the nonvolatile memory unit 51. Need to write. For this reason, in the conventional circuit configuration, it is necessary to exchange data with the SRAM 15 because it is necessary to transmit / receive data via the BUS or to select a necessary storage area from the large-capacity nonvolatile memory unit 51. There was a problem of taking time.

  In contrast, in the nonvolatile SRAM memory cell 55a of the present invention, the first to fourth nonvolatile memory sections 16a, 16b, 16c, and 16d are divided by the first switch transistor 18a and the second switch transistor 18b. As shown in FIG. 16B, the memory data can be written into the SRAM 15 at once for each nonvolatile memory section 16a, 16b, 16c, 16d by simply turning on and off the first switch transistor 18a and the second switch transistor 18b. it can. Thus, in the nonvolatile SRAM memory cell 55a, the necessary memory data is read out from the large-capacity nonvolatile memory unit 51 and the memory data is written to the SRAM 15 via the BUS as in the conventional case. Data can be exchanged with the SRAM 15 in time. Here, the non-volatile SRAM memory cell 55a of the present invention includes the four non-volatile memory units 16a, 16b, 16c, and 16d during a program operation and a memory data erasing operation in the non-volatile memory units 16a, 16b, 16c, and 16d. There is a degree of freedom in which any one of the memory areas can be selected. In general, a program operation or a memory data erasing operation can be performed in a memory area (nonvolatile memory units 16a, 16b, 16c, 16d) arbitrarily selected by the user.

  Next, in such a non-volatile SRAM memory cell 55a, a program operation for writing SRAM data from the SRAM 15 to the non-volatile memory units 16a, 16b, 16c, 16d, and memory data in the non-volatile memory units 16a, 16b, 16c, 16d A program operation and a memory data erasing operation that can efficiently perform the erasing operation, reduce the time required for the program operation and the memory data erasing operation, and further save the history of stored information will be described below. As shown in FIG. 17, in the nonvolatile SRAM memory cell 55a, first, the SRAM data of the SRAM 15 is written into the first-stage nonvolatile memory unit 16a, and at the same time as the program operation for writing this SRAM data, The memory data of the second stage non-volatile memory portion 16b to which SRAM data is to be written can be erased in advance.

  In practice, at this time, in the first stage nonvolatile memory unit 16a, the first switch transistor 18a and the second switch transistor 18b (FIG. 14) are turned on, and the first storage node SNT and the second storage node SNB of the SRAM 15 Can be electrically connected. At this time, in the second to fourth nonvolatile memory units 16b, 16c, and 16d, the first switch transistor 18a and the second switch transistor 18b are turned off, and the first storage node SNT and the second storage of the SRAM 15 are turned off. The electrical connection with the node SNB can be cut off.

  Thereby, in the nonvolatile SRAM memory cell 55a, the SRAM data of the SRAM 15 can be written only in the first-stage nonvolatile memory unit 16a. In addition, the second-stage nonvolatile memory unit 16b includes a memory gate line MGb and a memory source line MSb, the other first-stage nonvolatile memory unit 16a, the third-stage nonvolatile memory unit 16c, and the fourth-stage nonvolatile memory. Since the voltage of the memory gate line MGb and the memory source line MSb is adjusted, the floating gate FGa of either the first memory transistor 19a or the second memory transistor 19b is provided. , The charge injected into FGb can be extracted to erase the memory data.

  The non-volatile SRAM memory cell 55a has a plurality of non-volatile memory units 16a, 16a, 16d when new SRAM data written to the SRAM 15 from the outside is to be written to any of the non-volatile memory units 16a, 16b, 16c, 16d. Of 16b, 16c, and 16d, SRAM data is written into the second-stage nonvolatile memory unit 16b from which memory data has already been erased. Also at this time, the non-volatile SRAM memory cell 55a can previously erase the memory data of the third-stage non-volatile memory portion 16c to which new SRAM data is to be written next.

  After that, when the non-volatile SRAM memory cell 55a tries to write new SRAM data written to the SRAM 15 from the outside into any of the non-volatile memory units 16a, 16b, 16c, 16d, there are a plurality of non-volatile memory units 16a, 16b. , 16c, 16d of the fourth stage non-volatile memory section 16d to which new SRAM data is to be written next, at the same time, is written to the third stage non-volatile memory section 16c from which memory data has already been erased. Memory data can be erased in advance. The non-volatile SRAM memory cell 55a has a plurality of non-volatile memory units 16a, 16a, 16d when new SRAM data written to the SRAM 15 from the outside is to be written to any of the non-volatile memory units 16a, 16b, 16c, 16d. Of the 16b, 16c, and 16d, the SRAM data is written into the fourth-stage nonvolatile memory unit 16d in which the memory data has already been erased, and at the same time, the first-stage nonvolatile memory to which new SRAM data is to be written next The memory data in the memory unit 16a can be erased.

  As described above, in the nonvolatile SRAM memory cell 55a, for example, when SRAM data written to the SRAM 15 from the outside is written to the nonvolatile memory unit 16a, the memory data of the other nonvolatile memory unit 16b associated with the nonvolatile memory unit 16a is stored. The non-volatile memory portion 16b (16a, 16c, 16d) in which memory data is always erased is secured at the same time. Thus, the non-volatile SRAM memory cell 55a can immediately store the SRAM data in the non-volatile memory as compared with the case where, for example, when the SRAM data is written in the second-stage non-volatile memory unit 16b, the memory data in the non-volatile memory unit 16b starts to be erased. Since the data can be written to the unit 16b, the SRAM data writing time can be shortened. Further, in the nonvolatile SRAM memory cell 55a, for example, the past three generations of SRAM data can be held in the nonvolatile memory units 16a, 16b, and 16c as memory data for each generation. , 16c can be read out to the SRAM 15 as needed.

  In the above-described embodiment, the case where the nonvolatile memory sections 16a, 16b, 16c, and 16d arranged in four stages is described. However, the present invention is not limited to this, and two stages, three stages, and the like. Nonvolatile memory units arranged in a plurality of stages may be applied.

(4-2) Non-Volatile Memory Unit Control Circuit According to Other Embodiments In the above-described embodiment, as shown in FIG. 1, memory gates are arranged for non-volatile SRAM memory cells 2 arranged in a matrix. Lines MG0, MG1, MG2, MG3, first switch gate lines CGT0, CGT1, CGT2, CGT3, second switch gate lines CGB0, CGB1, CGB2, CGB3, and memory source lines MS0, MS1, MS2, MS3 in row units These memory gate lines MG0, MG1, MG2, MG3, first switch gate lines CGT0, CGT1, CGT2, CGT3, second switch gate lines CGB0, CGB1, CGB2, CGB3, and memory source lines MS0, MS1, MS2, Although the nonvolatile semiconductor memory device 1 provided with the nonvolatile memory unit control circuit 11 that applies a predetermined voltage to the MS 3 in units of rows has been described, the present invention is not limited to this, and the same reference numerals are given to the corresponding parts to FIG. As shown in FIG. 18, the nonvolatile SRAM memory cells 2 arranged in a matrix are shared. Memory gate line MG, first switch gate line CGT, second switch gate line CGB, and memory source line MS are provided, and these memory gate line MG, first switch gate line CGT, second switch gate line CGB, and memory are provided. A nonvolatile semiconductor memory device 61 provided with a nonvolatile memory unit control circuit 62 that applies a predetermined voltage to the source lines MS all at once may be used.

  Here, all of the SRAM 15 can be controlled with a voltage equal to or lower than the power supply voltage VDD. However, since the nonvolatile memory unit 16 requires a relatively high voltage for writing the SRAM data, the voltage is supplied to the nonvolatile memory unit 16 for control. It is effective from the viewpoint of reducing the module size and simplifying the write operation to simplify the nonvolatile memory unit control circuit as much as possible. In this regard, in the nonvolatile semiconductor memory device 61 shown in FIG. 18, the common memory gate line MG, the first switch gate line CGT, the second switch gate line CGB, and the memory source line MS are connected by the nonvolatile memory unit control circuit 62. Since all can be collectively controlled within the mat, control in units of rows becomes unnecessary as compared with the nonvolatile semiconductor memory device 1 shown in FIG. Therefore, in the non-volatile semiconductor memory device 61, only one non-volatile memory unit control circuit 62 is required in the mat, so that the area can be reduced and simple control can be realized, and further, the program operation and the memory data erasing operation can be performed. Since it can be performed in batches, the time required for these program operations and memory data erase operations can be shortened.

(4-3) Nonvolatile Memory Unit According to Other Embodiments In the embodiment described above, as shown in FIG. 4A, the second switch transistor 18b having the switch gate electrode 40 and the memory gate electrode 39 are arranged. The second memory cell 17b having the configuration in which the second memory transistor 19b is adjacently connected in series and injecting charges into the floating gate FGb by source side injection during the SRAM data program operation has been described. The invention is not limited to this, and the first memory cell and the second memory cell having various configurations may be applied as long as charges can be injected into the floating gate by source-side injection during the SRAM data program operation.

  Hereinafter, the second memory cell according to another embodiment is shown in FIGS. 19A, 20A, and 21A, and these FIGS. 19A, 20A, and 21A focus on the second memory cell in accordance with FIG. 4A. FIG. Note that the first memory cell that constitutes the nonvolatile memory portion together with the second memory cell has the same configuration as the second memory cell, and thus the description thereof is omitted.

(4-3-1) Nonvolatile Memory Part Consisting of First Memory Cell and Second Memory Cell Having Erase Transistor FIG. 19A, in which parts corresponding to those in FIG. 4 is a schematic diagram showing a cross-sectional configuration of a second memory cell 65. FIG. In this case, the second memory cell 65 is erased on the other source / drain region 36 connected to the memory source line MS1 so as to cover the side surface of the memory gate electrode 39 and the corner portion of the upper end of the side surface of the floating gate FGb. A gate electrode 66 is disposed, and an erase transistor 67 is formed. An erase gate line EG1 is connected to the erase gate electrode 66, and a predetermined voltage can be applied via the erase gate line EG1.

  The erase gate line EG1 is shared by the first memory cell (not shown) and the second memory cell 65, and a predetermined voltage is uniformly applied to the first memory cell and the second memory cell 65. Can do. The erase gate line EG1 is provided for each row of the nonvolatile SRAM memory cells 2 when the nonvolatile SRAM memory cells 2 are arranged in a matrix as shown in FIG. Thus, a predetermined voltage can be uniformly applied to the nonvolatile memory unit in units of rows.

  Here, FIG. 19B corresponding to FIG. 4B uses a non-volatile memory unit including the second memory cell 65 shown in FIG. 19A and a first memory cell having the same configuration as the second memory cell 65. An example of the voltage at each part is shown. “Program (sram to flash)” in FIG. 19B indicates a voltage at each part during a program operation for writing SRAM data from the SRAM 15 to the nonvolatile memory unit, and “Erase (reset data in flash)” is the nonvolatile memory unit. Indicates the voltage at each part during the memory data erasing operation, and “Write (external data to sram)” indicates the voltage at each part during the external data writing operation for writing external data to the SRAM 15 from the outside. “Read (output sram data)” indicates the voltage at each part during the data read operation from the SRAM 15.

  In this case, in the program operation, for example, 10 [V] is applied to the memory gate line MG1, and 6 [V] is applied to the memory source line MS1 and the erase gate line EG1, respectively. Thus, in the nonvolatile memory unit, when the second storage node SNB is at the low level, for example, as in “(2-3) Program operation for writing SRAM data from the SRAM to the nonvolatile memory unit”, the second storage node SNB Charges can be injected into the floating gate FGb by source-side injection caused by a current flowing in a strong electric field region between the second memory transistor 19b and the first switch transistor 18b in the nonvolatile memory unit connected to the. When one of the first storage nodes SNT (not shown in FIG. 19A) is at a low level, the strength between the first memory transistor 19a and the first switch transistor 18a of the nonvolatile memory portion connected to the first storage node SNT is strong. Charges can be injected into the floating gate FGa by source side injection caused by current flowing in the electric field region.

  In the memory data erasing operation, for example, 0 [V] can be applied to the memory gate line MG1 and the memory source line MS1, respectively, and 12 [V] can be applied to the erase gate line EG1. Thereby, for example, in the second memory cell 65 in which the charge is stored in the floating gate FGb, electrons can be emitted from the floating gate FGb to the erase transistor 67, and the memory data can be erased.

(4-3-2) Non-volatile memory portion including first memory cell and second memory cell provided with shared gate electrode FIG. 20A is shown in FIG. 4 is a schematic diagram showing a cross-sectional configuration of a second memory cell 68 according to FIG. In this case, the second memory cell 68 shares the gate electrode of the second switch transistor 18b and the gate electrode of the second memory transistor 19b on the second semiconductor region ER2 between the source / drain regions 36 and 37. One shared gate electrode 69 is provided, and the second switch gate line CGB1 is connected to the shared gate electrode 69.

  In practice, the second memory cell 68 is provided with a shared gate electrode 69 on the second semiconductor region ER2 so as to be adjacent to the source / drain region 37, and the second memory cell 68 is provided between the source / drain region 37 and the floating gate FGb. A two-switch transistor 18b can be configured. Further, a second memory transistor 19b having a floating gate FGb as a gate can be formed between the second switch transistor 18b and the source / drain region 36.

  Furthermore, by forming the shared gate electrode 69 so as to cover the corner portion at the upper end of the side wall of the floating gate FGb, when a predetermined voltage is applied to the second switch gate line CGB1, electrons are emitted by the strong electric field at the corner portion of the floating gate. In addition, the shared gate electrode 69 covering the corner portion can be configured as an erasing element. The second memory cell 68 does not have an electrode corresponding to the memory gate electrode 39 (FIGS. 4A and 19A). However, the second memory cell 68 has a region where the source / drain region 36 and the floating gate FGb overlap with the gate insulating film interposed therebetween, and the potential of the floating gate FGb can be controlled by the potential of the memory source line MS1 by capacitive coupling. Thus, the function of the memory gate electrode 39 is supplemented.

  Here, FIG. 20B corresponding to FIG. 4B is a nonvolatile memory including the second memory cell 68 shown in FIG. 20A and a first memory cell (not shown) having the same configuration as the second memory cell 68. An example of the voltage in each part when using a memory part is shown. In this case, during the program operation indicated by “Program (sram to flash)” in FIG. 20B, for example, the power supply voltage VDD is applied to the first switch gate line CGT1 and the second switch gate line CGB1, respectively, and the memory source line MS1 is applied. 10 [V] is applied.

  At this time, in the second memory cell 68, the potential of the floating gate FGb rises due to capacitive coupling generated in the region where the source / drain region 36 and the floating gate FGb overlap, and the channel of the second memory transistor 19b is turned on, Most of the potential of the memory source line MS1 can be transmitted to the vicinity of the boundary between the second memory transistor 19b and the second switch gate line CGB1.

  Thus, in the nonvolatile memory unit, when the second storage node SNB is at the low level, for example, as in “(2-3) Program operation for writing SRAM data from the SRAM to the nonvolatile memory unit”, the second storage node SNB Charges can be injected into the floating gate FGb by source-side injection caused by a current flowing in a strong electric field region between the second memory transistor 19b and the second switch transistor 18b in the nonvolatile memory portion connected to the. When one of the first storage nodes SNT (not shown in FIG. 20A) is at a low level, the strength between the first memory transistor 19a and the first switch transistor 18a of the non-volatile memory connected to the first storage node SNT is strong. Charges can be injected into the floating gate FGa by source side injection caused by current flowing in the electric field region.

  In addition, during the memory data erasing operation indicated by “Erase (reset data in flash)”, for example, 12 [V] is applied to the first switch gate line CGT1 and the second switch gate line CGB1, respectively, and the memory source line MS1 is applied. 0 [V] may be applied. Thereby, for example, in the second memory cell 68 in which charges are accumulated in the floating gate FGb, charges (electrons) can be discharged from the floating gate FGb to the second switch gate line CGB1, and memory data can be erased.

(4-3-3) Non-volatile memory unit composed of first memory cell and second memory cell in which erase transistors are separately formed. FIG. 21A, in which parts corresponding to those in FIG. 4 is a schematic diagram showing a cross-sectional configuration of a second memory cell 70 according to an embodiment. FIG. In this case, the second memory cell 70 has a source / drain region 74 between the switch gate electrode 40 of the second switch transistor 18b and the memory gate electrode 75 of the second memory transistor 19b, and the second switch transistor 18b and the second memory transistor 19b share the source / drain region 74, and the second switch transistor 18b and the second memory transistor 19b are arranged in series. In practice, in the second memory transistor 19b, a memory gate electrode 75 serving as a floating gate FGb is formed between the source / drain regions 36 and 74 and a part of the source / drain region 36 via a gate insulating film.

  An erase transistor 77 is formed in the second memory cell 70. The erase transistor 77 has the same conductivity type transistor configuration as the second switch transistor 18b and the second memory transistor 19b, and both are formed in the second semiconductor region ER2. In this case, in the second semiconductor region ER2, the second active region EA2 is formed apart from the first active region EA1 in which the second switch transistor 18b and the second memory transistor 19b are formed. An erase transistor 77 is formed in the active region EA2.

  Actually, in the erase transistor 77, source / drain regions 71, 72 are formed on the second active region EA2 with a space therebetween, and the erase line E1 is connected to the source / drain region 71 on at least one end thereof. On the second active region EA2 between the source / drain regions 71 and 72, an erase gate electrode 73 serving as a floating gate FGb is formed via a gate insulating film, and the erase gate electrode 73 is connected to the second memory transistor 19b. The memory gate electrode 75 is connected.

  Here, FIG. 21B corresponding to FIG. 4B is a nonvolatile memory including the second memory cell 70 shown in FIG. 21A and a first memory cell (not shown) having the same configuration as the second memory cell 70. An example of the voltage in each part when using a memory part is shown. In this case, during the program operation indicated by “Program (sram to flash)” in FIG. 21B, for example, the power supply voltage VDD is applied to the first switch gate line CGT1 and the second switch gate line CGB1, respectively, and the memory source line MS1 is applied. 10 [V] is applied, and 0 [V] is further applied to the erase gate line EG1.

  Thus, in the nonvolatile memory unit, when the second storage node SNB is at the low level, for example, as in “(2-3) Program operation for writing SRAM data from the SRAM to the nonvolatile memory unit”, the second storage node SNB Charges can be injected into the floating gate FGb by source-side injection caused by a current flowing in a strong electric field region between the second memory transistor 19b and the second switch transistor 18b in the nonvolatile memory portion connected to the. When one of the first storage nodes SNT (not shown in FIG. 21A) is at a low level, the strength between the first memory transistor 19a and the second switch transistor 18a of the nonvolatile memory portion connected to the first storage node SNT is strong. Charges can be injected into the floating gate FGa by source side injection caused by current flowing in the electric field region.

  In the memory data erasing operation indicated by “Erase (reset data in flash)”, for example, 0 [V] is applied to the first switch gate line CGT1, the second switch gate line CGB1, and the memory source line MS1, respectively. Furthermore, 10 [V] can be applied to the erase line E1. Thereby, for example, in the second memory cell 70 in which charges are accumulated in the floating gate FGb, electrons can be emitted or holes are injected from the memory source line MS1 side into the floating gate FGb, and memory data can be erased.

  Here, in the description of the memory data erasing operation of the present invention, the case where the memory data erasing operation is performed by applying a high voltage to the diffusion layer has been described. However, the present invention is realized by using the data in the nonvolatile memory portion. Is performed by source-side injection, the voltage in the SRAM that applies a voltage to the nonvolatile memory portion can also be lowered, and the SRAM can be configured with a thin film transistor correspondingly. Therefore, the memory data erasing operation and its method are not essential. Therefore, as the memory data erasing operation, for example, various erasing methods may be used such as using a coupling capacitor connected to the floating gate to efficiently transmit the erasing voltage to the floating gate and accelerating the erasing operation. An erasing method using a conductive diffusion layer may be used.

  In the present invention, a non-volatile memory unit in which the structures of the second memory cells 65, 68, and 70 shown in FIGS. 19A, 20A, and 21A are appropriately combined may be used. As shown in FIG. The nonvolatile memory unit having the structure may be a nonvolatile SRAM memory cell connected in parallel to one SRAM.

(4-3-4) Structure of Charge Storage Area of Nonvolatile Memory Unit In the above-described embodiment, floating gates FGa and FGb are used as charge storage areas indicating whether data is written depending on whether charge is stored. As described above, the present invention is not limited to this. For example, a discrete trap type charge accumulation region may be used as a charge accumulation region that obtains the same effect.

  In this case, the first memory transistor and the second memory transistor having the discrete trap type charge storage region are formed on the semiconductor substrate (second semiconductor region ER2) that becomes the channel region, for example, via the gate insulating film. Alternatively, a discrete trap type charge accumulation region made of a compound of hafnium and silicon or the like is provided, and a memory gate electrode is provided on the charge accumulation region via a gate insulating film. In this case, in the first memory transistor and the second memory transistor, the gate insulating film between the charge storage region and the second semiconductor region ER2, the gate insulating film between the charge storage region and the memory gate electrode, and the charge storage Operations and effects similar to those of the above-described embodiment can be obtained by appropriately adjusting the film thickness of the region.

(4-4) Program Operation According to Other Embodiments In the above-described embodiment, as shown in FIG. 1, complementary first bit lines BLT0, BLT1, BLT2, BLT3 and complementary second bit lines The nonvolatile semiconductor device 1 in which the data inverting circuit 4 is separately provided outside the BLB0, BLB1, BLB2, and BLB3 has been described. In this nonvolatile semiconductor memory device 1, in order to invert the bit information, the information stored in the nonvolatile SRAM memory cell 2 is changed to the potential relationship between the complementary first bit line BLT1 and the complementary second bit line BLB1, for example. It is necessary to convert, and it is difficult to invert the information of the plurality of nonvolatile SRAM memory cells 2 connected to the complementary first bit line BLT1 and the complementary second bit line BLB1 at a time.

  Therefore, in the nonvolatile semiconductor memory device of the present invention according to another embodiment, the memory operation that writes the SRAM data held in the SRAM 15 to the nonvolatile memory unit 16 and the memory data that writes the memory data held in the nonvolatile memory unit 16 to the SRAM 15 are performed. During the data write operation, in the nonvolatile SRAM memory cell 2, the connection relationship between the first memory cell and the second memory cell, and the first storage node SNT and the second storage node SNB is switched, and the nonvolatile SRAM memory cell Logic inversion may be performed every two.

  In this case, in the nonvolatile semiconductor memory device, processing for performing logic inversion outside the nonvolatile SRAM memory cell 2 is not necessary, and all the word lines WL0, WL1, WL2, WL3 are kept in an off operation state, for example. A program operation and a memory data write operation can be performed at a time on the plurality of nonvolatile SRAM memory cells 2 connected to the complementary first bit line BLT1 and the complementary second bit line BLB1.

  Here, the nonvolatile SRAM memory cell 85 shown in FIG. 22A and the nonvolatile SRAM memory cell 95 shown in FIG. 22B do not use the data inverting circuit 4 shown in FIG. The logical inversion can be performed between the SRAM 15 and the nonvolatile memory unit 16 by appropriately switching the connection relationship between the first memory transistor 19a and the second memory transistor 19b and the first storage node SNT and the second storage node SNB.

  In the nonvolatile semiconductor device provided with such nonvolatile SRAM memory cells 85 and 95, although the data inverting circuit 4 shown in FIG. 1 is unnecessary, the same effect as the data inverting circuit 4 can be obtained. Since it is not necessary to provide an independent step of inverting the bit information described in “(2-5) Memory data write operation for writing memory data of nonvolatile memory unit to SRAM”, the data of SRAM 15 and nonvolatile memory unit 16 is Communication can be simplified.

  In the nonvolatile semiconductor memory device provided with the nonvolatile SRAM memory cells 85 and 95, the program operation from the SRAM 15 to the nonvolatile memory unit 16 and the memory data writing operation from the nonvolatile memory unit 16 to the SRAM 15 are performed on the entire memory mat. Since it can be performed in a lump, the processing time can be greatly reduced. Hereinafter, the nonvolatile SRAM memory cells 85 and 86 will be individually described.

  (4-4-1) Nonvolatile SRAM memory cell in which connection configuration of first switch transistor and second switch transistor to first storage node and second storage node is changed

  The nonvolatile SRAM memory cell 85 includes a first memory cell 86a and a second memory cell 86b in the nonvolatile memory section 16, as shown in FIG. In this case, the first memory cell 86a includes a first memory transistor 19a, an N-type MOS first switch transistor 87a connected in series to one end of the first memory transistor 19a, and the one end of the first memory transistor 19a. And an N-type MOS first read transistor 88a connected in series. In addition, the first memory cell 86a has one end of the first switch transistor 87a connected in series to the first memory transistor 19a connected to the second storage node SNB and connected to the one end of the first memory transistor 19a. One end of the first read transistor 88a connected in series is connected to the first storage node SNT.

  On the other hand, the second memory cell 86b also has the same configuration as the first memory cell 86a, and includes a second memory transistor 19b and a second switch transistor 87b connected in series to one end of the second memory transistor 19b. And a second read transistor 88b connected in series to the one end of the second memory transistor 19b. The second memory cell 86b has one end of the second switch transistor 87b connected in series to the second memory transistor 19b connected to the first storage node SNT and the other end of the second memory transistor 19b. One end of the second read transistor 88b connected in series is connected to the second storage node SNB.

  Further, in this case, the first switch transistor 87a and the second switch transistor 87b have a configuration in which each gate is connected to a common program gate line CGP1. In this case, the first read gate line RGT1 is connected to the gate of one first read transistor 88a, and the second read transistor 88b is connected to the first read gate line RGT1 separately from the first read gate line RGT1. 2 Read gate line RGB1 is connected to the gate. By changing the voltage applied to the first read gate line RGT1 and the second read gate line RGB1, the first read transistor and the second read transistor are individually turned on and off. It is made to work.

  In such a nonvolatile SRAM memory cell 85, in a program operation for writing SRAM data from the SRAM 15 to the nonvolatile memory unit 16, 0 [V] is applied to the first read gate line RGT1 and the second read gate line RGB1, respectively. The first read transistor 88a and the second read transistor 88b are turned off. At this time, the power supply voltage VDD can be applied to the program gate line CGP1, the voltage of 6 [V] can be applied to the memory source line MS1, and the voltage of 7 [V] can be applied to the memory gate line MG1. .

  Here, the case where one first storage node SNT is at the low level and the other second storage node SNB is at the high level before the writing of the SRAM data to the nonvolatile memory unit 16 will be described below. In this case, since the first storage node SNT is 0 [V], the second switch transistor 87b connected to the first storage node SNT can be turned on. As a result, the low voltage of 0 [V] of the first storage node SNT is applied to one end of the second memory transistor 19b via the second switch transistor 87b. As a result, the floating gate FGb is charged by the source side injection. Can be injected.

  At this time, since the second storage node SNB is at the power supply voltage VDD, the first switch transistor 87a connected to the second storage node SNB can be turned off. Thereby, in the first memory transistor 19a, a low voltage of 0 [V] is not applied to one end, and the data write operation does not occur.

  Next, a memory data write operation to the SRAM 15 will be described. In this case, 0 [V] is applied to the program gate line CGP1, and the first switch transistor 87a and the second switch transistor 87b are turned off. Further, the power supply voltage VDD is applied to the first read gate line RGT1 and the second read gate line RGB1, respectively, and 0 [V] is applied to the memory source line MS1. As a result, in the nonvolatile SRAM memory cell 85, the first memory transistor 19a to which no data is written is turned on, the first read transistor 88a is also turned on, and the first storage node SNT is turned on by the first read transistor 88a and The first memory transistor 19a is connected to the 0 [V] memory source line MS1. As a result, when the SRAM 15 is latched, the first storage node SNT goes to the low level, the second storage node SNB goes to the high level, and the original SRAM data before being written in the nonvolatile memory unit 16 can be reproduced in the SRAM 15. .

  In the above configuration, in the nonvolatile SRAM memory cell 85, one first memory transistor 19a is connected to the first storage node SNT via the first read transistor 88a, and the second memory via the first switch transistor 87a. Connected to the storage node SNB, the other second memory transistor 19b is connected to the second storage node SNB via the second read transistor 88b, and connected to the first storage node SNT via the second switch transistor 87b I tried to make it.

  Further, in the nonvolatile SRAM memory cell 85, during the program operation for writing the SRAM data held in the SRAM 15 to the nonvolatile memory unit 16, the first switch transistor 87a or the first switch transistor 87a or the Either one of the second switch transistors 87b is turned on, and the second memory transistor 19b is connected to the first storage node SNT via the second switch transistor 87b that is turned on, or the first switch transistor 87a that is turned on By connecting the first memory transistor 19a to the second storage node SNB via the first storage node SNB, the ethics (Low level and High level) of the SRAM data in the first storage node SNT and the second storage node SNB are transferred to the nonvolatile memory unit 16. Inverted and can be written.

  In addition, in the nonvolatile SRAM memory cell 85, the first memory transistor 19a and the second memory transistor 19b have a charge accumulation state in the memory data write operation for writing the memory data held in the nonvolatile memory unit 16 to the SRAM 15, and the first memory transistor 19b has a first charge. Only one of the memory transistor 19a and the second memory transistor 19b is turned on, and the turned on first memory transistor 19a is connected to the first storage node SNT via the first read transistor 88a or turned on. By connecting the second memory transistor 19b to the second storage node SNB via the second read transistor 88b, the same logic as the ethics (low level or high level) of the first memory transistor 19a is directly applied to the first storage node SNT. The second memory transistor 19 can be written and The same logic as b's ethics can be written to the second storage node SNB.

  Thus, in the nonvolatile SRAM memory cell 85, the logic inversion process outside the nonvolatile SRAM memory cell 85 can be made unnecessary, and the logic inversion process can be executed for each nonvolatile SRAM memory cell 85. Therefore, in the non-volatile SRAM memory cell 85, since the program operation from the SRAM 15 to the non-volatile memory unit 16 and the memory data writing operation from the non-volatile memory unit 16 to the SRAM 15 can be performed at the same time on the entire memory mat, the processing time is greatly reduced. be able to.

  Incidentally, even in this case, since the potential of the first storage node SNT and the second storage node SNB is 0 [V] or the power supply voltage VDD during the program operation in the nonvolatile memory unit 16, the first switch transistor The gate voltage required for the on / off operation of 87a, the second switch transistor 87b, the first read transistor 88a, and the second read transistor 88b only needs to be equal to or lower than the power supply voltage VDD. Since it becomes unnecessary, the gate insulating films of the first switch transistor 87a, the second switch transistor 87b, the first read transistor 88a, and the second read transistor 88b can be formed to 4 [nm] or less.

(4-4-2) Nonvolatile SRAM Memory Cell Provided with Switch Mechanism FIG. 22B, in which the same reference numerals are assigned to corresponding parts to FIG. 2, shows the configuration of the nonvolatile SRAM memory cell 95 provided with the switch mechanism 90. FIG. In this non-volatile SRAM memory cell 95, the SRAM 15 and the non-volatile memory unit 16 are connected to the switch mechanism 90, and at the time of the program operation for writing the SRAM data to the non-volatile memory unit 16, or the memory data writing operation for writing the memory data to the SRAM 15 Occasionally, the connection relationship between the first memory cell 17a and the second memory cell 17b and the first storage node SNT and the second storage node SNB is switched by the switch mechanism 90, and the logic inversion is performed in the nonvolatile SRAM memory cell 95. It can be done.

  In this case, the switch mechanism 90 includes, for example, a pair of an N-type MOS first selection transistor 20a and an N-type MOS second selection transistor 20b connected to the first switch transistor 18a, and a second switch transistor 18b. The third selection transistor 20c of the N-type MOS and the fourth selection transistor 20d of the N-type MOS are connected to each other. A common program gate line CGP1 is connected to each gate of the first selection transistor 20a provided on the first memory cell 17a side and the third selection transistor 20c provided on the second memory cell 17b side. A predetermined voltage can be applied uniformly through the program gate line CGP1. Further, the third select transistor 20c provided on the first memory cell 17a side and the fourth select transistor 20d provided on the second memory cell 17b side are provided with other write signals provided separately from the program gate line CGP1. A gate line CGW1 is connected to each gate, and a predetermined voltage can be uniformly applied via the write gate line CGW1.

  Here, the first selection transistor 20a provided on the first memory cell 17a side has one end connected to one end of the first switch transistor 18a and one end of the second selection transistor 20b, and the other end. The other end of the fourth selection transistor 20d and the second storage node SNB are connected. Further, the second selection transistor 20b paired with the first selection transistor 20a has one end connected to one end of the first selection transistor 20a and one end of the first switch transistor 18a, and the other end connected to the first selection transistor 20a. The other end of the 3-select transistor 20c is connected to the first storage node SNT.

  On the other hand, the third selection transistor 20c provided on the second memory cell 17b side has one end connected to one end of the second switch transistor 18b and one end of the fourth selection transistor 20d, and the other end is The other end of the second selection transistor 20b is connected to the first storage node SNT. The fourth selection transistor 20d that forms a pair with the third selection transistor 20c has one end connected to one end of the third selection transistor 20c and one end of the second switch transistor 18b, and the other end The other end of the first selection transistor 20a is connected to the second storage node SNB.

  That is, the first switch transistor 18a is connected to the second storage node SNB via the first selection transistor 20a, and is also connected to the first storage node SNT via the second selection transistor 20b. The second switch transistor 18b is also connected to the first storage node SNT via the third selection transistor 20c, and is also connected to the second storage node SNB via the fourth selection transistor 20d.

  In such a nonvolatile SRAM memory cell 95, the power supply voltage VDD is applied to the program gate line CGP1, the first switch gate line CGT1, and the second switch gate line CGB1 during a program operation for writing SRAM data from the SRAM 15 to the nonvolatile memory unit 16. Can be applied. At this time, in the nonvolatile SRAM memory cell 95, 0 [V] is applied to the write gate line CGW1, and the second selection transistor 20b on the first memory cell 17a side and the fourth selection transistor 20d on the second memory cell 17b side are applied. And can be turned off. At this time, a voltage of 6 [V] can be applied to the memory source line MS1, and a voltage of 7 [V] can be applied to the memory gate line MG1.

  Here, the case where one first storage node SNT is at the low level and the other second storage node SNB is at the high level before the writing of the SRAM data to the nonvolatile memory unit 16 will be described below. In this case, since the first storage node SNT is 0 [V], the third selection transistor 20c connected to the first storage node SNT is turned on, and accordingly, the third selection transistor 20c The connected second switch transistor 18b is also turned on. As a result, the low voltage of 0 [V] of the first storage node SNT is applied to one end of the second memory transistor 19b via the third selection transistor 20c and the second switch transistor 18b. Thus, charge can be injected into the floating gate FGb.

  At this time, since the second storage node SNB is at the power supply voltage VDD, the first selection transistor 20a connected to the second storage node SNB can be turned off. As described above, since the second selection transistor 20b is also turned off, the low voltage of 0 [V] of the first storage node SNT can be cut off. Thereby, in the memory transistor 19a, the low voltage of 0 [V] is not applied to one end, and the data writing operation does not occur.

  Next, a memory data write operation to the SRAM 15 will be described. In this case, 0 [V] is applied to the program gate line CGP1, and the first selection transistor 20a on the first memory cell 17a side and the third selection transistor 20c on the second memory cell 17b side are turned off. At this time, the power supply voltage VDD is applied to the write gate line CGW1, the first switch gate line CGT1, and the second switch gate line CGB1, and 0 [V] is applied to the memory source line MS1.

  As a result, in the nonvolatile SRAM memory cell 95, only the first memory transistor 19a to which no data is written is turned on, and the first switch transistor 18a and the second selection transistor 20b are also turned on, and the first storage node SNT is turned on. The memory cell is connected to the memory source line MS1 of 0 [V] through the second selection transistor 20b, the first switch transistor 18a, and the first memory transistor 19a. As a result, when the SRAM 15 is latched, the first storage node SNT goes to the low level, the second storage node SNB goes to the high level, and the original SRAM data before being written in the nonvolatile memory unit 16 can be reproduced in the SRAM 15. .

  In the above configuration, in the nonvolatile SRAM memory cell 95, one first storage node SNT is connected to the first switch transistor 18a via the second selection transistor 20b, and the second storage node SNT is connected via the third selection transistor 20c. The other second storage node SNB is connected to the switch transistor 18b via the fourth selection transistor 20d, and connected to the first switch transistor 18a via the first selection transistor 20a. A switch mechanism 90 is also provided for connection.

  In the nonvolatile SRAM memory cell 95, the second selection transistor 20b and the fourth selection transistor 20d are turned off during the program operation for writing the SRAM data held in the SRAM 15 to the nonvolatile memory unit 16, and the first storage nodes SNT and One of the first selection transistor 20a and the third selection transistor 20c is turned on depending on the voltage difference of the second storage node SNB. Thus, in the nonvolatile SRAM memory cell 95, the first memory transistor 19a is connected to the second storage node SNB via the first selection transistor 20a that is turned on, or the third selection transistor 20c that is turned on. By connecting the second memory transistor 19b to the first storage node SNT, the ethics (Low level and High level) of the SRAM data in the first storage node SNT and the second storage node SNB are inverted to the nonvolatile memory unit 16. Can write.

  In the nonvolatile SRAM memory cell 95, the first selection transistor 20a and the third selection transistor 20c are turned off and the first memory is written in the memory data writing operation in which the memory data held in the nonvolatile memory unit 16 is written to the SRAM 15. Only one of the first memory transistor 19a and the second memory transistor 19b is turned on depending on whether charge is accumulated in the transistor 19a and the second memory transistor 19b. As a result, in the nonvolatile SRAM memory cell 95, the first memory transistor 19a that has been turned on is connected to the first storage node SNT via the first switch transistor 18a and the second selection transistor 20b, or the second memory that has been turned on. By connecting the memory transistor 19b to the second storage node SNB via the second switch transistor 18b and the fourth selection transistor 20d, the same logic as the ethics (Low level or High level) of the first memory transistor 19a is maintained as it is. One storage node SNT can be written, and the same logic as the ethics of the second memory transistor 19b can be written to the second storage node SNB. Thereby, in the nonvolatile SRAM memory cell 95, the logic inversion process outside the nonvolatile SRAM memory cell 95 can be made unnecessary, and the logic inversion process can be executed for each nonvolatile SRAM memory cell 95. Therefore, in the non-volatile SRAM memory cell 95, the program operation from the SRAM 15 to the non-volatile memory unit 16 and the memory data writing operation from the non-volatile memory unit 16 to the SRAM 15 can be performed at once on the entire memory mat, so that the processing time is greatly reduced. be able to.

  Incidentally, also in the above-described embodiment, since the potential of the first storage node SNT and the second storage node SNB is 0 [V] or the power supply voltage VDD during the program operation in the nonvolatile memory unit 16, the switch mechanism 88 is provided. The gate voltage required for the on / off operation of the first selection transistor 20a, the second selection transistor 20b, the third selection transistor 20c, and the fourth selection transistor 20d to be configured only needs to be equal to or lower than the power supply voltage VDD. Since a voltage higher than the power supply voltage VDD is not required for operation, the gate insulating films of the first selection transistor 20a, the second selection transistor 20b, the third selection transistor 20c, and the fourth selection transistor 20d are also 4 [nm] or less. Can be formed.

  In the embodiment described above, as shown in FIG. 3, the first switch transistor 18a, the first memory transistor 19a, the second switch transistor 18b, and the second memory transistor 19b constituting the nonvolatile memory unit 16 are P P-type second semiconductor formed in the second conductivity type second semiconductor region ER2 and having the same first access transistor 21a, second access transistor 21b, first drive transistor 23a, and second drive transistor 23b constituting the SRAM 15. Although the case where it is formed in the region ER2 has been described, the present invention is not limited to this, and the first switch transistor 18a, the first memory transistor 19a, the second switch transistor 18b, and the second memory transistor 19b constituting the nonvolatile memory unit 16 However, it may be formed in the N-type conductive first semiconductor region ER1. In that case, since the nonvolatile memory portion can be formed in the same first semiconductor region ER1 as the first load transistor and the second load transistor of the SRAM, the area of the nonvolatile SRAM memory cell can be reduced accordingly.

1,61 Nonvolatile semiconductor memory device
2,55a, 85,95 Nonvolatile SRAM memory cell
4 Data inversion circuit
5 Bit line control circuit
8 SRAM power control circuit
11 Nonvolatile memory control circuit
15 SRAM
16 Nonvolatile memory section
17a First memory cell
17b, 65,68,70 Second memory cell
18a, 87a 1st switch transistor
18b, 87b Second switch transistor
19a First memory transistor
19b Second memory transistor
BLT0, BLT1, BLT2, BLT3 Complementary first bit line
BLB0, BLB1, BLB2, BLB3 Complementary second bit line
21a 1st access transistor
21b Second access transistor
22a First load transistor
22b Second load transistor
23a 1st drive transistor
23b Second drive transistor
90 Switch mechanism
FGa, FGb Floating gate (charge storage region)
VSp0, VSp1, VSp2, VSp3 power line
VSn0, VSn1, VSn2, VSn3 reference voltage line

Claims (15)

Having a first storage node between one first load transistor and first drive transistor connected at one end, and having a second storage node between the other second load transistor and second drive transistor connected at one end An SRAM (Static Random Access) in which the other ends of the first load transistor and the second load transistor are connected to a power supply line, and the other ends of the first drive transistor and the second drive transistor are connected to a reference voltage line. Memory)
A first memory cell to which a voltage can be applied from either the first storage node or the second storage node to one end of a first switch transistor connected in series with the first memory transistor, and a second memory transistor in series A non-volatile SRAM having a non-volatile memory section having a second memory cell to which a voltage can be applied from the remaining second storage node or the other of the first storage nodes at one end of the connected second switch transistor A memory cell,
The SRAM is
One end is connected to the gates of the other second load transistor and the second drive transistor and one first storage node, the other end is connected to the complementary first bit line, and the gate is a word A first access transistor connected to the line;
One end is connected to the gate of one of the first load transistor and the first drive transistor and the other second storage node, the other end is connected to a complementary second bit line, and the gate is A second access transistor connected to the word line,
The film thickness of each gate insulating film of the first access transistor, the second access transistor, the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor is 4 [nm] or less. A non-volatile semiconductor memory device characterized in that the non-volatile semiconductor memory device is formed. Due to a difference in voltage between the first storage node and the second storage node, only one of the first switch transistor and the second switch transistor is turned on, and the first switch transistor and the second switch transistor are turned on. 2. The nonvolatile semiconductor memory device according to claim 1, wherein writing data into the first memory transistor or the second memory transistor and blocking data writing are determined by an on / off operation. 3. The nonvolatile semiconductor according to claim 1, wherein a film thickness of each gate insulating film of the first switch transistor and the second switch transistor in the nonvolatile memory unit is 4 nm or less. Storage device. The first storage node is connected to one end of the first switch transistor, and the voltage of the first storage node is applied,
4. The device according to claim 1, wherein the second storage node is connected to one end of the second switch transistor, and a voltage of the second storage node is applied. 5. Nonvolatile semiconductor memory device. A first read transistor having one end connected to the first storage node and the other end connected to the first memory transistor;
A second read transistor having one end connected to the second storage node and the other end connected to the second memory transistor;
The second storage node is connected to one end of the first switch transistor, and the voltage of the second storage node is applied,
4. The device according to claim 1, wherein the first storage node is connected to one end of the second switch transistor, and a voltage of the first storage node is applied. 5. Nonvolatile semiconductor memory device. A switch mechanism connected to the SRAM and the nonvolatile memory unit;
The switch mechanism is
Only one of the first storage node or the second storage node is selectively connected to the first switch transistor, and only the other of the remaining second storage node or the first storage node, The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is selectively connected to the second switch transistor. The nonvolatile SRAM memory cell is
The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the nonvolatile memory units are connected in parallel to one SRAM. A first semiconductor region in which the first load transistor and the second load transistor constituting the SRAM are formed;
The first access transistor, the second access transistor, the first drive transistor, and the second semiconductor region in which the second drive transistor is formed.
The first switch transistor, the first memory transistor, the second switch transistor, and the second memory transistor that form the nonvolatile memory unit are formed in either the first semiconductor region or the second semiconductor region. 8. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device. The nonvolatile memory unit is
A first gate line is connected to the gate of the first switch transistor, and a second gate line different from the first gate line is connected to the second switch transistor, and the first switch transistor and the first switch transistor 9. The nonvolatile semiconductor memory device according to claim 1, wherein the second switch transistor is independently turned on / off. After detecting the voltage of the first storage node and / or the second storage node via the complementary first bit line and the complementary second bit line, one of the first voltages to which a high level voltage is applied Apply a logically inverted low level voltage to one storage node or the second storage node, and logically invert the other second storage node or the first storage node to which another low level voltage is applied A data inversion circuit that applies a high level voltage is provided.
The SRAM is
When writing SRAM data from the first storage node and the second storage node to the nonvolatile memory unit, the Low level and High level voltages logically inverted based on the data inverting circuit are applied to the nonvolatile memory unit. 4. The nonvolatile semiconductor memory device according to claim 1, wherein charge is injected into a charge storage region of either the first memory transistor or the second memory transistor. After detecting the voltage of the first storage node and / or the second storage node via the complementary first bit line and the complementary second bit line, one of the first voltages to which a high level voltage is applied Apply a logically inverted low level voltage to one storage node or the second storage node, and logically invert the other second storage node or the first storage node to which another low level voltage is applied A data inversion circuit that applies a high level voltage is provided.
The SRAM is
When writing the memory data held in the nonvolatile memory unit to the SRAM, based on the presence or absence of charge injection in the charge storage region of the first memory transistor and the second memory transistor in the nonvolatile memory unit, the low level The high level voltage and the low level voltage logically inverted by the data inversion circuit after the high level voltage is applied to the first storage node and the second storage node, The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied to the second storage node. An SRAM power supply control circuit for applying a power supply voltage to the power supply line;
The SRAM power control circuit
9. When writing memory data of the non-volatile memory section into the SRAM, the voltage application to the power supply line is stopped, and the first load transistor and the second load transistor are turned off. The nonvolatile semiconductor memory device according to any one of the above. A bit line control circuit for supplying a reference current to either the complementary first bit line or the complementary second bit line;
When the reference current is supplied to the first storage node, the first switch transistor is turned on, a measurement voltage of a predetermined voltage is applied to the gate of the first memory transistor, and the reference current is applied to the second storage node. A non-volatile memory unit control circuit that, when supplied to the node, turns on the second switch transistor and applies a predetermined measurement voltage to the gate of the second memory transistor;
The first storage node and the second storage node are:
When a memory current flowing through the first memory transistor or the second memory transistor by the measurement voltage is smaller than the reference current, the memory current is latched to a low level voltage, and the memory current is larger than the reference current. 10. The nonvolatile semiconductor memory device according to claim 9, wherein when it is large, the reference current is latched to a high level voltage. The nonvolatile SRAM memory cells are arranged in a matrix;
The predetermined voltage is collectively applied to the memory gate lines or the memory source lines connected to the plurality of nonvolatile SRAM memory cells in each direction. The nonvolatile semiconductor memory device described. The nonvolatile SRAM memory cell is
Among the plurality of nonvolatile memory units, when SRAM data is written from one SRAM to the other nonvolatile memory unit, while turning off the first switch transistor and the second switch transistor in the other nonvolatile memory unit, The charge accumulated in the charge accumulation region of either the first memory transistor or the second memory transistor of another nonvolatile memory unit associated with the one nonvolatile memory unit to which the SRAM data is written is extracted. 8. The nonvolatile semiconductor memory device according to claim 7.

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