KR101459506B1 - Multi-Time Programmable memory device - Google Patents

Abstract

The present invention relates to an MIP memory device. More particularly, the present invention relates to an MIP memory device which prevents the breakage of well bonding even in a high voltage. An MIP memory device according to an embodiment of the present invention includes an MTP memory cell. According to an embodiment of the present invention, the MIP memory device includes a control gate MOS capacitor (MC1); a tunnel gate_sense transistor (MN1); and a select transistor (NM2). According to an embodiment of the present invention, the control gate MOS capacitor (MC1) functions as a coupling capacitor.

Description

MTP memory device {Multi-Time Programmable memory device}

The present invention relates to an MTP memory device, and more particularly, to an MTP memory device in which the size of an MTP memory cell (Multi-Time Programmable Memory) is reduced while the number of MOS devices used is reduced without deteriorating the characteristics.

PMIC (Power Management IC) is a chip that receives input power from information equipment such as mobile phone, notebook PC, TV and monitor, and converts it into stable and efficient power required by the system. The PMIC chip provides a soft start time for sequencing power-on and power-down of individual transducers, setting the output voltage, setting the output pull-down resistor, setting the inductor current limit, protecting the circuit against inrush current, In order to perform the setting function, a non-volatile memory (NVM) memory IP is required.

The NVM cell used for the PMIC chip is a single-poly EEPROM (MEP) memory cell with a bit cell size of several tens of microns in case of less than several Kb, and one or two mask layers are added do. MTP memory is used in many PMIC chips because of its simplicity and cost competitiveness.

A conventional MTP memory cell is composed of a capacitor, a sense transistor, and a select transistor. The sense transistor and the select transistor have a problem that the well junction is broken when an excessive voltage is applied to the transistors in each well process.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which shares a dip-and-well region DNW of a control gate capacitor MC1, a tunnel gate capacitor MC2, a sense transistor MN1 and a select transistor MN2 of an MTP memory, The transistor MN1 and the select transistor MN2 share the P-type well region PW so as to reduce the size of the MTP memory cell (Multi-Time Programmable Memory) without deteriorating the normal characteristics, and the MTP And a memory device.

The MTP memory cell of the MTP memory device according to the present invention is formed in a first P-type well region (PW), a control gate driving circuit (CG Driver) is connected to the first terminal and the second terminal, 3 terminal is formed in the second P-type well region PW, the control gate MOS capacitor MC1 connected to the floating gate FG, the tunnel gate TG is connected to the second terminal, and the third terminal is connected to the floating gate FG The bit line BL is connected to the first terminal of the tunneling gate sense transistor MN1 and the second terminal of the tunneling gate sense transistor MN1 is formed in the second gate region of the tunneling gate sense transistor MN1. Sense transistor MN1 and the select transistor MN2 are connected to the second P-type well region PW (PW), and the third terminal is connected to the word line WL. ), And between the first P-type well region PW and the second P-type well region PW, Region (DNW) and N hyeongwel (NW) is located inside, N hyeongwel (NW) located therein is characterized in that spaced apart from the 1 P hyeongwel region (PW) or claim 2 P hyeongwel region (PW).

The memory cells of the MTP memory device according to the present invention suitably share the wells of the components so that the wells are not destroyed at transient voltages. In addition, the structure of the shared well can reduce the number of MOS devices used in the memory cell, thereby reducing the overall chip size.

1 is an embodiment of a memory cell circuit diagram of an MTP memory device according to the present invention.
Figure 2 is a cross-sectional view of a memory cell process of an MTP memory device according to the present invention.
3 is an embodiment of a 32 row X 16 column MTP memory cell array circuit of an MTP memory device according to the present invention.
4. FIG. 4 illustrates an example of a bias voltage condition in the erase mode of the MTP memory device according to the present invention.
5 illustrates an example of a bias voltage condition in the program mode of the MTP memory device according to the present invention.
6. FIG. 6 illustrates an example of a bias voltage condition in a read mode of the MTP memory device according to the present invention.
7 is an embodiment of a specification of an MTP memory device according to the present invention.
8 is a block diagram of an MTP memory device according to an embodiment of the present invention.
9. FIG. 9 is a timing chart for the erase mode of the MTP memory device according to the present invention.
10 is a timing diagram for a program mode of the MTP memory device according to the present invention.
11 is a timing diagram for a read mode of the MTP memory device according to the present invention.
12 is a timing diagram for a reset mode of the MTP memory device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is an embodiment of a memory cell circuit diagram of an MTP memory device according to the present invention.

Figure 2 is a cross-sectional view of a memory cell process of an MTP memory device according to the present invention.

1 and 2, MTP memory cells 100 and 200 are formed in a first P-type well region 250, a control gate driving circuit (CG Driver) is connected to a first terminal and a second terminal, The terminal is formed in the control gate MOS capacitor MC1 210 connected to the floating gate FG and the second P type well region 270. The tunnel gate TG is connected to the second terminal and the third terminal is connected to the floating gate Sense transistor MN1 220 and the second P-type well region 270 connected to the bit line BL and the bit line BL are connected to the first terminal and the second terminal is connected to the tunnel gate sense transistor MN1 and 220 and the third terminal is composed of select transistors MN2 and 230 connected to a word line WL.

The tunnel gate sense transistors MN1 and 220 and the select transistors MN2 and 230 share the second P-type well region 270.

The dip-well region DNW 240 is located between the first P-type well region 250 and the second P-type well region 270 and the N-type well NW 260 is located within the deep-n-well region DNW 240 , N-type wells (NW) 260 located inside the first P-type well region 250 or the second P-type well region 270 are separated from each other.

The control gate MOS capacitors MC1 and 210, the tunnel gate sense transistors MN1 and 220, and the select gate transistors MN2 and 230 share the dipper well regions DNW and 240, respectively.

The tunnel gate sense transistors MN1 and 220 emit electrons of the floating gate FG or inject electrons into the floating gate FG by the FN tunneling method.

The Fowler-Nordheim tunneling (FN) tunneling scheme is a quantum tunneling effect in which data can be electrically rewritten using FN tunneling.

The control gate MOS capacitors MC1 and 210 serve as coupling capacitors.

The select transistors MN2 and 230, when erased, reduce the off-leakage current in the bit line BL.

To reduce the size of the MTP memory cells 100 and 200, a Deep N-Well region of the 512b cell array is shared, and the number of MOS devices used is three.

The P-type wells 250 and 270 of the tunnel gate sense transistor and the select transistor are shared. The tunnel gate sense transistor serves as a tunnel gate transistor for tunneling in an erase mode and a program mode, and as a sense transistor in a read mode. Meanwhile, the proposed MTP memory cells 100 and 200 use an FN tunneling scheme for low power consumption in a write mode.

In an embodiment of the MTP (Multi-Time Programmable) memory device according to the present invention, the cell size of the MTP laid out using the general CMOS 0.18 탆 process is 9.465 탆 X 4.28 탆 (= 40.51 탆 2).

In the present invention, the P-type well 250 (250, 270) is formed in order to increase the breakdown voltage of the well junction between the P-type well 250 and 270 in the deep N-well region and the N- Type well 260 and the N-type well 260 without leaving an additional mask, the space between the P-type well 250 and the N-type well 260 is maintained at a predetermined interval, ).

The first P-type well 250 and the N-type well 260 and the second P-type well 270 and the N-type well 260 are spaced apart from each other by a predetermined distance have.

3 is an embodiment of a 32 row X 16 column MTP memory cell array circuit of an MTP memory device according to the present invention.

The power supply (VDD, = 1.8V, 10%) uses a single power supply, and the operation modes support the erase mode, the program mode, the read mode, and the reset mode. The write time of the MTP memory cell is 5 ms and the access time is 200 ns.

4. FIG. 4 illustrates an example of a bias voltage condition in the erase mode of the MTP memory device according to the present invention.

In the erase mode, -8V and + 8V are applied to the control gate (CG) and the tunnel gate (TG) of the selected cell to emit electrons of the floating gate by the FN tunneling method.

5 illustrates an example of a bias voltage condition in the program mode of the MTP memory device according to the present invention.

In the program mode, +8 V and -8 V are applied to the control gate (CG) and the tunnel gate (TG) of the selected cell, respectively, and electrons are injected into the floating gate by the same FN tunneling method as the erase.

6. FIG. 6 illustrates an example of a bias voltage condition in a read mode of the MTP memory device according to the present invention.

The erased cell in the read mode outputs 0V on the bit line while the programmed cell is boosted by the power supply (VDD) -threshold voltage (V _T ) due to the loss of the threshold voltage (V _T ) of the NMOS transistor of the bit line switch (pull-up).

7 is an embodiment of a specification of an MTP memory device according to the present invention.

8 is a block diagram of an MTP memory device according to an embodiment of the present invention.

The MTP memory device according to the present invention includes a control logic for generating a control signal according to an operation mode, a control for outputting a word line WL and a control gate (CG) signal in response to a control logic signal, A gate drive circuit CG Driver, a tunnel gate drive circuit (TG Driver) receiving input data and outputting a tunnel gate (TG) signal, and MTP memory cells 100 and 200.

The MTP memory cell array 100, 200 receives the word line WL, control gate CG, and tunnel gate (TG) signals to store data.

A row driver for selecting one of a plurality of rows according to an address and supplying a voltage to a node of a word line WL and a control gate driving circuit CG Driver and the data of an array of MTP memory cells 100 and 200 (VPP, + 4.75V) and the second voltage (VNN) required for the control gate drive circuit (CG Driver) and the tunnel gate drive circuit (TG Driver) , -4.75V), and a third voltage (= second voltage / 2) voltage.

The MTP memory device further includes a bit line switch for transferring the data of the bit line (BL) in the read mode to the data line (DL) of the data output buffer circuit.

The block diagram of the designed 512b MTP includes 32 rows X M columns of memory cells 100, 200 arrays, control logic for generating control signals in accordance with the mode of operation, 32 rows according to address [4: 0] A row driver for supplying a voltage to a word line, a control gate (CG) node by selecting one of the data lines (data) to be input to the data output (DOUT) buffer in a read mode, a bit line switch for transferring data to a line, a data output (DOUT) buffer for reading a data line (read data), a tunnel gate (TG) driver, and a high voltage And a DC-DC converter circuit for supplying a first voltage (VPP, = + 8V), a second voltage (VNN, = -8V), and a third voltage (VNNL, = VNN / 2). The interface signals include control signals RSTb, READ, ERS and PGM, addresses [4: 0], input data DIN [15: 0] and output data data outputs DOUT [15: 0]. Reading and writing are done word by word.

The MTP memory cells 100 and 200 according to the present invention must first perform an erase operation before programming.

9. FIG. 9 is a timing chart for the erase mode of the MTP memory device according to the present invention.

9 shows an example of the erase timing of the selected word cell when the erase signal ERS is applied to the power supply VDD after the address a [4: 0] to be erased is first applied in an erase timing diagram, t _ERS ) and then to the destruction time (t _exer ). At this time, the read signal READ and the program signal PGM are not applied, and the power source VDD is applied to the reset inversion signal RSTb. The erase time t _ERS is 5 ms considering the settling time of the DC-DC converter.

10 is a timing diagram for a program mode of the MTP memory device according to the present invention.

When the program signal PGM is applied to the power supply VDD while the address a [4: 0] and the input data are first applied in the program timing diagram, the input data DIN [ 15: 0].

At this time, the read signal READ and the erase signal ERS are not applied, and the power supply VDD is applied to the reset inversion signal RSTb.

11 is a timing diagram for a read mode of the MTP memory device according to the present invention.

A read operation is to read address (a [4: 0]) the first when the applied and then a read signal (READ) is applied to the power supply (VDD) the word data of the selected cell is an access time period amplification conversion time (t _AC) is Outputs to the data output (DOUT) [15: 0] port after the last.

12 is a timing diagram for a reset mode of the MTP memory device according to the present invention.

The reset mode circuitatically turns off the DC-to-DC converter circuit and puts the MTP memory in a stand-by state.

At this time, the erase signal ERS and the program signal PGM are not applied, and the power source VDD is applied to the reset inversion signal RSTb.

In an embodiment of the MTP memory device according to the present invention, in order to ensure 10,000 write cycles and 10 years of data integrity in a 0.18 mu m general CMOS process, the maximum voltage applied to the device is limited to 8.5 V or less have.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

100, 200: MTP memory cell 110, 210: control gate MOS capacitor
120, 220: Tunnel gate sense transistor
130, 230: select transistor

Claims (7)

1. An MTP memory device comprising an MTP memory cell,
The MTP memory cell
A control gate MOS capacitor MC1 formed in the first P-type well region PW and having a first terminal and a second terminal connected to a control gate driving circuit CG Driver and a third terminal connected to the floating gate FG;
A tunnel gate sense transistor MN1 formed in the second P-type well region PW and having a second terminal connected to the tunnel gate TG and a third terminal connected to the floating gate FG; And
A bit line BL is connected to the first terminal, a second terminal is connected to the first terminal of the tunnel gate sense transistor MN1, and a third terminal is formed in the second P type well region PW, And a select transistor MN2 to which a line WL is connected,
The tunnel gate sense transistor MN1 and the select transistor MN2 share the second P-type well region PW,
A deep-n-well region DNW is located between the first P-type well region PW and the second P-type well region PW, an N-type well NW is located inside the deep-n-well region DNW, Wherein the N-type well (NW) located at the first P-type well region (PW) is spaced from the first P-type well region (PW) or the second P- 2. The semiconductor memory device according to claim 1, wherein the tunnel gate sense transistor MN1
Wherein the floating gate (FG) emits electrons by the FN tunneling method or injects electrons into the floating gate (FG) 2. The semiconductor memory device according to claim 1, wherein the control gate MOS capacitor (MC1)
MTP memory device characterized by acting as a coupling capacitor The semiconductor memory device according to claim 1, wherein the select transistor (MN2)
Leakage current in the bit line (BL) when the memory cell is over-erased. The method according to claim 1,
(DNW) of the control gate MOS capacitor (MC1), the tunnel gate sense transistor (MN1) and the select transistor (MN2). 2. The apparatus of claim 1, wherein the MTP memory device
Control logic for generating a control signal according to the operation mode;
A control gate driving circuit (CG Driver) for receiving a signal of the control logic and outputting a word line (WL) and a control gate (CG) signal;
A tunnel gate driving circuit (TG Driver) receiving input data and outputting a tunnel gate (TG) signal;
An MTP memory cell array including the MTP memory cell and storing data by receiving the word line (WL), the control gate (CG), and the tunnel gate (TG) signal;
A row driver (30) for selecting one of a plurality of rows according to an address to supply a voltage to a node of the word line (WL) and a node of the control gate drive circuit (CG Driver);
A data output buffer circuit for latching data of the MTP memory cell array and outputting the latched data to a data output port; And
(VPP, + 4.75V), the second voltage (VNN, -4.75V), and the third voltage (= 0V) required for the control gate drive circuit (CG Driver) and the tunnel gate drive circuit DC converter 70 for supplying a first voltage / second voltage to the MTP memory device 70. The MTP memory device 70 further includes a DC / 2. The apparatus of claim 1, wherein the MTP memory device
And a bit line switch (40) for transferring data of the bit line (BL) to a data line (DL) of a data output buffer circuit in a read mode.

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