WO2024055484A1 - Programmable storage array, programming method and semiconductor memory - Google Patents

Abstract

The embodiments of the present disclosure provide a programmable storage array, a programming method and a semiconductor memory. The programmable storage array comprises a plurality of storage units. Each storage unit comprises a first transistor and a second transistor, which are connected in series, wherein a first end of the first transistor is connected to a bit line, a gate end of the first transistor is connected to a programming line, and a second end of the first transistor is connected to a first end of the second transistor; and a gate end of the second transistor is connected to a word line, and a second end of the second transistor is connected to a first preset power supply. When the storage unit is programmed, the second transistor is controlled to be in a connected state, and the voltage difference between the gate end of the first transistor and the first end of the first transistor is controlled to be greater than 0; and when the storage unit is restored, the second transistor is controlled to be in a connected state, and the voltage difference between a gate of the first transistor and the first end of the first transistor is controlled to be smaller than 0.

Description

Programmable storage array, programming method and semiconductor memory

Cross-references to related applications

This disclosure is based on a Chinese patent application with the application number 202211129986.3, the filing date being September 16, 2022, and the invention title being "A programmable storage array, programming method and semiconductor memory", and claims the priority of this Chinese patent application , the entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of integrated circuit technology, and in particular, to a programmable memory array, a programming method and a semiconductor memory.

Background technique

With the continuous development of integrated circuit technology, fuse memory cells are widely used in integrated circuits for repair work. Among them, the gate oxide fuse memory unit is a typical representative. Its most classic structure is a fuse circuit composed of a control gate + a fuse gate, which is realized by controlling whether the gate oxide of the fuse gate breaks down or not. programming effects.

The gate oxide fuse memory cell may include a fuse transistor and a pass transistor. When a high voltage is applied to the fuse gate of the fuse transistor, the gate oxide layer of the fuse transistor is destroyed due to the voltage difference between the high voltage fuse gate and the low voltage bit line. Specifically, a voltage sufficient to form a conductive channel is applied to the control gate of the pass transistor to transmit the fuse gate voltage; then, by controlling the voltage difference between the fuse gate and the bit line to breakdown the gate oxide layer, Thus completing a programming operation.

Contents of the invention

The present disclosure provides a programmable memory array, a programming method and a semiconductor memory, which not only do not require breakdown of the gate oxide layer, but also enable multiple programming of memory cells.

In a first aspect, an embodiment of the present disclosure provides a programmable memory array. The programmable memory array includes a plurality of memory cells, and the memory cells include a first transistor and a second transistor connected in series;

The first terminal of the first transistor is connected to the bit line, the gate terminal of the first transistor is connected to the programming line, and the second terminal of the first transistor is connected to the first terminal of the second transistor;

The gate terminal of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the first preset power supply;

Wherein, when programming the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is controlled to be greater than 0;

When restoring the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0.

In some embodiments, multiple memory cells are distributed in an array, where:

A plurality of memory cells are distributed in the extending direction of the bit line, and the plurality of memory cells are connected to the bit line through the first end of the first transistor;

A plurality of memory cells are distributed in the extending direction of the word line, and the plurality of memory cells are connected to the word line through the gate terminal of the second transistor;

A plurality of memory cells are distributed in the extension direction of the programming line, and the plurality of memory cells are connected to the programming line through the gate terminal of the first transistor;

The extension direction of the bit line and the extension direction of the word line are perpendicular to each other, and the extension direction of the programming line and the extension direction of the word line are parallel to each other.

In some embodiments, precharge modules are also distributed in the extension direction of the bit lines, where:

The precharge module is configured to receive a precharge signal, precharge the bit line according to the precharge signal, and precharge the bit line voltage of the bit line to a preset voltage.

In some embodiments, the precharge module includes a third transistor and a fourth transistor, wherein:

A first end of the fourth transistor is connected to a first voltage, a second end of the fourth transistor is connected to a bit line, a gate end of the fourth transistor is used to receive a first precharge signal, and when programming the memory cell, the first precharge signal turns on the fourth transistor to precharge the bit line where the memory cell is located to the first voltage;

The first terminal of the third transistor is connected to the second voltage, the second terminal of the third transistor is connected to the bit line, the gate terminal of the third transistor is used to receive the second precharge signal, and when the memory cell is restored, the second precharge signal is turned on. Pass the third transistor to precharge the bit line where the memory cell is located to the second voltage;

Wherein, the first voltage is lower than the second voltage.

In some embodiments, the first voltage ranges from -0.7 to 0V, and the second voltage ranges from 2.5 to 3V.

In some embodiments, the first voltage is -0.7V and the second voltage is 3V.

In some embodiments, the programmable memory array further includes a first power module and a second power module, the first power module is connected to the programming line, and the second power module is connected to the word line, wherein:

a first power module configured to provide a control voltage for the programming line;

The second power module is configured to provide word line voltage for the word line.

In some embodiments, when programming the memory cell, the control voltage of all programming lines is controlled by the first power module to be a third voltage;

When restoring the memory unit, the first power module controls the control voltage of the programming line where the memory unit is located to be the fourth voltage, and controls the control voltage of other programming lines to be the third voltage;

Wherein, the third voltage is higher than the fourth voltage.

In some embodiments, the third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V.

In some embodiments, the third voltage is 3V and the fourth voltage is 1.5V.

In some embodiments, when the word line is selected, the word line voltage of the word line is controlled by the second power module to be the fifth voltage; or, when the word line is not selected, the word line voltage is controlled by the second power module. The word line voltage of the word line is the sixth voltage;

Wherein, the fifth voltage is lower than the sixth voltage.

In some embodiments, when the word line is selected, if the fifth voltage is lower than the power supply voltage of the first preset power supply, it is determined that the second transistor is in the on state; or, when the word line is not selected, , if the sixth voltage is greater than or equal to the power supply voltage of the first preset power supply, it is determined that the second transistor is in the off state.

In some embodiments, the fifth voltage is 0V and the sixth voltage is 3V.

In some embodiments, the programmable memory array further includes a readout circuit, and the bit lines are respectively connected to the readout circuit through different fifth transistors, wherein:

The first terminal of the fifth transistor is connected to the bit line, the second terminal of the fifth transistor is connected to the readout circuit, the gate terminal of the fifth transistor receives the column selection signal, and the fifth transistor transmits the signal corresponding to the bit line according to the column selection signal. to the readout circuit.

In some embodiments, the readout circuit includes a read resistor and a comparator, where:

The first input terminal of the comparator and the first terminal of the reading resistor are both connected to the second terminal of the fifth transistor. The second terminal of the reading resistor is connected to ground. The second input terminal of the comparator is used to receive the reference voltage. The comparator The output terminal is used to read out the data stored in the target memory unit, where the target memory unit is determined based on the column selection signal and the word line.

In some embodiments, the first transistor is a PMOS transistor, and the second transistor is a PMOS transistor.

In a second aspect, embodiments of the present disclosure provide a programming method applied to a programmable memory array including a plurality of memory cells. The memory unit includes a first transistor and a second transistor, and a first end of the first transistor is connected to a bit line. connection, the gate terminal of the first transistor is connected to the programming line, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate terminal of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the A default power connection; the method includes:

When programming the memory cell, control the second transistor to be in a conductive state, and control the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor to be greater than 0;

When restoring the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0.

In some embodiments, the method further includes:

When programming the memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is greater than 0;

When restoring the memory cell, the control voltage of the programming line is lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is less than 0.

In a third aspect, an embodiment of the present disclosure provides a semiconductor memory, which includes the programmable memory array as described in the first aspect.

Embodiments of the present disclosure provide a programmable storage array, a programming method and a semiconductor memory. The programmable storage array includes a plurality of storage units, the storage unit includes a first transistor and a second transistor connected in series; a first terminal of the first transistor Connected to the bit line, the gate terminal of the first transistor is connected to the programming line, the second terminal of the first transistor is connected to the first terminal of the second transistor; the gate terminal of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the bit line. The terminal is connected to the first preset power supply; wherein, when programming the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is controlled to be greater than 0; in When restoring the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0. In this way, based on the memory cell composed of the first transistor and the second transistor connected in series, when programming the memory cell, since the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is a forward voltage difference, the third transistor is programmed. The channel leakage current of a transistor increases, thereby enabling the data stored in the memory unit to change to 1; when the memory unit is restored, because the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is negative The voltage difference reduces the channel leakage current of the first transistor, thereby enabling the data stored in the memory cell to change to 0; in this way, the memory cell can be reprogrammed multiple times, and since there is no need to breakdown the gate oxide layer, This also avoids the use of excessive voltage stress, can improve the overshoot damage of high voltage to memory cells, and ultimately improves the performance of the memory.

Description of drawings

Figure 1 is a schematic diagram of the composition and structure of a gate oxide fuse memory unit;

Figure 2 is a schematic structural diagram of a programmable memory array provided by an embodiment of the present disclosure;

Figure 3 is a schematic diagram 2 of the composition of a programmable memory array provided by an embodiment of the present disclosure;

Figure 4 is a schematic diagram 3 of the composition of a programmable memory array provided by an embodiment of the present disclosure;

Figure 5 is a schematic diagram of the change between gate voltage and channel leakage current provided by an embodiment of the present disclosure;

Figure 6 is a schematic diagram 4 of the composition of a programmable memory array provided by an embodiment of the present disclosure;

Figure 7 is a schematic flow chart of a programming method provided by an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described here are only used to explain the relevant application, but not to limit the application. It should also be noted that, for convenience of description, only parts relevant to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be noted that the terms "first\second\third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first\second\third" Where permitted, the specific order or sequence may be interchanged so that the embodiments of the disclosure described herein can be practiced in an order other than that illustrated or described herein.

It should also be pointed out that the high level and low level used in the signals involved in the embodiments of the present disclosure refer to the logic level of the signal. There is a difference between a signal having a high level and a signal having a low level. For example, a high level may correspond to a signal having a first voltage, and a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is higher than the second voltage. Furthermore, the logic levels of signals may be different or opposite to those described. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level .

Referring to Figure 1, a schematic structural diagram of a gate oxide fuse memory cell is shown. As shown in FIG. 1 , a gate oxide fuse memory cell may include a substrate 101 and a fuse transistor 102 and a pass transistor 103 located above the substrate 101 . Among them, a deep N-well region 104 is formed in the substrate 101, and a P-well region 105 is formed in the deep N-well region 104. The P-well region 105 is provided with a first doping region 106, a second doping region 107 and The third doped region 108. The fuse transistor 102, also called a programming transistor, is disposed above the substrate between the first doped region 106 and the second doped region 107; and the transfer transistor 103, also called a selection transistor, is disposed above the second doped region. above the substrate between the region 107 and the third doped region 108.

In FIG. 1 , the fuse gate of the fuse transistor 102 is used to receive the word line voltage Wlp, and the control gate of the transfer transistor 103 is used to receive the word line voltage Wlr. The first doped region 106, the second doped region 107 and the third doped region 108 may all be N+ doped regions, which may be used to form a source electrode or a drain electrode.

In this way, as shown in Figure 1, two separate gates (fuse gate + control gate) together form a fuse path, and the programming effect is achieved by controlling the gate oxygen breakdown of the fuse gate. Specifically, by controlling the voltage difference between the fuse gate and the bit line to break down the gate oxide layer, a One-Time Programmable (OTP) operation can be completed. However, if the gate oxide fuse memory cell once completes OTP programming, the gate oxide layer of the fuse gate will become a permanent conductive path, which cannot be subsequently reprogrammed to have a different state.

Based on this, embodiments of the present disclosure provide a programmable memory array. The programmable memory array includes a plurality of memory cells, and the memory cells include a first transistor and a second transistor connected in series. When programming the memory cell, since the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is a forward voltage difference, the channel leakage current of the first transistor increases, thereby enabling storage The data stored in the cell changes to 1; when the memory cell is restored, since the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is a negative voltage difference, the channel leakage current of the first transistor decreases. Small, so that the data stored in the memory cell can be converted to 0; in this way, the memory cell can be reprogrammed multiple times, and because there is no need to breakdown the gate oxide layer, it also avoids the use of excessive voltage stress and can improve high voltage Overshoot damage to memory cells ultimately improves memory performance.

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, see FIG. 2 , which shows a schematic structural diagram of a programmable memory array provided by an embodiment of the present disclosure. As shown in FIG. 2 , the programmable memory array 20 may include multiple memory cells (specifically, memory unit A, memory unit B, memory unit C, and memory unit D).

Taking one of the memory cells as an example, the memory cell includes a first transistor P1 and a second transistor P2 connected in series; the first terminal of the first transistor P1 is connected to the bit line, the gate terminal of the first transistor P1 is connected to the programming line, and the first transistor P1 is connected to the bit line. The second terminal of a transistor P1 is connected to the first terminal of the second transistor P2; the gate terminal of the second transistor P2 is connected to the word line, and the second terminal of the second transistor P2 is connected to the first preset power supply.

It should be noted that when programming the memory cell, the second transistor P2 is controlled to be in a conductive state, and the voltage difference between the gate terminal of the first transistor P1 and the first terminal of the first transistor P1 is controlled to be greater than 0. In this way, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a forward voltage difference, based on the hot electron induced breakdown effect (Hot Electron Induced Punchthrough, HEIP) of the first transistor P1, the first transistor P1 experiences HEIP degradation characteristics under forward voltage stress, causing the channel leakage current of the first transistor P1 to increase, thereby enabling the transition of data stored in the memory cell from "0" to "1".

It should also be noted that when restoring the memory cell, the second transistor P2 is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor P1 and the first terminal of the first transistor P1 is controlled to be less than 0. In this way, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a negative voltage difference, the first transistor P1 experiences HEIP recovery characteristics under negative voltage stress, causing the channel leakage of the first transistor P1 The current decreases, thereby enabling the transition of the data stored in the memory cell from "1" to "0".

In some embodiments, multiple memory cells may be distributed in an array, where:

Several memory cells are distributed in the extending direction of the bit line, and the plurality of memory cells are connected to the bit line through the first end of the first transistor P1;

Several memory cells are distributed in the extending direction of the word line, and the plurality of memory cells are connected to the word line through the gate terminal of the second transistor P2;

Several memory cells are distributed in the extending direction of the programming line, and the plurality of memory cells are connected to the programming line through the gate terminal of the first transistor P1.

It should be noted that, in the embodiment of the present disclosure, the extension direction of the bit line and the extension direction of the word line are perpendicular to each other, and the extension direction of the programming line and the extension direction of the word line are parallel to each other.

It should also be noted that in the embodiment of the present disclosure, the number of bit lines may be at least one, the number of word lines may be at least one, and the number of programming lines may be at least one. See Figure 2 for details. For four memory cells, the number of bit lines is two, which can be represented by BL1 and BL2; the number of word lines is two, which can be represented by WL1 and WL2; the number of programming lines is two , can be represented by WL1', WL2'; the first preset power supply can be represented by VDD1.

For example, as shown in FIG. 2 , memory unit A, memory unit B, memory unit C, and memory unit D are distributed in a 2×2 array. Wherein, the first terminal of the first transistor P1 in the memory unit A and the first terminal of the first transistor P1 in the memory unit B are both connected to the bit line BL1, and the first terminal of the first transistor P1 in the memory unit C is connected to the first terminal of the first transistor P1 in the memory unit D. The first terminal of the first transistor P1 in the memory unit A is connected to the bit line BL2; the gate terminal of the first transistor P1 in the memory unit A and the gate terminal of the first transistor P1 in the memory unit C are both connected to the programming line WL1', and the memory unit B The gate terminal of the first transistor P1 in the memory unit D and the gate terminal of the first transistor P1 in the memory unit D are both connected to the programming line WL2'; the second terminal of the first transistor P1 in the memory unit A is connected to the first terminal of the second transistor P2 in the memory unit A. terminals are connected, the second terminal of the first transistor P1 in the memory unit B is connected to the first terminal of the second transistor P2 in the memory unit C, and the second terminal of the first transistor P1 in the memory unit C is connected to the first terminal of the second transistor P2 in the memory unit C. The second terminal of the first transistor P1 in the memory unit D is connected to the first terminal of the second transistor P2 in the memory unit D; the gate terminal of the second transistor P2 in the memory unit A and the gate terminal of the second transistor P2 in the memory unit C Both terminals are connected to the word line WL1, the gate terminal of the second transistor P2 in the memory unit B and the gate terminal of the second transistor P2 in the memory unit D are both connected to the word line WL2; the second terminal of the second transistor P2 in the memory unit A , the second terminal of the second transistor P2 in the memory unit B, the second terminal of the second transistor P2 in the memory unit C, and the second terminal of the second transistor P2 in the memory unit D are all connected to the first preset power supply VDD1. Here, the first preset power supply VDD1 may be 3.0V.

In some embodiments, both the first transistor and the transistor may be a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), that is, a P-type MOSFET, which may be referred to as a PMOSFET or a PMOS transistor. That is to say, the first transistor is a PMOS transistor, and the second transistor is a PMOS transistor, that is, each memory cell is composed of two PMOS transistors connected in series. In this way, based on the decay and recovery characteristics of the PMOS tube HEIP, multiple-time programmable (MTP) of the memory unit can be realized.

It should be noted that in the embodiment of the present disclosure, for the first transistor and the second transistor, the memory unit described here may be composed of two PMOS transistors with thick gate oxide layers connected in series. Among them, the thickness of the thick gate oxide layer is generally greater than or equal to 30 nanometer (nm). Here, the purpose of thick gate oxide is to prevent gate breakdown, while HEIP is the tunneling of the shallow trench isolation (shallow trench isolation, STI) part, which has nothing to do with the gate oxide layer. Therefore, the embodiment of the present disclosure uses a fuse circuit formed by two PMOS tubes connected in series, which no longer needs to penetrate the gate oxide layer to achieve the programming effect, avoids the use of excessive voltage stress, and thus effectively prevents high voltage from damaging the memory cells. Overshoot damage.

It should also be noted that in the embodiment of the present disclosure, for the PMOS transistor, the first terminal may be the source terminal, and the second terminal may be the drain terminal. In this way, based on the HEIP degradation and recovery characteristics under voltage stress between the gate terminal and the source terminal of the first transistor P1, MTP programming can be performed and overshoot damage to the memory cell caused by using excessive voltage can be avoided.

It can be understood that on the basis of the programmable memory array 20 shown in Figure 2, in some embodiments, see Figure 3, precharge modules are also distributed in the extension direction of the bit lines, wherein:

The precharge module is configured to receive a precharge signal, precharge the bit line according to the precharge signal, and precharge the bit line voltage of the bit line to a preset voltage.

It should be noted that in the embodiment of the present disclosure, the number of bit lines may be at least one, and accordingly, the number of precharge modules may be at least one. That is, pre-charge modules are evenly distributed in the extension direction of each bit line to pre-charge the bit line where the pre-charge module is located to the corresponding preset voltage. For example, referring to FIG. 3 , precharge modules 201 are distributed in the extension direction of bit line BL1 , and precharge modules 202 are distributed in the extension direction of bit line BL2 .

In some embodiments, for each precharge module, the precharge module may include a third transistor and a fourth transistor, wherein:

The first terminal of the fourth transistor is connected to the first voltage, the second terminal of the fourth transistor is connected to the bit line, the gate terminal of the fourth transistor is used to receive the first precharge signal, and when programming the memory cell, the first precharge signal Turn on the fourth transistor to precharge the bit line where the memory cell is located to the first voltage;

The first terminal of the third transistor is connected to the second voltage, the second terminal of the third transistor is connected to the bit line, the gate terminal of the third transistor is used to receive the second precharge signal, and when the memory cell is restored, the second precharge signal is turned on. By passing the third transistor, the bit line where the memory cell is located is precharged to the second voltage.

In embodiments of the present disclosure, the first voltage is lower than the second voltage.

In the embodiment of the present disclosure, the third transistor may be a P-type MOSFET (PMOS transistor for short), and the fourth transistor may be an N-type MOSFET (NMOS transistor for short).

For example, specifically referring to FIG. 3 , a precharge module 201 is distributed in the extension direction of the bit line BL1. The precharge module 201 may include a third transistor P31 and a fourth transistor N11, where the first precharge signal may be Precharge1 means that the second precharge signal can be represented by CSL1. The first terminal of the fourth transistor N11 is connected to the first voltage V1, the first terminal of the third transistor P31 is connected to the second voltage V2, and the second terminal of the third transistor P31 and The second terminals of the fourth transistor N11 are both connected to the bit line BL1. A precharge module 202 is distributed in the extension direction of the bit line BL2. The precharge module 202 may include a third transistor P32 and a fourth transistor N12. The first precharge signal may be represented by Precharge2, and the second precharge signal may be Expressed as CSL2, the first terminal of the fourth transistor N12 is connected to the first voltage V1, the first terminal of the third transistor P32 is connected to the second voltage V2, and the second terminal of the third transistor P32 and the second terminal of the fourth transistor N12 are both connected. Connected to bit line BL2.

Taking memory cell A as an example, when programming memory cell A, the first precharge signal Precharge1 is set to a high level, controlling the fourth transistor N11 in the precharge module 201 to turn on, thereby precharging the bit line BL1 to a low potential (i.e., the first voltage V1); when restoring memory cell A, the second precharge signal CSL1 is set to a low level, controlling the third transistor P31 in the precharge module 201 to turn on, thereby causing the bit line BL1 Precharge to a high potential (ie, the second voltage V2). In addition, during the process of programming the memory cell A, the second precharge signal CSL2 can also be set to a low level to control the third transistor P32 in the precharge module 202 to turn on, so that the bit line BL2 is precharged to a high potential ( That is, the second voltage V2) to prevent other memory cells (eg, memory cell C and memory cell D) from being programmed.

In some embodiments, the first voltage ranges from -0.7 to 0V, and the second voltage ranges from 2.5 to 3V. In a specific embodiment, the first voltage is -0.7V, and the second voltage is 3V.

That is to say, taking memory cell A as an example, when programming memory cell A, the precharge module 201 controls the bit line BL1 to precharge to a low potential (for example, -0.7V), and the precharge module 202 To control the bit line BL2 to precharge to a high potential (for example, 3V); when restoring memory cell A, the precharge module 201 controls the bit line BL1 to precharge to a high potential (for example, 3V), and through the precharge module 202 Continue to control the bit line BL2 to be precharged to a high potential (for example, 3V).

It can also be understood that based on the programmable memory array 20 shown in Figure 3, in some embodiments, referring to Figure 4, the programmable memory array 20 can also include a first power module 203 and a second power module 204, And the first power module 203 is connected to the programming line, and the second power module 204 is connected to the word line, where:

The first power module 203 is configured to provide a control voltage for the programming line;

The second power module 204 is configured to provide word line voltage for the word line.

It should be noted that in the embodiment of the present disclosure, for the programming lines (WL1', WL2'), the control voltage can be provided through the first power module 203; for the word lines (WL1, WL2), the control voltage can be provided. The word line voltage is provided through the second power module 204 .

It should also be noted that in the embodiment of the present disclosure, when programming a memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the gate terminal of the first transistor P1 and the first transistor P1 The voltage difference between the first terminal of the first transistor P1 is greater than 0; or, when restoring the memory cell, the control voltage of the programming line is controlled to be lower than the bit line voltage of the bit line, so that the gate terminal of the first transistor P1 and the third terminal of the first transistor P1 The voltage difference at one end is less than 0.

In this way, when programming the memory cell, since the voltage difference between the gate terminal of the first transistor P1 and the first terminal of the first transistor P1 is greater than 0, based on the HEIP degradation characteristics of the first transistor P1, the channel of the first transistor P1 will The channel leakage current increases, thereby controlling the data stored in the memory unit to be converted from first data to second data; or, when restoring the memory unit, due to the gap between the gate terminal of the first transistor P1 and the first terminal of the first transistor P1 If the voltage difference is less than 0, then based on the HEIP recovery characteristic of the first transistor P1, the channel leakage current of the first transistor P1 is reduced, thereby controlling the data stored in the memory unit to be converted from the second data to the first data. Here, the first data may be 0 and the second data may be 1.

Further, in some embodiments, when programming the memory cell, the control voltage of all programming lines is controlled by the first power module 203 to be the third voltage;

When restoring the memory cell, the first power module 203 controls the control voltage of the programming line where the memory cell is located to be the fourth voltage, and controls the control voltage of other programming lines to be the third voltage.

In embodiments of the present disclosure, the third voltage is higher than the fourth voltage.

It should be noted that the programmable memory array 20 includes multiple memory cells, and the number of programming lines is at least one. Illustratively, as shown in Figure 4, taking memory unit A as an example, when programming memory unit A, the control voltage of the programming line WL1' can be controlled to the third voltage through the first power module 203, and other programming can be controlled. The control voltage of line WL2' is the third voltage; when restoring memory cell A, the control voltage of programming line WL1' can be controlled to be the fourth voltage through the first power module 203, and the control voltage of other programming lines WL2' is still controlled to be third voltage.

In some embodiments, the third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V. In a specific embodiment, the third voltage is 3V, and the fourth voltage is 1.5V.

That is to say, still taking memory unit A as an example, when programming memory unit A, the control voltage of programming line WL1' can be 3V, and the control voltage of other programming lines WL2' can be 3V; when restoring memory unit A , the control voltage of the programming line WL1' can be 1.5V, and the control voltage of the other programming lines WL2' is still 3V. In this way, compared with the OTP fuse circuit in the related art, the MTP fuse circuit in the embodiment of the present disclosure adds a control end of the programming line WL', which can realize the recovery of HEIP caused by the PMOS tube under the action of negative voltage stress. , thus enabling multiple repeated programming.

Further, in some embodiments, when the word line is selected, the word line voltage of the word line is controlled to be the fifth voltage through the second power module 204; or,

When the word line is not selected, the word line voltage is controlled by the second power module 204 to be the sixth voltage.

In embodiments of the present disclosure, the fifth voltage is lower than the sixth voltage.

It should be noted that the programmable memory array 20 includes multiple memory cells, and the number of word lines is at least one. Illustratively, as shown in FIG. 4 , still taking memory cell A as an example, when word line WL1 is turned on, that is, word line WL1 is selected, the word line voltage of word line WL1 can be controlled through the second power module 204 to be The fifth voltage, and the word line voltage that controls other unselected word lines WL2 is the sixth voltage; in the case that all word lines are not selected, all word lines (for example, WL1 and The word line voltages of WL2) are all the sixth voltage.

Further, in some embodiments, when the word line is selected, if the fifth voltage is lower than the power supply voltage of the first preset power supply, it is determined that the second transistor is in the on state; or,

When the word line is not selected, if the sixth voltage is greater than or equal to the power supply voltage of the first preset power supply, it is determined that the second transistor is in the off state.

It should also be noted that in the programmable memory array 20 , taking word line WL1 as an example, if word line WL1 is selected, that is, when word line WL1 is turned on, the word line voltage of WL1 at this time is lower than the first preset power supply VDD1 power supply voltage, then the second transistor P2 in the corresponding memory cell of word line WL1 is in the on state; otherwise, if word line WL1 is not selected, that is, when word line WL1 is turned off, the word line voltage of WL1 at this time is greater than or equal to the When the power supply voltage of the power supply VDD1 is preset, the second transistor P2 in the memory cell corresponding to the word line WL1 is in an off state.

In some embodiments, the fifth voltage is 0V and the sixth voltage is 3V.

That is to say, still taking memory cell A as an example, memory cell A serves as the target memory cell (Target Cell). When programming memory cell A, the word line WL1 where memory cell A is located is turned on, that is, the word line voltage of WL1 is 0V to control the second transistor P2 in all memory cells on WL1 to be in the on state; when restoring memory cell A, the word line WL1 where memory cell A is located is still in the open state, that is, the word line voltage of WL1 is still on. is 0V to control the second transistor P2 in all memory cells on WL1 to be in a conductive state. For non-target memory cells (Non-Target Cell), memory cell B is a non-target memory cell. Whether memory cell B is programmed or restored, the word line WL2 where memory cell B is located is closed, that is, the word line of WL2 The voltage is 3V to control the second transistor P2 in all memory cells on WL2 to be in an off state.

To put it simply, the embodiment of the present disclosure proposes an MTP fuse circuit design based on the PMOSFET HEIP recovery mechanism, thereby realizing a new fuse programming architecture. In this fuse programming architecture, two series-connected PMOSFETs are used to form a fuse path. Its working principle is divided into two parts: the first part is programming. Based on the test results of actual devices, the first transistor P1 can experience HEIP degradation under the voltage stress conditions of the bit line BL1 = -0.7V and the programming line WL1' = 3V, causing the channel leakage current of the first transistor P1 to increase. Thus achieving the transition from "0" to "1". The second part is recovery. Based on the test results of actual devices, the first transistor P1 can be made to undergo HEIP recovery under the voltage stress conditions of the bit line BL1 = 3V and the programming line WL1' = 1.5V, resulting in a reduction in the channel leakage current of the first transistor P1, thereby reducing the channel leakage current of the first transistor P1. Realize the transition from "1" to "0". It can be seen that the design of this MTP fuse circuit is different from the gate oxide fuse programming mechanism in related technologies, and can support multiple repeated programming; in addition, this MTP fuse circuit does not need to breakdown the gate oxide layer, thus avoiding The use of excessive voltage stress prevents overshoot damage to memory cells caused by high voltage.

Referring to FIG. 5 , it shows a schematic diagram of the change between the gate voltage and the channel leakage current provided by an embodiment of the present disclosure. As shown in Figure 5, the gate voltage can be expressed by Vg, and the unit is Volt (V); the AC leakage current can be expressed by Id, and the unit is Ampere (Ampere, A). In Figure 5, it is assumed that the drain voltage Vd is equal to the source voltage Vs, that is, Vd = Vs = 3V, and the substrate voltage Vb = 0V. At this time, the change curve between the starting current (Id_Fresh) and Vg can be Represented by a solid line, the change curve between the recovery current (Id_recover) and Vg can be represented by a dotted line, and the change curve between the decay current (Id_after stress) and Vg can be represented by a dotted line. For example, the current magnitudes of the source drain current (Ids) and the turn-off current (Ioff) in these three cases are shown in Table 1.

Table 1

​	IDs	Ioff
Fresh	-7.96E-05	-5.81E-12
After stress	-9.23E-05	-1.09E-08
After recover	-7.80E-05	-1.72E-11

That is to say, on the basis of the OTP fuse circuit based on the PMOSFET HEIP decay mechanism, the recovery characteristics of PMOSFET HEIP under the action of negative voltage stress (or "reverse voltage stress") can be used to achieve PMOSFET HEIP recovery. Mechanical MTP fuse circuit design. Specifically, embodiments of the present disclosure provide an MTP fuse memory unit circuit array design based on the PMOSFET HEIP recovery mechanism. Compared with the OTP fuse circuit, this MTP fuse circuit adds a programming line WL' control end, which The function is to realize the reverse voltage stress of PMOSFET, which will lead to the recovery of HEIP, thus enabling multiple repeated programming.

In a specific embodiment, taking Figure 2 as an example, when programming memory cell A, the bit lines BL1=-0.7V, BL2=3V; the programming lines WL1'=3V, WL2'=3V; the word lines WL1=0V, WL2=3V; first preset power supply VDD1=3V; when restoring memory cell A, bit line BL1=3V, BL2=3V; programming line WL1'=1.5V, WL2'=3V; word line WL1 =0V, WL2=3V; the first preset power supply VDD1=3V.

The embodiment of the present disclosure provides a programmable memory array, which includes a plurality of memory cells, and the memory cell includes a first transistor and a second transistor connected in series. When programming the memory cell, since the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is a positive voltage difference, the channel leakage current of the first transistor increases, so that the data stored in the memory cell can be converted to 1; when restoring the memory cell, since the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is a negative voltage difference, the channel leakage current of the first transistor decreases, so that the data stored in the memory cell can be converted to 0; in this way, the memory cell can be repeatedly programmed, and since there is no need to break through the gate oxide layer, it also avoids the use of excessively high voltage stress, can improve the overshoot damage of high voltage to the memory cell, and ultimately improve the performance of the memory.

In another embodiment of the present disclosure, see FIG. 6 , which shows a schematic structural diagram of another programmable memory array provided by an embodiment of the present disclosure. As shown in Figure 6, based on the programmable memory array 20 shown in Figure 3, the programmable memory array 20 can also include a readout circuit 205, and the bit lines pass through different fifth transistors (for example, N21 and N22). Connected to readout circuit 205, where:

The first terminal of the fifth transistor is connected to the bit line, the second terminal of the fifth transistor is connected to the readout circuit 205, the gate terminal of the fifth transistor receives the column selection signal, and the fifth transistor converts the signal corresponding to the bit line according to the column selection signal. transmitted to the readout circuit 205.

It should be noted that in the embodiment of the present disclosure, the number of bit lines is at least one, and accordingly, the number of fifth transistors is at least one, that is, fifth transistors are also distributed in the extension direction of each bit line; and The second end of the at least one fifth transistor is connected to the readout circuit 205 so as to transmit the signal of the corresponding bit line to the readout circuit 205 according to the column selection signal. For example, as shown in FIG. 6 , a fifth transistor N21 is distributed on the bit line BL1. The first end of the fifth transistor N21 is connected to the bit line BL1, and the second end of the fifth transistor N21 is connected to the readout circuit 205. The gate terminal of the fifth transistor N21 is used to receive the column selection signal Y0; a fifth transistor N22 is distributed on the bit line BL2, the first end of the fifth transistor N22 is connected to the bit line BL2, and the second end of the fifth transistor N22 is connected to the read The output circuit 205 is connected, and the gate terminal of the fifth transistor N22 is used to receive the column selection signal Y1. Here, if the column selection signal Y0 is set to a high level, that is, the fifth transistor N21 is turned on, then the signal of the bit line BL1 will be transmitted to the readout circuit 205; if the column selection signal Y1 is set to a high level, that is, the fifth transistor N21 is turned on. By passing the fifth transistor N22, the signal of the bit line BL2 is transmitted to the readout circuit 205. In addition, it should be noted that when reading data, only one of the column selection signals is set to high level, and no voltage is applied to the bit lines BL1\BL2 when reading.

Further, for the readout circuit 205, in some embodiments, as shown in Figure 6, the readout circuit 205 may include a readout resistor R1 and a comparator U1, where:

The first input terminal of the comparator U1 and the first terminal of the reading resistor R1 are both connected to the second terminal of the fifth transistor (for example, N21 and N22). The second terminal of the reading resistor R1 is connected to the ground. The third terminal of the comparator U1 The two input terminals are used to receive the reference voltage, and the output terminal (OUT) of the comparator U1 is used to read the data stored in the target memory unit, where the target memory unit is determined based on the column selection signal and the word line.

In the embodiment of the present disclosure, the reference voltage can be represented by Vref, and the ground can be represented by VSS. Specifically, taking the target memory unit as memory unit A as an example, the bit line voltage of BL2 is equal to 3V in order to prevent non-target cells from being programmed, that is, the first transistor in memory unit C, memory unit D, and memory unit B. P1 will not be attenuated, and then read through bit line BL1. Here, BL1 will be grounded through a read resistor R1, and the outside world will no longer provide bit line voltage to BL1 (that is, -0.7V and 3V will no longer be provided), and the potentials at other positions will remain unchanged. At this time, the third bit in memory cell A One transistor P1 has a large current, so the potential at the connection point between the reading resistor R1 and the bit line BL1 is a high potential. At this time, "1" can be read through the output terminal (OUT) of the comparator U1.

It can be understood that in the embodiment of the present disclosure, the programmable memory array 20 may include a readout circuit and a precharge module. Among them, whether the bit line voltage is 3V or -0.7V is achieved through the precharge module. On the one hand, when programming the target memory cell, the bit line where the target memory cell is located can be precharged to -0.7V; on the other hand, for non-target memory cells, in order to prevent being programmed, the bit line where the non-target memory cell is located can be precharged to -0.7V. lines are precharged to 3V. In the same precharge module, the third transistor and the fourth transistor are selectively turned on to either precharge the bit line to -0.7V or precharge the bit line to 3V.

Taking Figure 6 as an example, when programming the target memory cell (such as memory cell A), the programming line WL1' is set to high potential (3V), the bit line BL1 is pulled down to low potential (-0.7V), and the word line WL1 and the second precharge signal CSL2 are set to low potential (0V), and word line WL2 is set to high potential (3V). In order to protect non-target memory cells (such as memory cell C), it is necessary to set the bit line BL2 to a preset voltage through the precharge module, for example, turning on the third transistor to precharge the bit line voltage of BL2 to 3V; when When the word line WL1 is turned on, the voltage difference between the gate terminal and the drain terminal of the first transistor P1 in the memory cell C is small, so that the memory cell C can be protected.

In addition, when reading data, no voltage is applied to the bit line. At this time, the target memory cell can be determined through the column selection signal and word line. For example, according to the column selection signal Y0 being high level and the word line WL1 being low level, it can be determined that the target memory cell is memory unit A, and then the programming line WL1' still provides 3V. At this time, through the first transistor in memory unit A The leakage current of P1 determines whether the final read data is "1" or "0".

Embodiments of the present disclosure provide a programmable memory array, where two PMOS tubes with thick gate oxide are connected in series to form an MTP fuse unit circuit structure, and the HEIP decay characteristics of the PMOS tubes under forward voltage can be used to increase the The off-state leakage current of the PMOS tube can be used to achieve the transition from "0" to "1"; the HEIP recovery characteristics of the PMOS tube under reverse voltage can be used to reduce the off-state leakage current of the PMOS tube, thereby achieving the transition from "1" to "1". "0" transition; in this way, using the HEIP decay and recovery characteristics of the PMOS tube under forward voltage and reverse voltage for MTP programming can avoid overshoot damage to the memory cells caused by using too high voltage; in addition, this can Programmed memory arrays also have good thermal stability, ultimately improving memory performance.

In yet another embodiment of the present disclosure, see FIG. 7 , which shows a schematic flowchart of a programming method provided by an embodiment of the present disclosure. As shown in Figure 7, the method may include:

S701: When programming the memory cell, control the second transistor to be in a conductive state, and control the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor to be greater than 0.

S702: When restoring the memory cell, control the second transistor to be in a conductive state, and control the voltage difference between the gate of the first transistor and the first terminal of the first transistor to be less than 0.

It should be noted that, in the embodiment of the present disclosure, the programming method is applied to a programmable memory array including multiple memory cells. Wherein, the memory unit may include a first transistor and a second transistor, and the first terminal of the first transistor is connected to the bit line, the gate terminal of the first transistor is connected to the programming line, and the second terminal of the first transistor is connected to the second transistor. The first terminal is connected, the gate terminal of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the first preset power supply.

It should also be noted that in embodiments of the present disclosure, multiple memory units may be distributed in an array. Among them, several memory cells are distributed in the extension direction of the bit line, and several memory cells are connected to the bit line through the first end of the first transistor P1; several memory cells are distributed in the extension direction of the word line, and several memory cells are distributed in the extension direction of the word line. The cells are connected to the word line through the gate terminal of the second transistor P2; several memory cells are distributed in the extending direction of the programming line, and the several memory cells are connected to the programming line through the gate terminal of the first transistor P1.

In some embodiments, the method may further include:

When programming the memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is greater than 0;

When restoring the memory cell, the control voltage of the programming line is lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is less than 0.

It should be noted that in the embodiment of the present disclosure, when programming the memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the gate terminal of the first transistor P1 is connected to the gate terminal of the first transistor P1 The voltage difference at the first terminal is greater than 0. In this way, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a forward voltage difference, the first transistor P1 experiences HEIP degradation characteristics under forward voltage stress, causing the channel leakage of the first transistor P1 The current increases, thereby enabling the data stored in the memory cell to transition from "0" to "1".

It should be noted that, in the embodiment of the present disclosure, when restoring the memory cell, the control voltage of the programming line is controlled lower than the bit line voltage of the bit line, so that the gate terminal of the first transistor and the first terminal of the first transistor The voltage difference is less than 0. In this way, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a negative voltage difference, the first transistor P1 experiences HEIP recovery characteristics under negative voltage stress, causing the channel leakage of the first transistor P1 The current decreases, thereby enabling the transition of the data stored in the memory cell from "1" to "0".

Embodiments of the present disclosure provide a programming method, which is applied to the programmable memory array described in any of the preceding embodiments. In this way, in the programmable memory array, the memory cell can be reprogrammed multiple times, and since there is no need to breakdown the gate oxide layer, excessive voltage stress is avoided and overshoot damage caused by high voltage to the memory cell can be improved. , ultimately improving memory performance.

In yet another embodiment of the present disclosure, see FIG. 8 , which shows a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure. As shown in FIG. 8 , the semiconductor memory 80 at least includes the programmable memory array 20 described in any one of the previous embodiments.

In some embodiments, semiconductor memory 80 may include dynamic random access memory (Dynamic Random Access Memory, DRAM). Among them, DRAM can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5. There are no restrictions here.

In the embodiment of the present disclosure, for the semiconductor memory 80, it mainly involves the circuit design of the fuse memory unit, using a new fuse programming principle to implement a new fuse programming architecture. In this way, the programmable memory array 20 includes multiple memory cells. For each memory cell, two series-connected PMOS tubes are used to form a fuse path. Based on the HEIP decay and recovery characteristics of the PMOS tubes, it can not only support multiple Repeated programming, and because this circuit does not need to breakdown the gate oxide, it avoids the use of excessive voltage stress and prevents overshoot damage to the memory cells due to high voltage, thus improving the performance of the memory.

The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of the present disclosure.

It should be noted that in the present disclosure, the terms "comprising", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements , but also includes other elements not expressly listed or inherent in such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

The features disclosed in several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, and all of them should be covered. within the scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a programmable storage array, a programming method and a semiconductor memory. The programmable storage array includes a plurality of storage units, the storage unit includes a first transistor and a second transistor connected in series; a first terminal of the first transistor Connected to the bit line, the gate terminal of the first transistor is connected to the programming line, the second terminal of the first transistor is connected to the first terminal of the second transistor; the gate terminal of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the bit line. The terminal is connected to the first preset power supply; wherein, when programming the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is controlled to be greater than 0; in When restoring the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0. In this way, based on the memory cell composed of the first transistor and the second transistor connected in series, when programming the memory cell, since the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is a forward voltage difference, the third transistor is programmed. The channel leakage current of a transistor increases, thereby enabling the data stored in the memory unit to change to 1; when the memory unit is restored, because the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is negative The voltage difference reduces the channel leakage current of the first transistor, thereby enabling the data stored in the memory cell to change to 0; in this way, the memory cell can be reprogrammed multiple times, and since there is no need to breakdown the gate oxide layer, This also avoids the use of excessive voltage stress, can improve the overshoot damage of high voltage to memory cells, and ultimately improves the performance of the memory.

Claims (19)

1. A programmable memory array including:

   a plurality of memory cells, the memory cells including first transistors and second transistors connected in series;

   The first terminal of the first transistor is connected to the bit line, the gate terminal of the first transistor is connected to the programming line, and the second terminal of the first transistor is connected to the first terminal of the second transistor;

   The gate terminal of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the first preset power supply;

   Wherein, when programming the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is controlled to be greater than 0;

   When restoring the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0.
2. The programmable memory array according to claim 1, wherein the plurality of memory cells are distributed in an array, wherein:

   A plurality of the memory cells are distributed in the extending direction of the bit line, and the plurality of memory cells are connected to the bit line through the first end of the first transistor;

   A plurality of the memory cells are distributed in the extending direction of the word line, and the plurality of memory cells are connected to the word line through the gate terminal of the second transistor;

   A plurality of the memory cells are distributed in the extension direction of the programming line, and the plurality of memory cells are connected to the programming line through the gate terminal of the first transistor;

   The extension direction of the bit line and the extension direction of the word line are perpendicular to each other, and the extension direction of the programming line and the extension direction of the word line are parallel to each other.
3. The programmable memory array according to claim 2, wherein precharge modules are also distributed in the extending direction of the bit lines, wherein:

   The precharge module is configured to receive a precharge signal, precharge the bit line according to the precharge signal, and precharge the bit line voltage of the bit line to a preset voltage.
4. The programmable memory array of claim 3, wherein the precharge module includes a third transistor and a fourth transistor, wherein:

   The first terminal of the fourth transistor is connected to the first voltage, the second terminal of the fourth transistor is connected to the bit line, and the gate terminal of the fourth transistor is used to receive the first precharge signal and to the When the memory cell is programmed, the first precharge signal turns on the fourth transistor to precharge the bit line where the memory cell is located to the first voltage;

   The first terminal of the third transistor is connected to the second voltage, the second terminal of the third transistor is connected to the bit line, and the gate terminal of the third transistor is used to receive the second precharge signal and restore the When storing the cell, the second precharge signal turns on the third transistor to precharge the bit line where the memory cell is located to the second voltage;

   Wherein, the first voltage is lower than the second voltage.
5. The programmable memory array according to claim 4, wherein the first voltage ranges from -0.7V to 0V, and the second voltage ranges from 2.5V to 3V.
6. The programmable memory array of claim 5, wherein the first voltage is -0.7V and the second voltage is 3V.
7. The programmable memory array according to claim 2, wherein the programmable memory array further includes a first power module and a second power module, and the first power module is connected to the programming line, and the second power module The power module is connected to the word line, where:

   The first power module is configured to provide a control voltage for the programming line;

   The second power module is configured to provide a word line voltage for the word line.
8. The programmable memory array of claim 7, wherein:

   When programming the memory cell, the control voltage of all the programming lines is controlled by the first power module to be a third voltage;

   When restoring the memory unit, the first power module controls the control voltage of the programming line where the memory unit is located to be a fourth voltage, and controls the control voltage of other programming lines to be a third voltage;

   Wherein, the third voltage is higher than the fourth voltage.
9. The programmable memory array according to claim 8, wherein the third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V.
10. The programmable memory array of claim 9, wherein the third voltage is 3V and the fourth voltage is 1.5V.
11. The programmable memory array of claim 7, wherein:

    When the word line is selected, the word line voltage of the word line is controlled to be a fifth voltage through the second power module; or,

    When the word line is not selected, controlling the word line voltage of the word line to a sixth voltage through the second power module;

    Wherein, the fifth voltage is lower than the sixth voltage.
12. The programmable memory array of claim 11, wherein:

    When the word line is selected, if the fifth voltage is lower than the power supply voltage of the first preset power supply, it is determined that the second transistor is in a conducting state; or,

    When the word line is not selected, if the sixth voltage is greater than or equal to the power supply voltage of the first preset power supply, it is determined that the second transistor is in an off state.
13. The programmable memory array of claim 11, wherein the fifth voltage is 0V and the sixth voltage is 3V.
14. The programmable memory array according to claim 2, wherein the programmable memory array further includes a readout circuit, and the bit lines are respectively connected to the readout circuit through different fifth transistors, wherein:

    The first terminal of the fifth transistor is connected to the bit line, the second terminal of the fifth transistor is connected to the readout circuit, the gate terminal of the fifth transistor receives the column selection signal, and the fifth transistor has a gate terminal connected to the readout circuit. The transistor transmits the signal corresponding to the bit line to the readout circuit according to the column selection signal.
15. The programmable memory array of claim 14, wherein the readout circuit includes a read resistor and a comparator, wherein:

    The first input terminal of the comparator and the first terminal of the reading resistor are both connected to the second terminal of the fifth transistor. The second terminal of the reading resistor is connected to ground. The second terminal of the comparator The input terminal is used to receive a reference voltage, and the output terminal of the comparator is used to read data stored in a target storage unit, wherein the target storage unit is determined based on the column selection signal and the word line.
16. The programmable memory array according to any one of claims 1 to 15, wherein the first transistor is a PMOS transistor, and the second transistor is a PMOS transistor.
17. A programming method applied to a programmable memory array including a plurality of memory cells, the memory unit includes a first transistor and a second transistor, and a first end of the first transistor is connected to a bit line, and the first The gate terminal of the transistor is connected to the programming line, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate terminal of the second transistor is connected to the word line, and the third terminal of the second transistor is connected to the word line. The two ends are connected to the first preset power supply; the method includes:

    When programming the memory cell, control the second transistor to be in a conductive state, and control the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor to be greater than 0;

    When restoring the memory cell, the second transistor is controlled to be in a conductive state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0.
18. The method of claim 17, further comprising:

    When programming the memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the voltage of the gate terminal of the first transistor and the first terminal of the first transistor The difference is greater than 0;

    When restoring the memory cell, the control voltage of the programming line is controlled to be lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor Less than 0.
19. A semiconductor memory including the programmable memory array according to any one of claims 1 to 16.

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