JPS62206877A - Semiconductor nonvolatile ram - Google Patents

Abstract

PURPOSE:To prevent the annihilation of informations even when supply voltage drops by adding EPROMs to each cell for a semiconductor RAM. CONSTITUTION:A recall transistor Tr1 and a Tr2 using a floating gate electrode as a gate electrode are connected at an anode C in a semiconductor RAM, and a source electrode for the Tr2 is grounded. Another output node D in the semiconductor RAM is connected to a transistor, to which Vs is applied as gate potential, and an MOS capacitor employing a floating gate electrode as a gate electrode. Consequently, the potential of the floating gate electrode 2 is changed by the potential of the node D, thus resulting in store operation. Supply voltage is applied to the gate electrode for the Tr1, thus allowing recall operation. That is, the semiconductor RAM in which information are not annihilated even when supply voltage drops is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to a semiconductor non-volatile RAM used in multiplex devices such as computers.

(Summary of the Invention) The present invention provides a semiconductor RAM in which each single conductor RA
Electrically rewritable semiconductor non-volatile memory (M cell)
By connecting EIEPROM (hereinafter referred to as 1), the Otsu information will not be erased even if the power is turned off.

(Prior Art) Conventionally, in a semiconductor RAM as shown in FIG. 2, a voltage is applied from a bit line to a node A or B via a word line, that is, information is written. Also, information is read from node A or B via the word line.
The potential was transmitted to the bit line or bit bar line and output.

(Problems to be Solved by the Invention) As shown in FIG.
Since the potential is the output of each inverter when two stages of inverters are connected in series, a stable state can be maintained. However, if the power supply voltage drops due to a power outage, etc., the inverter will fall outside the operating voltage range, causing the problem that information will be lost.

SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, it is an object of the present invention to provide a semiconductor nonvolatile RAM in which information does not disappear even when the power supply voltage decreases.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a semiconductor RA
By creating a simple circuit configuration in which an EEPROM is added to each cell of M, information is not lost even when the power supply voltage drops.

(Function) By adding an EEPROM to the semiconductor RAM as described above, the information in the electrically volatile semiconductor RAM is transferred to the electrically non-volatile EEPROM, and the
This makes it possible to return information from the EP ROM to the semiconductor RAM. In other words, it becomes possible to create a semiconductor RAM that does not retain information even when the power supply voltage decreases.

(Example) Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 does not show a circuit diagram of the semiconductor nonvolatile RAM of the present invention. A recall transistor T is connected to the node C of the semiconductor RAM.
r1 is connected to r2 whose gate electrode is a floating gate electrode, and the source electrode of Tr2 is grounded. The other output node D of the semiconductor RAM is connected to a transistor to which VS is applied as a gate potential and a MOS capacitor whose gate electrode is a floating gate electrode. FIG. 1 depicts a Tr3 in which a transistor whose gate potential is VS and a MOS capacitor whose gate electrode is a floating gate electrode are combined into one transistor structure. The gate insulating film between the floating gate electrode of Tr3 and the substrate is a tunnel insulating film with a thickness of approximately 100 mm. FIG. 3 is a cross-sectional view of Tr3. A voltage VS is applied to the gate 'fIi pole 4 of the store transistor, and its drain region VL5 is connected to the node D of the semiconductor RAM shown in FIG.

The floating gate electrode 2 is used as a gate electrode, and the tunnel insulating film 3 is used as a gate electrode.
MOS transistors having a gate insulating film are connected in series via a store transistor.

The operation of the semiconductor nonvolatile RAM of the present invention will be explained in detail with reference to FIGS. 1, 3, and 4.

First, a store operation will be described in which the information in the semiconductor RAM is not transferred to the EEr'ROM.

First, the erase voltage (■) applied to the erase electrode of Tr2 is approximately 20V.
Apply a high voltage of Floating gate electrode (FG in Figure 1)
) and the applied voltage of the control gate electrode with large capacitive coupling ■. 6 is set to the same potential as the substrate. Since the potential of the floating gate electrode is almost equal to the substrate potential due to the potential of the control gate electrode cG, a large electric field is applied between the floating gate electrode and the dissipating electrode, causing the electrons in the floating gate electrode to be erased. It goes out to the electrode. That is, the potential of the floating gate electrode is positively charged. Next, the potential V of the control gate electrode.

. When the voltage is increased to about 20V, the potential of the floating gate electrode also becomes high. At this time, if the potential of the node D of the semiconductor RAM in FIG. 1 is close to the substrate potential, the surface potential under the tunnel insulating film 3 becomes equal to the potential of the node D due to the potential Vs of the gate electrode 4 in FIG. . Therefore, a strong electric field is applied to the tunnel insulating film 3, causing electrons to flow from the substrate 1 to the floating goo 1-electrode 2.

Conversely, if the potential of the node D of the semiconductor RAM in FIG. 1 is a high potential near the power supply voltage, the potential of the drain region 5 becomes high at J3 in FIG. Or: Becomes F state.

Therefore, the surface potential of the channel region under the tunnel insulating film 3 and the rain region 5 are electrically disconnected. Therefore, even though the floating gate electrode 2 has a high potential, no large voltage is applied to the tunnel insulating film 3, so no tunnel current flows through the tunnel insulating film 11A3.

As explained above, when the potential of the node D is as low as the potential of the substrate 1, the potential of the floating gate electrode 2 is negatively charged due to electron injection, and conversely, the potential of the node D is as high as the power supply voltage. In the case of electric potential, the electric potential of the floating gate electrode 2 becomes positively charged.

That is, the potential of the floating gate electrode 2 changes depending on the potential of the node D, thereby enabling the store operation.

Next, a description will be given of a recall operation in which information stored in the EEr'ROM is returned to the semiconductor RAM by a store operation.

The recall operation is based on the gate-1f pressure V1 of Trl in FIG.
If a voltage 1, for example, a power supply voltage 1-, higher than its threshold voltage is applied to
It is clamped to the same low potential as the base plates. On the other hand, when the floating gate electrode reaches a negative voltage, the node D is always clamped to a potential as high as the power supply voltage. this is,
This can be easily done due to the design of ZF i9 RAM.

As explained above, the gate voltage vR of Trl in FIG.
Recall operation becomes possible by applying a power supply voltage to .

FIG. 4 shows the potential of each electrode in the store operation and recall operation. EEr'ROM at time tp after erasing time tc'C''
program to. Sum of student time and program time
is the store time. Further, the recall time is the time tn during which ■R becomes the power supply voltage 5■.

FIG. 5 shows a second embodiment of the semiconductor nonvolatile RAM of the present invention. The embodiment shown in FIG. 5 is a circuit in which the gate electrode 4 shown in FIG. 3 also serves as an erase electrode. Erase electrode with high voltage applied and control goo! - If the electrodes are provided on the substrate, the current during storage can be reduced, so the back pressure circuit can be made smaller.

Store and recall operations can be performed by setting the voltages of each electrode at timings as shown in the timing diagram A7 of FIG.

In the case of Figure 1, the operation as a normal semiconductor RAM is as follows.
By turning off the transistors Trl and Tr3, and in the case of FIG.
By turning off the transistor, it can operate regardless of the state of the EEPROM.

(Effects of the Invention) As explained above, the present invention has the effect that information does not disappear even if the power supply voltage decreases by adding an EEPROM to each rail of the semiconductor RAM.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a semiconductor non-volatile RAM for use in the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor non-volatile RAM. FIG. 3 is a cross-sectional view of Tr3 of the MOS transistor of the first embodiment of the semiconductor non-volatile RAM of the present invention, and FIG. 4 is a timing diagram of the potential of each electrode in the embodiment of FIG. . FIGS. 5 and 6 are a circuit diagram of a second embodiment of the semiconductor nonvolatile RAM of the present invention and a timing diagram of the potential of each electrode. 1...P-type semiconductor substrate 2...Floating gate electrode 3...Tunnel insulating film 4...Gate electrode 5...Drain region Applicant Reiko Denryo Gyo Co., Ltd. Figure 1 Conventional surprise 4 SATRAMQ time AZ Fig. 2 EEPROM in Rffi Fig. 3 s Fig. 2 @ 3- @ Haya 〉 Google ゛ ゛ 〉 Fig. 6 LIJ 〉 ME〉 Sac ---

Claims (1)

[Claims] The first output terminal of the static RAM is an EEPR whose gate electrode is a recall transistor and a floating gate electrode.
A second output terminal, which is grounded through a series connection with an OM transistor and which is different from the first output terminal, connects the floating gate electrode to the gate electrode through a store transistor, and connects the tunnel insulating film to the gate insulating film. A semiconductor nonvolatile RAM characterized in that it is connected to a MOS capacitor.