JP3993581B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to an electrically rewritable nonvolatile semiconductor memory device.

  In recent years, a NAND cell type EEPROM has been proposed as one type of nonvolatile semiconductor memory device (EEPROM) that can be electrically rewritten. In this EEPROM, for example, a plurality of memory cells having an n-channel MOSFET structure in which, for example, a floating gate and a control gate are stacked as a charge storage layer, their sources and drains are shared by adjacent ones, This is connected to the bit line as a unit.

FIGS. 20A and 20B are a pattern plan view and an equivalent circuit diagram of one NAND cell portion of a memory cell array in a conventional NAND type EEPROM, respectively. FIGS. 21A and 21B are cross-sectional views taken along lines AA ′ and BB ′ of the pattern shown in FIG. A p-type semiconductor substrate surrounded by an element isolation oxide film 12 (in this example, an n-type well region 11-2 is formed in a p-type silicon substrate 11-1, and a p-type well is formed in the n-type well region 11-2. A region 11-3 is formed, but a p-type silicon substrate can be used), and a memory cell array composed of a plurality of NAND cells is formed. To explain with a focus on one NAND cell, in this example, eight memory cells M _{1 to} M ₈ are connected in series to constitute one NAND cell. Each of the memory cells M _{1 to} M ₈ has a floating gate 14 (14 ₁ , 14 ₂ , 14 ₃ ,..., 14 ₈ ) formed on the substrate 11 via a gate insulating film 13. The control gates 16 (16 ₁ , 16 ₂ , 16 ₃ ,..., 16 ₈ ) are stacked through the insulating film 15. The n-type diffusion layers 19 which are the source and drain of these memory cells are connected in series so that adjacent ones are shared.

First and second select transistors S ₁ and S ₂ are provided on the drain side and the source side of the NAND cell, respectively. These selection transistors S ₁ and S ₂ include first selection gates 14 ₉ and 16 ₉ and second selection gates 14 ₁₀ and 16 ₁₀ formed simultaneously with the floating gate and control gate of the memory cell. The selection gates 14 ₉ and 16 ₉ are electrically connected in a region (not shown), and the selection gates 14 ₁₀ and 16 ₁₀ are also electrically connected in a region (not shown) and function as gate electrodes of the selection transistors S ₁ and S ₂ , respectively. . The substrate on which the element is formed is covered with a CVD oxide film 17, and a bit line 18 is disposed thereon. The control gates 16 of the NAND cells are commonly arranged as control gate lines CG ₁ , CG ₂ ,... CG ₈ . These control gate lines become word lines. The selection gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged as selection gate lines SG ₁ and SG ₂ continuously in the row direction, respectively.

  FIG. 22 shows an equivalent circuit diagram of a memory cell array in which NAND cells as described above are arranged in a matrix. The source line is connected to a reference potential wiring such as Al or polysilicon via a contact, for example, every 64 bit lines. This reference potential wiring is connected to a peripheral circuit. The control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction. Usually, a set of memory cells connected to the control gate is called one page, and a set of pages sandwiched by one set of drain side (first selection gate) and source side (second selection gate) selection gates is 1 NAND. This is called a block or simply one block. One page is composed of, for example, 256 bytes (256 × 8) memory cells. One page of memory cells are written almost simultaneously. One block is composed of, for example, 2048 bytes (2048 × 8) memory cells. The memory cells for one block are erased almost simultaneously.

  In the above configuration, data is written in order from the memory cell farther from the bit line. 0V ("0" write) or power supply voltage Vcc ("1" write) is applied to the bit line according to the data. The selection gate connected to the bit line is the power supply voltage Vcc, and the selection gate connected to the source line is 0V. At this time, 0 V is transmitted to the channel of the cell in which “0” is written. In “1” writing, the selection gate connected to the bit line is turned off. Therefore, the channel of the memory cell to which “1” is written becomes Vcc−Vthsg (Vthsg is the threshold voltage of the selection gate) and becomes floating. Alternatively, when the threshold voltage of the memory cell closer to the bit line than the memory cell to be written has a positive voltage Vthcell, the channel of the memory cell becomes Vcc−Vthcell. Thereafter, the boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and the intermediate potential Vpass (= about 10V) is applied to the control gate of the other non-selected memory cells. As a result, when the data is “0”, since the channel potential is 0 V, a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunneled from the substrate to the floating gate, and the threshold voltage is positive. Move to. When the data is “1”, the floating channel is at an intermediate potential (about 6 V) due to capacitive coupling with the control gate, and electrons are not injected.

  On the other hand, data erasure is performed almost simultaneously in units of blocks. That is, all the control gates of the block to be erased are set to 0 V, and the boosted potential VppE (about 20 V) is applied to the p-type well region 11-3 and the n-type well region 11-2. The control gate of the block that is not erased is boosted to the VppE level by capacitive coupling with the p-type well region 11-3 from the floating state. As a result, electrons in the floating gate are emitted to the p-type well region 11-3 in the memory cell of the block to be erased, and the threshold voltage moves in the negative direction. In a block where erasure is not performed, erasure is not performed because both the control gate and the p-type well region 11-3 are VppE.

  In the data read operation, the bit line is precharged to the power supply voltage Vcc and then floated, the control gate of the selected memory cell is set to 0 V, the control gates of other memory cells, and the selection gate are set to the power supply voltage Vcc (for example, 3 V). This is done by setting the source line to 0 V and detecting on the bit line whether or not current flows in the selected memory cell. That is, if the data written in the memory cell is “0” (threshold voltage Vth> 0 of the memory cell), the memory cell is turned off, so that the bit line maintains the precharge potential, but “1” (memory cell If the threshold voltage Vth <0), the memory cell is turned on and the bit line is lowered from the precharge potential by ΔV. By detecting these bit line potentials with a sense amplifier, data in the memory cell is read out.

  In the conventional reading method, after the bit line is precharged to the stepped down power supply voltage Vdd (for example, 2.5 V) inside the chip, the bit line is discharged to 0.5 V or less in the case of “1” reading, In the case of “0” reading, Vdd is maintained. The bit line discharge time Tbl at the time of “1” reading is Tbl = Cbl × Vbl / Icell with respect to the bit line capacitance Cbl, the bit line amplitude Vbl, and the memory cell current Icell. In the NAND type EEPROM, since the memory cells are connected in series, the memory cell current Icell is small. As a result, there is a problem that the bit line discharge time Tbl is large and the reading is long. For example, if the bit line capacitance is 3 pF and the current flowing through the memory cell during “1” reading is 0.5 μA, the bit line discharge time is 3 pF × (2.5 V−0.5 V) /0.5 μA = 12 μsec.

Furthermore, the conventional NAND flash memory has the following problems during reading. For example FIG. 20 (a), the in the case where the memory cell M5 (b), data is read, the control gate lines CG ₅ ground, the selection gate lines _SG 1, SG _2, the control gate lines _{CG 1, CG 2, CG 3} , CG ₄ , CG ₆ , CG ₇ , CG ₈ are set to the power supply voltage Vcc. The timings for biasing the control gate line and the selection gate line are all biased simultaneously, or first, the control gate lines CG _{1 to} CG ₈ and the selection gate line SG ₂ are set to the power supply voltage Vcc, and then the selection gate line SG ₁ is set. Bias to power supply voltage Vcc. When the memory cell M5 is turned on, float also the control gate lines CG ₅ by capacitive coupling between the channel and the control gate. For example, when the channel is charged from 0 V to 1.2 V, the control gate line CG ₅ floats to about 0.5 V, and then returns to 0 V after the RC time constant (about 1 μsec) of the control gate. As described above, when the control gate floats to about 0.5 V due to the capacitive coupling noise between the channel and the control gate, the “0” cell that should originally be turned off is also turned on, which causes a problem of erroneous reading.

  By the way, at the time of reading and writing of the nonvolatile semiconductor memory device including the above-described NAND type EEPROM, it is necessary to apply a voltage VH higher than the power supply voltage Vcc to a predetermined node Na of the sense amplifier or the row decoder. A conventional voltage bias circuit for biasing the node Na is configured as shown in FIG. 23, for example. This voltage bias circuit includes transistors Q1, Q2, and Q3, an inverter INV1, and a high voltage switch SW1, and selectively supplies a power voltage Vcc, a ground voltage Vss, and a high voltage VH higher than the power voltage Vcc to the node Na. To be applied. The high voltage switch SW1 includes transistors Q4 to Q7 and a capacitor C. In FIG. 23, transistors Q3 to Q6 labeled HN are high voltage (high withstand voltage) enhancement type n-channel transistors to which a voltage higher than the power supply voltage Vcc can be applied. Since the threshold voltages of these transistors Q3 to Q6 are about 0.6V, they turn off when 0V is applied to their gates. On the other hand, the transistors Q2 and Q7 labeled DHN are high-voltage depletion type n-channel transistors. The threshold voltages of these transistors Q2 and Q7 are -1V. When the gate and drain are set to the power supply voltage Vcc, the power supply voltage Vcc can be transferred to the source. When the gates of the transistors Q2 and Q7 are set to 0V, the source / drain voltage is turned off under the condition of the power supply voltage Vcc. The transistor Q1 is a low-voltage p-channel transistor to which a voltage equal to or lower than the power supply voltage Vcc is applied. The transistor Q2 connected in series to the transistor Q1 is for preventing a high voltage from being applied to the transistor Q1.

  In the above configuration, when the node Na is grounded, the voltage V3 applied to the gate of the transistor Q3 is the power supply voltage Vcc, the voltage V1 applied to the input terminal of the inverter INV1 and the gate of the transistor Q2 is the ground voltage Vss, and the transistor The voltage V2 applied to one end of the current path of Q7 may be the ground voltage Vss. When the clock signal CLK is applied to one electrode of the capacitor CB1 with the voltages V1 and V3 set to the ground voltage Vss and the voltage V2 set to the power supply voltage Vcc, the high voltage VH is applied to the node Na via the high voltage switch SW1. . When the voltage V1 is the power supply voltage Vcc and the voltages V2 and V3 are the ground voltage Vss, the node Na is biased to the power supply voltage Vcc.

  However, in the conventional voltage bias circuit as shown in FIG. 23, when changing the node Na from the high voltage VH to the power supply voltage Vcc, first the voltage V3 is changed to the power supply voltage Vcc, whereby the node Na is connected via the transistor Q3. To discharge. Thereafter, the voltage Na is set to the power supply voltage Vcc via the transistors Q1 and Q2 by setting the voltage V1 to the power supply voltage Vcc. As described above, when the node Na is changed from the high voltage VH to the power supply voltage Vcc, since it is grounded and then charged to the power supply voltage Vcc, it takes time and the current consumption increases.

  On the other hand, when the voltage V1 is changed to the power supply voltage Vcc in order to discharge the node Na directly from the high voltage VH to the power supply voltage Vcc, VH is applied to the source (p-type semiconductor region) of the transistor Q1, and the substrate (n The pn junction diode between the first semiconductor region and the second semiconductor region is turned on. As a result, there is a problem of causing latch-up.

  The present invention has been made in view of the above circumstances, and a first object is to provide a semiconductor memory device capable of shortening a bit line discharge time and shortening a read time.

  A second object of the present invention is to provide a semiconductor memory device capable of preventing erroneous reading even when the potential of the control gate rises due to capacitive coupling noise between the channel and the control gate.

A semiconductor memory device according to one embodiment of the present invention includes a memory cell portion including at least one memory cell, a first selection transistor connecting the memory cell portion and a source line, and connecting the memory cell portion and a bit line. A second select transistor that is connected to the bit line and is connected to the bit line and is not connected to a write circuit at the time of writing. the bit lines, boosted power supply voltage is supplied to the gate connected to the step-down power supply voltage within the chip by turning on and step-down power supply voltage is the gate of the chip during standby after the completion of writing It is supplied to a third transistor for grounding the bit line by turning on the memory cell portion from the bit line In a read operation to flow a current to the source line via the second selection transistor is so turned on, the gate of the second selection transistor by applying a predetermined voltage, a predetermined gate of the memory cell After the voltage is applied, the gate voltage of the memory cell reaches a predetermined voltage, and the voltage that has fluctuated due to capacitive coupling noise between the channel and gate of the memory cell returns to the predetermined voltage, the first selection is performed. A predetermined voltage is applied to the gate of the first selection transistor so that the transistor is turned on.

The semiconductor memory device according to one embodiment of the present invention includes a memory cell portion including a plurality of memory cells connected in series to each other, a first selection transistor that connects the memory cell portion and a source line, and the memory cell A second selection transistor for connecting the bit line and the bit line; a sense amplifier connected to the bit line for reading data of the memory cell by detecting a potential of the bit line; and connected to the bit line for writing not connected to the bit line during a write circuit, connected to the step-down power supply voltage within the chip by the boosted power supply voltage is turned on is supplied to the gate, and the step-down in the chip standby state after completion of writing and a power supply voltage is supplied to the gate and a third transistor for grounding the bit line by turning on the bit line In a read operation to flow a current to the source line via the Luo memory cell portion, as described above second selection transistor is turned on, a predetermined voltage is applied to the gate of the second selection transistors, said memory cells A read voltage is applied to a selected memory cell in a portion, a predetermined voltage is applied to a gate of the unselected memory cell so that the unselected memory cell in the memory cell portion is turned on, and the unselected memory cell The first selection transistor is turned on after the gate voltage of the first voltage reaches a predetermined voltage and the voltage that has fluctuated due to capacitive coupling noise between the channel and the gate of the memory cell returns to the predetermined voltage. A predetermined voltage is applied to the gate of the first selection transistor.

  According to the present invention, a nonvolatile semiconductor memory device that can shorten the bit line discharge time and shorten the read time can be obtained.

  In addition, a semiconductor memory device can be obtained that can prevent erroneous reading even when the potential of the control gate rises due to capacitive coupling noise between the channel and the control gate.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of a NAND cell type EEPROM for explaining a semiconductor memory device according to an embodiment of the present invention. This NAND type EEPROM has a memory cell array 1 for storing data, a sense amplifier / latch circuit 2 for writing and reading data, a row decoder 3 for selecting word lines, a column decoder 4 for selecting bit lines, and an address buffer 5. , I / O sense amplifier 6, data output buffer 7, substrate potential control circuit 8 and the like. In addition, although not shown, a booster circuit that generates a read voltage, a write voltage, and an erase voltage is provided.

  The memory cell array 1 has the same configuration as the conventional NAND-type EEPROM shown in FIGS. 20A, 20B, 21A, 21B, and FIG.

  The sense amplifier / data latch circuit 2 and the row decoder 3 are configured as shown in FIGS. That is, in the sense amplifier / data latch circuit 2 shown in FIG. 2, the two bit lines BL0 and BL1 share one sense amplifier in order to reduce the capacitance coupling noise between the bit lines. One end of the select transistor in the NAND cell shown in FIGS. 20A and 20B and FIGS. 21A and 21B is connected to the bit lines BL0 and BL1. One end of a current path of n-channel transistors Tr1, Tr2, Tr3, Tr4 is connected to both ends of these bit lines BL0, BL1, respectively. A signal BLCU0 is supplied to the gate of the transistor Tr1, a signal BLTR0 is supplied to the gate of the transistor Tr2, a signal BLCU1 is supplied to the gate of the transistor Tr3, and a signal BLTR1 is supplied to the gate of the transistor Tr4. The other ends of the current paths of the transistors Tr1 and Tr3 are commonly connected, and a signal BLCRL is input. The other ends of the current paths of the transistors Tr2 and Tr4 are connected in common, and are connected to one end of the current paths of the n-channel transistors Tr5 and TrN1. A signal BLCD is supplied to the gate of the transistor Tr5, and a signal BLCRAMP is supplied to the gate of the transistor TrN1. The other input side node N1 of the current path of the transistor Tr5 is connected to the first input terminal of the latch circuit LA and one end of the current paths of the transistors Tr6 and Tr7. The latch circuit LA is composed of p-channel transistors Tr8 to Tr11 and n-channel transistors Tr12 and Tr13. The operation of the latch circuit LA is controlled in response to a signal SAP supplied to the gates of the transistors Tr8 and Tr9. The second input terminal (node N2) of the latch circuit LA is connected to one end of the current path of the n-channel transistor Tr14. A signal BLSEN0 is supplied to the gate of the transistor Tr14. The other end of the current path of the transistors Tr7 and Tr14 is connected to one end of the current path of the transistor TrN3. The other end of the current path of the transistor TrN3 is grounded, and the other end of the current path of the transistor TrN1 is connected to the gate (sense node Nsense). Further, a current path of an n-channel transistor TrN2 is connected between the sense node Nsense and the power supply Vdd, and a signal BLPRE is supplied to the gate of the transistor TrN2. Between the sense node Nsense and the ground Vss, a source and a drain are commonly connected, and an n-channel transistor TrN4 serving as a capacitor is connected.

  Further, one end of the current path of the n-channel transistor Tr15, the gate of the n-channel transistor Tr16, and one end of the current path of the n-channel transistor Tr17 are connected to the node N2. The other end of the current path of the transistor Tr15 is grounded, and a signal SAPRST is supplied to the gate. A signal FLAG is supplied to one end of the current path of the transistor Tr16. A current path of an n-channel transistor Tr18 is connected between the other end of the current path of the transistor Tr16 and the ground, and a signal VERIFY is supplied to the gate of the transistor Tr18. A common column selection signal line CSL is connected to the gates of the transistors Tr6 and Tr17, and input / output signal lines IO and IOn are connected to the other ends of the current paths of the transistors Tr6 and Tr17.

  The row decoder 3 shown in FIG. 3 includes block address selection circuits 20-1, 20-2,... Provided for each of the memory cell blocks 1, 2,. The block addresses are supplied to the block address selection circuits 20-1, 20-2,..., And the output signals RDECI1, RDECI2,. It has become so. Focusing on block 1, the output signal RDECI1 of the block address selection circuit 20-1 is supplied to one input terminal of the NAND gate 21-1, one end of the current path of the transistor Tr20, and the input terminal of the inverter 22-1. The The other input terminal of the NAND gate 21-1 is supplied with the signal OSCRD, and its output terminal is one electrode of the capacitor C1 formed by commonly connecting the source and drain of the transistor and the input terminal of the inverter 23-1. Connected to. The output terminal of the inverter 23-1 is connected to one electrode of a capacitor C2 formed by commonly connecting the source and drain of the transistor. One end of the current path of the n-channel transistors Tr21 and Tr22 and the gate of the transistor Tr22 are connected to the other electrode of the capacitor C2. The signal VRDEC is supplied to the other end of the current path of the transistor Tr21, and the gate is connected to the other electrode of the capacitor C1. The other end of the current path of the transistor Tr22 is connected to the other electrode of the capacitor C1. A signal VRDEC is supplied to one end of the current path of the n-channel transistor Tr23, and the other end and gate of the transistor Tr23 are connected to the other electrode of the capacitor C1.

  One end of the current path of the transistor Tr24 is connected to the other end of the current path of the transistor Tr20, and a signal BSTON is supplied to the gate. The other end of the current path of the transistor Tr24 is connected to the other end of the current path of the transistor Tr23 and the gates of the n-channel transistors TrSG1, TrCG1 to TrCG16, TrSG2. A signal SGD is supplied to one end of the current path of the transistor TrSG1, and the other end of the current path is connected to the select gate line SG1 in the adjacent block 2. One end of the current path of the n-channel transistor Tr25 is connected to the selection gate line SG1, and the output signal RDECI1B of the inverter 22-1 is supplied to the gate. Furthermore, one end of the current path of the n-channel transistor Tr26 is connected to the other end of the current path of the transistor Tr25. The output signal RDECI2B of the inverter 22-2 is supplied to the gate of the transistor Tr26, and the signal SGDS is supplied to the other end of the current path. Signals CGN1 to CGN16 are supplied to one end of the current paths of the transistors TrCG1 to TrCG16, and control gate lines CG1 to CG16 are connected to the other ends of the current paths. The signal SGS is supplied to one end of the current path of the transistor TrSG2, and the other end of the current path is connected to the selection gate line SG2. One end of the current path of the n-channel transistor Tr27 is connected to the selection gate line SG2, the signal RDECI1B is supplied to the gate, and the signal SGDS is supplied to the other end of the current path.

  Block 2 has basically the same configuration as block 1.

  2 and 3, the transistors Tr1 to Tr4, Tr21, Tr23, Tr25 to Tr27, TrSG1, TrCG1 to TrCG16, and TrSG2 denoted by HN are high voltages that can apply a voltage higher than the power supply voltage Vcc. (High breakdown voltage) enhancement type n-channel transistor. The threshold voltage of these transistors is about 0.6V, and is turned off when 0V is applied to the gate. On the other hand, transistors Tr20, Tr25, C1, and C2 labeled HND are high voltage depletion type n-channel transistors. The threshold voltage of HND is -1V. When the gate and drain are set to the power supply voltage Vcc, the power supply voltage Vcc can be transferred to the source. When the gate of the HND is set to 0V, the source / drain voltage is turned off under the condition of the power supply voltage Vcc. The transistor Tr22 labeled HNI is an intrinsic type transistor having a threshold voltage of around 0V. The transistors Tr5 to Tr18 and TrN1 to TrN4 are low voltage transistors to which a voltage equal to or lower than the power supply voltage Vcc is applied.

  FIG. 4 is a cross-sectional view schematically showing the well structure of the NAND-type EEPROM shown in FIGS. The NAND type EEPROM has a high voltage n-channel transistor portion 11A, a low voltage n-channel transistor portion 11B, a low voltage p-channel transistor (p-channel MOS transistor) portion 11C, and a memory cell portion 11D. The high voltage n-channel transistor portion 11 </ b> A to which a voltage higher than the power supply voltage is applied is formed in the p-type silicon substrate 11. The low voltage n-channel transistor portion 11B is formed in the p-type well region, and the low voltage p-channel transistor portion 11C is formed in the n-type well region. Memory cell portion 11D is formed in a p-type well region in an n-type well region formed in a p-type silicon substrate. The n-type well region and the p-type well region in the memory cell portion 11D are set to the same potential.

  Next, the read operation will be schematically described with reference to FIGS. 5A to 5D, Vdd is an on-chip power supply voltage (2.5 V) generated by stepping down an externally supplied power supply voltage in the chip. The transistor TrN1 is a clamp transistor whose gate is set to a voltage lower than the power supply voltage Vdd at the time of bit line precharging and sensing. The transistor TrN2 is a transistor connected between the power supply Vdd and the sense node Nsense to charge the bit line, and the transistor TrN3 is a sense transistor. The transistor TrN4 functions as a stabilization capacitor for preventing the sense node Nsense from fluctuating due to coupling noise.

  First, as shown in FIG. 5A, after the bit line is precharged to 1V, it becomes floating. Thereafter, the charge on the bit line is discharged through the memory cell (FIG. 5B). When the bit line is discharged, the signal BLCLAMP is set to 0V and the signal BLPRE is set to 3.8V to charge the sense node Nsense to the power supply voltage Vdd. After the bit line discharge, the signal BLCLAMP is set to 1.5V. Since the bit line for reading “1” is 0.5V or less, the transistor TrN1 is turned on, and the sense node Nsense is 0.5V or less (FIG. 5C). As a result, the sense transistor TrN3 is turned off.

  On the other hand, since the bit line for reading “0” is higher than 0.5 V, the transistor TrN1 is turned off and the sense node Nsense maintains the power supply voltage Vdd (FIG. 5D). As a result, the sense transistor TrN3 is turned on. Thus, in the present embodiment, the sense node Nsense swings from 2.5V to 0.5V only by discharging the bit line from 1V to 0.5V by 0.5V. As a result, the bit line amplitude can be reduced from the conventional 2V to 0.5V, so that the bit line discharge time becomes ¼ that of the conventional one, and the reading speed is increased.

  The precharge transistor TrN2 may be a p-channel transistor, but is preferably an n-channel transistor. This is because when the transistor TrN2 is a p-channel type, it is necessary to wire the sense node Nsense not only to the n-channel transistor region but also to the p-channel transistor region. Since the capacitance of the sense node Nsense is sufficiently small (for example, 1/100) as compared with the bit line capacitance, it is easy to receive coupling noise from adjacent wirings and upper and lower wirings. Therefore, the wiring of the sense node Nsense is short, and stable reading can be performed when there are no other signal lines around. Therefore, when the precharge transistor TrN2 is of a p-channel type, the wiring becomes long and thus it is susceptible to noise. Further, as shown in FIGS. 5 and 2, when the sense system is formed by only n-channel transistors, the layout can be made without providing other wiring around the sense node Nsense. On the other hand, when the p-channel type is used for the transistor TrN2, as can be seen from FIG. 2, the sense node Nsense is an n-channel transistor region (transistors Tr12 and Tr13 and the sense activation signal BLSEN0 constituting the latch circuit LA). , BLSEN1 must pass through the transistors Tr7 and Tr14) supplied to the gates and be input to the precharge transistors Tr10 and Tr11 in the p-channel transistor region, so that noise is easily received. For example, since one of the sense activation signals BLSEN0 and BLSEN1 is activated at the time of sensing, the sense node Nsense receives coupling noise between the signals BLSEN0 and BLSEN1.

  Next, the read operation of the NAND type EEPROM of the present invention will be described in more detail with reference to the timing chart of FIG. In the figure, gnd is a ground potential. FIG. 6 is a timing chart when data is read from the memory cell MCELL16 in the circuit shown in FIG. In the standby state, the signals BLCU0 and BLCU1 are the power supply voltage Vdd, and the bit line is grounded. At time RCLK0, the read booster circuit activation signal LIMVRDn becomes “L” level, and the read booster circuit starts to operate. The VSG booster circuit activation signal LIMVSGn is also set to the “L” level, and the VSG booster circuit starts to operate. Then, VSGHH (about 7V) is generated by the VSG booster circuit.

  In the selected block (for example, block 1 in FIG. 3), the block selection signal RDECI1 becomes the power supply voltage Vdd, and transferG1 becomes a voltage boosted from VreadH of VRDEC (a voltage higher than Vread and about 6V). As a result, the control gates CG1, CG2,... CG16 become the potentials of the signals CGN1, CGN2,. In the non-selected block 2, the block selection signal RDECI2 becomes the ground voltage Vss, and transferG2 becomes the ground voltage Vss. As a result, the control gate of block 2 becomes floating. The selection gate SG3 in the non-selected block 2 is grounded from SGDS. In another non-selected block (not shown) that does not share the drain-side selection gate (SG1 in FIG. 3) with the selected block 1, the two selection gates in the block are both grounded.

  At time RCLK1, SG1, CG1, CG2,... CG15 become Vread (3.5 V). The selected control gate CG16 is 0V. At time RCLK2, the signal BLCLAMP becomes Vclamp (2V), and precharging of the selected bit line BL0 is started. The selected bit line BL0 is precharged to 1V, and the unselected bit line BL1 is grounded via BLCRL. Thus, the channels or drains of the memory cells (for example, MCELL 1, 2, 3,..., 15, 16) of the block selected during the bit line precharge are charged. As described in the prior art, the memory cells of the selected block (for example, MCELL1, MCELL2, MCELL3,..., MCELL15, MCELL16) are charged during this period, and the potentials of CG1, CG2,. Rises. However, since SG2 is a ground potential, no current flows through the memory cell, so that erroneous reading as in the prior art does not occur. At time RCLK3, the signal BLSEN0 becomes the power supply voltage Vcc, and the node N1 of the latch in the circuit shown in FIG. 2 is reset to “L” level and N2 to “H” level.

  After the bit line precharge is completed, the selection gate line SG2 is biased to Vread at time RCLK4, and the bit line discharge is started. As described above, the selection gate line SG1, the control gate lines CG1, CG2,..., CG16 floating during the bit line precharge due to the coupling noise return to the predetermined potential (Vread or 0V) at the time of RCLK4. . As described above, by charging the selection gate line SG1 and the control gate first and raising the selection gate line SG2 after the coupling noise disappears, stable reading without erroneous reading can be performed.

  The reason why the signal BLCLAMP is grounded during the discharge of the bit line is to prevent a leak current from the sense node Nsense to the bit line. During reading, the unselected bit line BL1 is grounded in order to reduce bit line capacitive coupling noise. The reason why the signals BLTR0 and BLCU1 are VSGHH (about 7V) is to reduce the on-resistance of the transistors selected by these signals BLTR0 and BLCU1. Further, the reason why the signal BLTR0 is rising slowly by 1.5 μsec is to prevent the power supply Vdd in the chip from being lowered by gradually precharging the bit line.

  By time RCLK5, the sense node Nsense is charged to the power supply voltage Vcc. At time RCLK6, the signal BLCLAMP becomes 1.5V, so that the sense node Nsense is charged to the power supply voltage Vcc, and at time RCLK6, the signal BLCLAMP becomes 1.5V. As a result, the charge of the sense node Nsense is transferred to the bit line. Thereafter, the signal BLSEN1 becomes “H” level at time RCLK7, whereby the potential of the sense node Nsense is sensed. As a result, if “0” is read (Nsense is “H” level), N2 is “L” level, and if “1” is read (Nsense is “L” level), N2 is “H”. Become a level.

  Thereafter, CSL becomes “H” level at time RCLK8, and latch data is output to IO and IOn. The recovery operation starts from time RCLK9. At time RCLK9, the discharge of the bit line, the control gate, and the selection gate to the ground voltage starts. At time RCLK10, the signals LIMVRDn and LIMVSGn become “H” level, and the booster circuit stops. At time RCLK11, the node in the row decoder is discharged.

  After completion of reading, all the bit lines are grounded by setting both the signals BLCU0 and BLCU1 to the power supply voltage Vdd.

  FIG. 7 is a timing chart of the negative threshold value reading mode. FIG. 7 shows a case where the memory cell MCELL16 of FIG. 3 is selected. In the negative threshold value reading, the signals BLCD, BLSEN0, and BLTR0 are set to the “H” level so that the selected bit line is precharged to 0V and then the source line is set to the power supply voltage Vdd. The selected control gate is set to Vsel, and the non-selected gate is set to Vread (3.5 V). For example, a case where Vsel is 0V will be described. When the memory cell has a negative threshold voltage, the absolute value of the threshold is output to the bit line. Since the potential of the bit line becomes Vsel + | Vth | with respect to a predetermined Vsel, the negative threshold value of the memory cell can be measured by changing Vsel from the outside of the chip. The absolute value of the negative threshold voltage is output to the selected bit line BL0. The unselected bit line BL1 is biased from the BLCRL to the power supply voltage Vcc in order to reduce bit line coupling noise. The signal BLSEN1 becomes “H” level at time RCLK8, whereby the potential of the bit line is sensed.

  In the negative threshold value reading, SG2 is first biased at time RCLK1 and the control gate is biased, and then the selection gate line SG1 is biased to Vread at time RCLK5. This is because the drain or channel of the memory cell is charged from the source line side, contrary to the normal reading in FIG. That is, as shown in FIG. 7, the selection gate line SG2, the control gate lines CG1, CG2,... CG16 floating during the bit line precharge due to the coupling noise are returned to the predetermined potential at the time of RCLK5. As described above, in the negative threshold value reading, the selection gate line SG2 and the control gate are charged first, and after the coupling noise disappears, the selection gate line SG1 is raised to perform stable reading without erroneous reading. Can do. Since the negative threshold voltage can be measured by using the method of FIG. 7, it can also be used in the erase verify mode for checking whether or not the erase is sufficiently performed.

  FIG. 8 is a timing chart showing the write operation. FIG. 8 shows the case where the memory cell MCELL16 is selected. When writing is performed, the node LA of the latch LA in FIG. 2 is at the “L” level. When writing is not performed, the node LA of the latch LA in FIG. 2 is at the “H” level. The write data is transferred to the selected bit line BL0 by setting the signal BCLD to Vsg (4V). In the case of “0” writing, the memory cell is set to 0 V from the bit line and writing is performed. In the case of “1” writing, the bit line is set to the power supply voltage Vdd. As shown by the solid line in FIG. 8, the power supply voltage Vdd may be transferred from the bit line to the “1” write channel by setting the selection gate line SG1 to Vsg and the control gate line to Vread (4.5V). Alternatively, the control gate line may be biased from 0V as indicated by the dotted line in FIG. After bit line charging, from time PCLK4, the selection control gate line CG16 is set to Vpgm (20V), and the non-selection control gate lines CG1, CG2,... CG15 are set to Vpass (10V). In the case of “0” writing, electrons are injected from the 0V channel into the floating gate. In the case of “1” writing, the selection gate TrSG1 is turned off, so that the channel rises to about 8 V due to capacitive coupling with the control gate. As a result, the memory cell in which “1” is written does not inject electrons.

  In FIG. 8, the memory cell connected to the unselected bit line BL1 is unselected for writing when the bit line BL1 is set from BLCRL to the power supply voltage Vcc. In FIG. 8, the reason why BLTR0 and BLCU1 are rising slowly by 1.5 μs is to prevent the power supply Vdd in the chip from being lowered by gradually charging the bit lines.

  FIG. 9 shows another writing method. In FIG. 9, by setting the source line and the selection gate line SG2 to 4.5V, a potential (about 3.5V) higher than the power supply voltage Vdd is transferred from the source line to the memory cell. The source line potential is applied to all the memory cells in the selected block.

  The operation timing can be variously modified. The control gate may be raised from 0 V at time PCLK4 as indicated by the solid line in FIG. Alternatively, a high potential of about 3.5 V may be transferred from the source to the “1” write channel by setting the control gate to Vread (4.5 V) as shown in FIG. By transferring a potential higher than the power supply voltage Vdd from the source line to the memory cell as shown in FIG. 9, the channel potential of the “1” -written memory cell can be increased, and the writing characteristics can be improved.

  The channel of the memory cell is boosted to about 9 V by capacitive coupling with the control gate, and then the selection gate line SG1 becomes the power supply voltage Vdd at time PCLK6, whereby the write data of the bit line is transferred. That is, the channel of the memory cell connected to the non-selected bit line BL1 and the channel of the memory cell to which “1” is written are maintained at 9V, and the channel of the memory cell to which “0” is written is discharged to 0V.

  FIG. 10 shows a timing diagram of the write verify read. The write data is set in the latch of FIG. 2. When “1” is written (when writing is not selected), the node N1 of the latch LA in FIG. 2 is at “H” level, and when “0” is written (when writing is selected). The node N1 is at the “L” level. The write verify mode is almost the same as the read in FIG. The difference is that the selected control gate CG16 is set to the verify voltage Vvrfy (0.5V) instead of 0V, and the reset operation of the latch LA of the sense amplifier (the signal BLSEN0 is “H” at time RCLK4 in FIG. 7). There is no action to become a level. As a result of the verify reading, when “0” writing is insufficient, the node N1 of the latch becomes “L” level and rewriting is performed. When “0” writing is sufficient and “1” writing is performed, N1 becomes “H” level and writing is not performed. Detection of whether or not writing has been sufficiently performed in all columns is performed as follows. First, after precharging the signal FLAG to the power supply voltage Vcc, the signal VERIFY is set to the “H” level at time RCLK8. As a result, if even one column has insufficient writing, the signal FLAG becomes the ground voltage Vss, and it is detected that there is an insufficient writing column.

  After programming, over program verify read may be performed. FIG. 11 is a timing diagram. In the over program verify read, it is detected whether or not memory cells are excessively written. That is, the control gate lines CG1, CG2,... CG16 are set to Vread for reading. Vread is 2.8V. As a result, it is detected whether or not the threshold voltage of the memory cell selected by the control gate lines CG1, CG2,... CG16 is 2.8V or higher. The reason why Vread is set lower than 3.5 V during normal reading is to provide a margin for power supply voltage fluctuation, temperature fluctuation, processing variation, and the like. Whether there is an excessively written memory cell somewhere in all the columns is detected by the signal VERIFY becoming “H” level at time RCLK8.

  FIG. 12 is a timing chart of erase verify read. Reading is performed by setting the control gate lines CG1, CG2,..., CG16 to 0V. As a result, it is detected whether the threshold voltage of the memory cell selected by the control gate lines CG1, CG2,... CG16 is 0 V or higher. Further, in order to provide a margin for power supply voltage fluctuation, temperature fluctuation, processing fluctuation, etc., the bit line precharge potential is increased from 1V to 1.3V of the lead, and further, the bit line discharge time (from time RCLK4 to time RCLK5 in FIG. 12). Time) is shorter than lead. Whether there is an insufficiently erased memory cell somewhere in all the columns is detected by the signal VERIFY becoming “H” level at time RCLK8.

  In the above-described embodiment, the NAND type EEPROM has been described as an example. However, the present invention is a NOR type, an AND type (A. Nozoe: ISSCC, Digest of Technical Papers, 1995), a DINOR type (S. Kobayashi: ISSCC). , Digest of Technical Papers, 1995), NAND type, Virtual Ground Array type (Lee, et al .: Symposium on VLSI Circuits, Digest of Technical Paper), etc. However, it is not limited to mask ROM, EPROM, or the like.

  2 and 5, a capacitor (transistor) TrN4 is connected to the sense node Nsense in order to reduce capacitive coupling noise from surrounding wiring and the like with respect to the sense node Nsense. Of course, when a desired capacitance can be obtained by the wiring capacitance of the sense node Nsense, the capacitance TrN4 is not necessary.

  Next, a voltage bias circuit used in the semiconductor memory device according to the embodiment of the present invention will be described.

  FIG. 13 shows a voltage bias circuit used in the semiconductor memory device according to the embodiment of the present invention. This voltage bias circuit includes transistors Q11 to Q19 and capacitors CB2 and CB3. The current path of transistor Q11 is connected between power supply Vcc and node Na. One end of the current path of the transistor Q12 is connected to the power supply Vcc, and the gate is connected to the gate of the transistor Q11. One end and gate of the current path of the transistor Q13 are connected to the other end of the current path of the transistor Q12, and the other end of the current path is connected to the gate of the transistor Q11. One electrode of the capacitor CB2 is connected to the connection point of the current paths of the transistors Q12 and Q13, and the clock signal CLK1 is supplied to the other electrode of the capacitor CB2. One end of the current path of the transistor Q14 is connected to the gate of the transistor Q11, the gate is grounded, and the voltage V1 is applied to the other end of the current path. This circuit unit constitutes a high voltage switch SW2.

  The current path of transistor Q16 is connected between high voltage VH and node Na. One end of the current path of the transistor Q17 is connected to the high voltage VH, and the gate is connected to the gate of the transistor Q16. One end and gate of the current path of the transistor Q18 are connected to the other end of the current path of the transistor Q17, and the other end of the current path is connected to the gate of the transistor Q16. One electrode of the capacitor CB3 is connected to the connection point of the current paths of the transistors Q17 and Q18, and the clock signal CLK2 is supplied to the other electrode of the capacitor CB3. One end of the current path of the transistor Q19 is connected to the gate of the transistor Q16, the gate is grounded, and the voltage V2 is applied to the other end of the current path. This circuit portion constitutes a high voltage switch SW3.

  The current path of the transistor Q15 is connected between the node Na and the ground point, and the voltage V3 is applied to the gate of the transistor Q15.

  In the above configuration, when the node Na is grounded, the voltage V3 may be set to the power supply voltage Vcc, and the voltages V1 and V2 may be set to the ground voltage Vss. When the voltages V1 and V3 are set to the ground voltage Vss and the voltage V2 is set to the power supply voltage Vcc and the clock signal CLK2 is applied to the capacitor CB3, the high voltage VH is applied to the node Na via the high voltage switch SW1. When voltage V1 is set to power supply voltage Vcc, voltages V2 and V3 are set to ground voltage Vss, and clock signal CLK1 is applied to capacitor CB2, node Na is biased to power supply voltage Vcc. Even when the node Na is discharged from the high voltage VH to the power supply voltage Vcc, the clock signal CLK1 may be applied with the voltage V1 set to the power supply voltage Vcc and the voltages V2 and V3 set to the ground voltage Vss. In FIG. 13, Vcc may be an on-chip power supply voltage that is stepped down from an external power supply voltage.

  As described above, according to the voltage bias circuit described above, a high-speed bias circuit with low current consumption can be realized.

  As shown in FIG. 23, when the node Na is biased to the power supply voltage Vcc through the high voltage switch SW1, the clock signal CLK1 is input and the capacitor CB1 is continuously driven. Since the current consumption when driving this capacitor is about 50 μA, it is negligibly small compared to the current of the entire chip (about 10 mA) consumed during operations such as reading and writing. Also, a circuit (ring oscillator or the like) that generates a clock consumes current. However, since it is necessary to reduce the current consumed by the entire chip to about 5 μA in the standby state (standby state), it is not desirable to operate the high voltage switch circuit during standby. The circuit shown in FIG. 14 solves this problem.

  In FIG. 14, a path via a p-channel transistor is added as a charging path for the power supply voltage Vcc. That is, the current paths of the transistors Q20 and Q21 are connected in series between the power supply Vcc and the node Na, the voltage V4 is supplied to the gate of the transistor Q20 via the inverter INV2, and the voltage V4 is supplied to the gate of the transistor Q21. Like to do. Since the other configuration is the same as that of the circuit shown in FIG. 13, the same components are denoted by the same reference numerals and detailed description thereof is omitted.

  In the above configuration, during standby, the node Na can be charged to the power supply voltage Vcc via the transistors Q20 and Q21 by setting the voltages V1, V2 and V3 to the ground voltage Vss and the voltage V4 to the power supply voltage Vcc. Since the transistor Q21 does not consume current after the node Na becomes the power supply voltage Vcc, the standby current can be reduced. In FIG. 14, when the node Na is grounded, the voltage V3 may be set to the power supply voltage Vcc, and the voltages V1, V2, and V4 may be set to the ground voltage Vss. When the clock signal CLK2 is applied to the capacitor CB3 with the voltages V1, V3, V4 as the ground voltage Vss and the voltage V2 as the power supply voltage Vcc, the high voltage VH is applied to the node Na via the high voltage switch SW3. When discharging the node Na from the high voltage VH to the power supply voltage Vcc, the voltage V1 is set to the power supply voltage Vcc, the voltages V2, V3, and V4 are set to the ground voltage Vss, and the clock signal CLK1 may be applied to the capacitor CB2. Further, when the power supply voltage Vcc is applied to the node Na during operations such as reading, writing, and erasing other than the standby time, the voltage V1 may be set to the power supply voltage Vcc and charged via the high voltage switch SW2. V4 may be set to the power supply voltage Vcc and charged via the transistor Q20, or both the voltages V1 and V4 may be set to the power supply voltage Vcc. Thus, according to the present invention, it is possible to realize a bias circuit which is high speed and consumes less current during standby.

  FIG. 15 is a block diagram illustrating a configuration example of a NAND cell type EEPROM for explaining a semiconductor memory device to which the voltage bias circuit described above is applied. This NAND cell type EEPROM includes memory cell arrays 1A and 1B, a sense amplifier / data latch 2 for writing and reading data, row decoders 3A and 3B for selecting word lines, a column decoder 4 for selecting bit lines, and an address buffer. 5, an I / O sense amplifier 6, a data output buffer 7, a substrate potential control circuit 8, bit line precharge circuits 9A and 9B, a step-down circuit 10 and the like. This NAND-type EEPROM is an open bit line system, and the memory cell arrays 1A and 1B are divided into two, and row decoders 3A and 3B and bit line precharge circuits 9A and 9B are provided corresponding to them. Also, two types of pads PD1 and PD2 that receive the external power supply voltage Vcc are provided, and the power supply voltage Vcc1 applied to the pad PD1 is stepped down by the step-down circuit 10 to generate the in-chip power supply voltage Vdd. The data latch 2, the row decoders 3A and 3B, the column decoder 4, the address buffer 5, and the I / O sense amplifier 6 are supplied as power sources, respectively. Further, the external power supply voltage Vcc2 supplied to the pad PD2 is supplied as a power source to the data output buffer 7, the substrate potential control circuit 8, and the bit line precharge circuits 9A and 9B. Vcc1 and Vcc2 become a common terminal Vcc outside the chip.

  FIG. 16 is a circuit diagram showing a configuration example of the memory cell array 1A in the circuit shown in FIG. As shown in the figure, NAND cells are arranged in a matrix, the first selection transistors of each NAND cell are connected to bit lines BL0A, BL1A, BL2A, BL3A, BL4A,..., And the second selection transistors are source lines. It is connected to the. The source line is commonly connected to a reference potential wiring. The first and second selection gates in each NAND cell MC are provided with selection gate lines SG1, SG2 arranged in a direction intersecting with the bit lines BL0A, BL1A, BL2A, BL3A, BL4A,. The control gate lines CG1 to CG8 arranged in parallel with the selection gate lines SG1 and SG2 are connected to the control gates of the memory cells in each NAND cell for each row (or column). ing.

  Various variations are conceivable for the configuration of the memory cell section, and NOR type flash memory, AND type EEPROM (H. Kume et al .; IEDM Tech. Dig., Dec. 1992, pp. 991-993), DINOR It may be a mold. Further, not only the EEPROM but also a so-called EPROM or mask ROM is effective.

  FIG. 17 is a circuit diagram showing a configuration example of the sense amplifier / data latch circuit 2 to which the bit lines BL2A and BL3A in FIG. 16 are connected. SS3A and SS4A in FIG. 17 are biased by the voltage bias circuit shown in FIG. In this case, however, what is indicated as Vcc in FIG. 14 is the step-down power supply Vdd in the chip. In other words, SS3A and SS4A are charged to the power supply voltage Vdd via the p-channel transistors Tr20 and Tr21 of FIG. 14 during standby.

  FIG. 18 shows a configuration example of the bit line precharge circuits 9A and 9B in the circuit shown in FIG. This circuit has an inverter circuit configuration that operates with a power supply voltage Vcc2, and inverts an input signal PREA to generate a signal BLPREA.

  Next, a writing procedure when writing to the memory cell MC1 in the circuit shown in FIG. 16 will be described below. FIG. 19 is a timing chart of this write operation. As shown in FIG. 17, in this embodiment, two bit lines are shared by one sense amplifier. Accordingly, one bit line is selected from the two bit lines. For example, when writing to MC1, the memory cells MC2 and MC3 in FIG. 16 are unselected for writing. Write data in the memory cell MC1 is supplied from the bit line BL2A, and a write non-selection potential is applied to the memory cells MC2 and MC3 from the bit lines BL1A and BL3A.

  Data written to the memory cell MC1 in FIG. 16 is latched in the sense amplifier circuit (SA1 in FIG. 17). That is, in the case of “0” writing, the node N1 is 0V, N2 is Vdd, in the case of “1” writing, the node N1 is Vdd, and N2 is 0V.

  When the write operation is started, SS3A is first set to VH at time t1. VH may be, for example, 6V so that the bit lines BL3A and BL1A can be charged to the power supply voltage Vdd (for example, 2.5V). On the other hand, the bit line precharge activation signal PREA becomes “L” level, and the signal BLPREA is charged to the power supply voltage Vdd. As a result, the bit lines BL1A and BL3A are charged to the power supply voltage Vdd. The bit line BL2A is set reflecting the write data of the sense amplifier SA1. In the case of writing “0”, BL2A is set to 0V. In the case of writing “1”, the bit line BL2A is charged to the power supply voltage Vdd.

  At time t2, the control gates CG1, CG2,. As a result of boosting the selected control gate CG1 to Vpgm (about 20V) and the non-selected control gates CG2, CG3,... CG8 to Vpass (about 10V), the memory cell MC1 for writing “1” and the unselected memory for writing Since the channels of the cells MC2 and MC3 are at an intermediate potential (about 8V) and the control gate CG1 is Vpp (about 20V), these memory cells are not written, but the channel of the memory cell for writing “0” is 0V, and the control gate is Since it is Vpp (about 20V), electrons are injected from the substrate to the floating gate and "0" is written. After the completion of writing, SS3A is charged from the high voltage VH to the power supply voltage Vdd via the high voltage switch 2 of FIG. SS4A may be charged to the power supply voltage Vdd via the p-channel transistor of FIG. 14, or may be charged to the power supply voltage Vdd via the high voltage switch SW2. In the standby state after the end of writing, the node Na is biased to the power supply voltage Vdd by setting the voltages V1, V2, and V3 of FIG. 14 to the ground voltage Vss and the voltage V4 to the power supply voltage Vdd. The reason why SS3A and SS4A are set to the power supply voltage Vdd at the time of standby is to ground the bit line to 0V via the signal BLPREA even in the standby state after completion of writing. It is preferable to ground the bit line during standby (standby) for the following reason. The bit line to which the read data is output needs to be grounded to 0V before performing the read operation. For example, when reading is performed immediately after the end of writing, there is a possibility of erroneous reading if charge remains on the bit line. In the method of grounding SS3A and SS4A to 0V during standby, writing must be completed after a sufficient time has elapsed until the bit line is discharged to 0V, which increases the writing time. Alternatively, since it is necessary to discharge the bit line after the read command is input, the read time increases. In the method of grounding the bit line by setting the power supply voltage Vdd at SS3A and SS4A during standby as in the present invention, for example, the bit line can be grounded while a read command is input. Can be shortened.

1 is a block diagram illustrating a schematic configuration of a NAND cell type EEPROM for explaining a semiconductor memory device according to an embodiment of the present invention; FIG. FIG. 2 is a circuit diagram showing a configuration example of a sense amplifier / data latch circuit in the circuit shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration example of a row decoder in the circuit shown in FIG. 1. FIG. 2 is a cross-sectional view schematically showing a well configuration of the NAND type EEPROM shown in FIG. 1. FIG. 4 is a diagram for explaining a read operation of the NAND type EEPROM shown in FIGS. 1 to 4, in which (a) shows a bit line precharge, (b) shows a bit line discharge, and (c) shows “1”. At the time of reading, (d) is a diagram for explaining the potential application relationship at the time of “0” reading. FIG. 5 is a timing chart for explaining a read operation of the NAND type EEPROM. The timing diagram for demonstrating the negative threshold value reading mode of the said NAND type EEPROM. 4 is a timing chart for explaining a write operation of the NAND type EEPROM. FIG. The timing diagram for demonstrating another write-in operation | movement of the said NAND type EEPROM. FIG. 4 is a timing chart for explaining a write verify mode of the NAND type EEPROM. FIG. 6 is a timing chart for explaining an over program verify read operation of the NAND type EEPROM. FIG. 4 is a timing chart for explaining an erase verify read operation of the NAND type EEPROM. 1 is a diagram showing a voltage bias circuit used in a semiconductor memory device according to an embodiment of the present invention. FIG. 10 is a diagram showing another voltage bias circuit used in the semiconductor memory device according to the embodiment of the present invention. FIG. 15 is a block diagram illustrating a configuration example of a NAND cell type EEPROM for explaining a semiconductor memory device to which the voltage bias circuit shown in FIG. 14 is applied. FIG. 16 is a circuit diagram showing a configuration example of a memory cell array in the circuit shown in FIG. 15. FIG. 17 is a diagram showing a configuration example of a sense amplifier / data latch circuit to which the bit line in FIG. 16 is connected. FIG. 16 is a diagram showing a bit line precharge circuit in the circuit shown in FIG. 15. FIG. 17 is a timing chart showing a write procedure when writing to the memory cell of FIG. 16. 2A and 2B are diagrams for explaining a conventional semiconductor memory device, in which FIG. 1A is a pattern plan view of one NAND cell portion of a memory cell array in a NAND type EEPROM, and FIG. 2B is an equivalent circuit diagram thereof. It is sectional drawing of the pattern shown to Fig.20 (a), (a) A figure is A-A 'line, (b) A figure is sectional drawing along a B-B' line. FIG. 22 is an equivalent circuit diagram of a memory cell array in which the NAND cells shown in FIGS. 20 and 21 are arranged in a matrix. The circuit diagram which shows the conventional voltage bias circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1A, 1B ... Memory cell array, 2 ... Sense amplifier and latch circuit, 3, 3A, 3B ... Row decoder, 4 ... Column decoder, 5 ... Address buffer, 6 ... I / O sense amplifier, 7 ... Data output buffer, 8 ... substrate potential control circuit, 9A, 9B ... bit line precharge circuit, 10 ... step-down circuit, Q11-Q19 ... transistor, CB2, CB3 ... capacitor, SW2, SW3 ... high voltage switch.

Claims (2)

A memory cell portion including at least one memory cell;
A first select transistor connecting the memory cell portion and a source line;
A second select transistor connecting the memory cell portion and the bit line;
A sense amplifier connected to the bit line and reading the data of the memory cell by detecting a potential of the bit line;
The bit line connected to the bit line and not connected to the write circuit at the time of writing is connected to the stepped down power supply voltage in the chip by turning on the boosted power supply voltage supplied to the gate, and after the end of writing and a third transistor for grounding the bit lines by the step-down power supply voltage within the chip during standby is supplied to turn on the gate,
In a read operation in which current flows from the bit line to the source line through the memory cell unit,
A predetermined voltage is applied to the gate of the second selection transistor so that the second selection transistor is turned on, a predetermined voltage is applied to the gate of the memory cell, and the gate voltage of the memory cell is The first selection transistor is turned on after the voltage reaches a predetermined voltage and the voltage that has fluctuated due to capacitive coupling noise between the channel and the gate of the memory cell returns to the predetermined voltage. A semiconductor memory device, wherein a predetermined voltage is applied to the gate of the select transistor. A memory cell unit including a plurality of memory cells connected in series with each other;
A first select transistor connecting the memory cell portion and a source line;
A second select transistor connecting the memory cell portion and the bit line;
A sense amplifier connected to the bit line and reading the data of the memory cell by detecting a potential of the bit line;
The bit line connected to the bit line and not connected to the write circuit at the time of writing is connected to the stepped down power supply voltage in the chip by turning on the boosted power supply voltage supplied to the gate, and after the end of writing and a third transistor for grounding the bit lines by the step-down power supply voltage within the chip during standby is supplied to turn on the gate,
In a read operation in which current flows from the bit line to the source line through the memory cell unit,
A predetermined voltage is applied to the gate of the second select transistor so that the second select transistor is turned on, a read voltage is applied to the selected memory cell of the memory cell unit, and the memory cell unit A predetermined voltage is applied to the gate of the non-selected memory cell so that the non-selected memory cell of the non-selected memory cell is turned on, the gate voltage of the non-selected memory cell reaches a predetermined voltage, and the channel of the non-selected memory cell A predetermined voltage is applied to the gate of the first selection transistor so that the first selection transistor is turned on after the voltage that has fluctuated due to capacitive coupling noise between the gate and the gate returns to the predetermined voltage. A semiconductor memory device.

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