JPH0281398A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make non-volatile holding data and to reduce the number of the times of rewriting for EEPROM by executing the memory access for a RAM in an ordinary action condition and transferring mutually data between the RAM and a non-volatile memory circuit as needed. CONSTITUTION:A non-volatile memory circuit to be able to electrically write and erase and a RAM having the same memory capacity are provided, a memory access is executed for the RAM in the ordinary action condition and data are mutually transferred between the RAM and the non-volatile memory circuit in accordance with the non-volatile operation of information. Namely, the access to rewrite the holding data is executed for the RAM, a high speed action is executed and as needed, data are transferred between the RAM and the EEPROM. Thus, the non-volatile operation of the holding data are carried out and the number of the times of rewriting for EEPROM can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and relates to a technique that is effective for use in, for example, a nonvolatile memory device.

[Conventional technology]

Electrically rewritable EEPROMs (Electrically Erasable and Programmable Read Only Memories) are known. This is E E P RO
Regarding M, for example - Ohmsha December 25, 1985
Japanese publication r microcomputer handpunk J page 264
, pages 266 and 588.

[Problem to be solved by the invention]

In the EEFROM as described above, it is necessary to spend a relatively long time of several tens of milliseconds for a unit write operation. In contrast, ordinary RAM (random access memory)
Then, several hundred n3 is sufficient for a unit of data write operation. Therefore, the writing time of the EEFROM as described above is extremely long for microcomputer systems and the like.

Furthermore, since EEPROMs are guaranteed to be written (rewritten) only tens of thousands of times, there remains a problem in terms of durability.

An object of the present invention is to provide a semiconductor memory device that achieves nonvolatile information, high-speed writing, and improved durability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

Representative inventions w1 among the inventions disclosed in this application
A simple explanation of the baby is as follows.

In other words, it is equipped with a nonvolatile memory circuit that can be electrically written and erased, and a RAM that has the same storage capacity. Under normal operating conditions, memory access is performed to the RAM, and as information becomes nonvolatile, the RAM is Data is mutually transferred between the nonvolatile memory circuit and the nonvolatile memory circuit.

[For production]

According to the above-mentioned means, access for rewriting the retained data is made to the RAM to achieve high-speed operation, and data is transferred between the RAM and the EEPROM as necessary, thereby rewriting the retained data. Non-volatileization and E
The number of times the EPROM is rewritten can be reduced.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a semiconductor memory device according to the present invention. Each circuit plotter shown in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The semiconductor memory device of this embodiment includes RAM and EEPROM.
It is equipped with The RAM is not particularly limited, but may be a static type RAM or a dynamic type RAM as described below.

The RAM and EEPROM are made to have the same storage capacity.

Although not particularly limited, the semiconductor memory device of this example includes:
As mentioned above, it is equipped with RAM and EEFROM, but
Only the RAM can be accessed from the outside, and direct access to the EEFROM from the outside is not possible. Therefore, the address signal ADD supplied from the outside is supplied only to the RAM, and the data terminal DAT is provided only to the RAM. Therefore, writing or reading from the RAM is performed by the address signal ADD, the chip selection signal C8, and the write enable signal WE supplied to the control circuit C0NT.

In this embodiment, EEFROM is used to make information non-volatile.
is provided. This EEFROM is connected to the control circuit C0
Access is performed by NT and address generation circuit ADC. That is, the address signal generated by the address generation circuit ADC is
(Word) system address terminals are supplied to the DSA. Therefore, the address input circuit of the RAM has a multiplexer function to switch and take in the X-system address signal supplied from the outside and the X-system address signal for data transfer according to the operation mode. Although not particularly limited, in order to transfer data between the RAM and the EEPROM at high speed, a latch circuit FF is provided to transmit information between the data line of the RAM and the data line of the EEPROM. This allows data transfer to be performed in units of word lines.

For example, in the initial state, memory access is performed to RAM. When the power is cut off, the control signal DS is set to low level to specify the data transfer mode, and the write enable signal WE is set to low level, the control circuit C
0NT determines that data is to be transferred from RAM to EEFROM, controls the address generation circuit ADC, and transfers data between RAM and EEPROM.
The corresponding word line of the ROM is placed in a selected state. After that, the latch circuit is activated, the data on the RAM side is taken in, and it is transmitted to the EEFROM side to instruct a write operation.The EEFROM side performs writing in word line units based on the data held in the rough child circuit FF. be exposed.

Thereafter, after the address switching operation of the address generation circuit ADC is repeated and the above-mentioned operation is repeated to perform the above-mentioned data transfer for all word lines, in other words, after all the data in the RAM has been transferred to the EEFROM, the power supply is turned off. to block it.

When the control signal DS is set to low level and the write enable signal WE is set to high level when the power is turned on again, the control circuit C
0NT determines that data is to be transferred to the EEPROM, controls the address generation circuit ADC, and selects the corresponding word line of the RAM and EEPROM. After that, the latch circuit is activated, data from the EEFROM is loaded,
When you convey this to the RAM side and instruct the write operation, the RAM
In M(l!1), writing is performed in units of word lines based on the data held in the latch circuit FF. After that, the address switching operation of the address generation circuit ADC is performed, and the same operation as described above is repeated to write data for all word lines. After the above data transfer, in other words, the EE
After all the data in the FROM is transferred to the RAM and the retained data is restored to the state before the power was shut off, memory access to the RAM is permitted. That is, while the address generation circuit ADC is in operation, the busy signal BSY is set to a low level to prohibit external access to the RAM.

FIG. 2 shows a circuit diagram of a specific embodiment of the main part of the RAM section. The RAM shown in the figure is formed on a single semiconductor substrate made of single-crystal silicon along with an EEFROM to be described later using the well-known CMO3 integrated circuit technology. Each MO3FET is manufactured by the so-called self-line technology using a gate electrode made of polysilicon as a kind of impurity introduction mask. In the same figure, the P-channel MO3FET is indicated by an arrow added to the channel portion of the N-channel MO3FET.
Distinguished from O3FET.

The N-channel MO3FET shown in the figure is formed on a P-type middle L region formed on an N-type semiconductor substrate. The P-channel portion S FET is formed on an N-type semiconductor substrate. The P-type well region as the substrate gate of the N-channel MO3FET is coupled to the ground terminal of the circuit, and the N-type well region as the common substrate gate of the P-channel MO3FET is coupled to the ground terminal of the circuit.
The type semiconductor substrate is coupled to a power terminal of the circuit. In addition,
N-channel portion that constitutes a memory cell S FET
The structure in which the information is formed in the well region is effective in preventing erroneous inversion of information stored in the memory cell caused by α rays or the like. Further, the above configuration corresponds to the fact that the MNOS (MNOS) transistor constituting the EEFROM, which will be described later, is also formed from the same P-type well region as described above.

The memory array includes a plurality of memory cells MC arranged in a matrix as a representative example, word lines WO to Wn made of polysilicon layers, complementary data lines (bit lines or digit lines) Do, no to DI,
It consists of DI. Each of the memory cells MC had the same configuration as each other, with the gate and drain cross-wired to each other and the source coupled to the ground point of the circuit, as shown in one specific circuit as a representative. Memory MO3FETQI, Q2 and the above MO3FETQI
, Q2 (7) l' A high resistance R1 made of a polysilicon layer provided between the lay 7 and the power supply terminal Vcc.
, R2. A transmission gate MO8FETQ3Q4 is provided between the common connection point of the MO3FETQI and Q2 and the complementary data lines Do and DO. Transmission gate MO3FETQ3 of memory cells arranged in the same row.
The gates of Q4 and the like are commonly connected to the corresponding word lines WO and the like shown by way of example, and the input/output terminals of the memory cells arranged in the same column are connected to the corresponding pair of word lines shown by way of example. Complementary data (or bit) lines DO, Do
and is connected to DI, Dl, etc.

In the memory cell MC, MO3FETQ1, Q2
The memory circuit consisting of the resistors R1 and R2 constitutes a type of flip-flop circuit, but the operating point in the information retention state is quite different from that of a flip-flop circuit in the ordinary sense. That is, in order to reduce power consumption in the memory cell MC, its resistance R1 is
MO3 when MO3FETQ1 is turned off
The resistance value is set to be extremely high enough to maintain the gate voltage of FET Q2 at a voltage slightly higher than its threshold voltage. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistors R1 and R2 are MO3FETQ1
．． , Q2 have a high resistance enough to compensate for the drain leakage current. The resistors R1 and R2 have enough current supply capability to prevent information charges stored in the gate capacitance (not shown) of the MO3FET Q2 from being discharged.

According to this embodiment, although the semiconductor memory device is manufactured by CMOSIC technology, the memory cell MC is composed of an N-channel inter-O3 FET and a polysilicon resistance element as described above. The memory cell MC of this embodiment can have a smaller size (occupied area) than when a P-channel MO3FET is used in place of the polysilicon resistance element. That is, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the drive MOS FET Q1 or Q2, and the size of the resistor itself can be reduced. And P channel MO3FE
Like the memory cell MC2 using T, the driving MO3FE
Since it is not necessary to separate it from TQI and Q2 by a relatively large distance, no wasted blank space is generated.

As a result, the area occupied by the static RAM made up of the memory cells MC can be made relatively small.

Note that instead of the memory cell MC as described above, CMOS
Needless to say, a latch circuit having a configuration in which the input and output of the inverter circuit are cross-connected may be used.

Word lines WO and Wn are brought into a selected state by x address decoder XDCR. The X address decoder XDCR decodes the X address signal ADD or ADA to form a selection signal for one word line. In this embodiment, the manual section of the X address decoder XDCR switches between the address signal ADD for normal memory access as described above and the address signal DSA for mutual data transfer between the RAM and the EEPROM as described below. It should be understood that a multiplexer, not shown, is provided. Instead of this configuration,
An address input circuit (not shown) may have a multiplexer function as described above.

A pair of complementary data lines Do, D in the memory array
O, DI, and Di are transmission gates MO3FETQ5.0 and DI, respectively, for data line selection. Q6 and Q7. It is connected to common complementary data lines CD, CD via a column switch circuit composed of Q8. This common complementary data line C
D and CD are connected to an input terminal of an output circuit for reading and an output terminal of an input circuit for writing, which constitute the input/output circuit 10B.

MOS FETQ5 that constitutes the column switch circuit,
Q6 and Q7. The gate of Q8 receives selection signals YO and Y, which are respectively formed by Y address decoder YDCR.
l is supplied. This Y address decoder YDCR is
The column selection signal is formed by decoding the address signal ADD supplied from the outside of the Y system for memory access.

In this embodiment, RAM and EE as described below are used.
In order to transfer data to and from the PROM at high speed, each pair of complementary data lines DO, DO and Dl, Di is provided with a latch circuit FF which also serves as an amplifier circuit as described below.

P-channel MO8FETQI O,Ql 2 and N-channel MO3FETQI1. A pair of CMOS inverter circuits each configured with Ql3 have their inputs and outputs cross-connected to form a latch configuration. A pair of input/output terminals of this unit latch circuit are coupled to the complementary data lines Do, DO via switches MO3FETQ22, Q23 forming a transfer gate. The latch circuit of this unit is a P-channel MO3 which receives complementary operation control signals (latch circuit activation pulses) FFE and FFE, respectively.
Power supply voltage Vcc and the ground potential of the circuit are supplied through FETQI4 and N-channel MO3FETQ15. Switches M similar to the above are also applied to other complementary data lines DI, D1, etc.
O3FETQ24. MOSFET Q16 through Q25
A unit latch circuit constituted by Q21 is provided. Switch MO3FETQ2 as the above transfer gate
A control signal RAM5 for selecting the RAM side is supplied to the gates of Q2 to Q25. The above operation control signals FFE, FF
E and RAM5 are formed by the control circuit C0NT as described above. Although not shown, the complementary data lines Do, Do, Di, Dl, etc. are equipped with a load MOS F E
Appropriate loading means such as T are provided.

As a result, under normal operating conditions, the state/7 type RAM
Similarly, writing/reading is performed through the input/output circuit 10B by address designation and a combination of control signals C8 and WE.

As mentioned above, in order to make the information non-volatile, etc.

When data on the RAM side is taken into the child circuit FF, one word line WO or the like is selected and the storage information of the selected memory cell is transmitted to the complementary data lines D0, Do to DI, Di. In this state, the switches MO3FETs Q22 to Q25 are turned on, and the complementary operation control signal FFE is set to low level and FFE is set to high level, thereby activating the latch circuit that also serves as an amplifier circuit. Thereby, the latch circuit FF amplifies the stored information of the memory cell corresponding to the word line WO and holds it. The information taken into this latch circuit FF is transmitted to the switch MO3FETQ26 . The signal is transmitted to the data line of the EEPROM as described below via Q27 and the like.

FIG. 3 shows a circuit diagram of a main part of an embodiment of the above-mentioned EEPROM. Although the circuit symbols attached to each circuit element in the figure partially overlap with those in FIG. 2, it should be understood that they are completely different.

Although not particularly limited, the EEPROM can be connected to a relatively low power supply voltage Vcc such as +5■ supplied from the outside, and -1
It is operated by a high negative voltage -vpp, such as 2V. X-address decoder X-D that constitutes the X-system selection circuit
CR etc. are constructed by 0M03 circuit. The 0M03 circuit operates by being supplied with a relatively low power supply voltage Vcc such as +5V. Therefore, the selection/non-selection signal level formed by the address decoder X-DCR is set to s'+5'J, and the low level is set to Ov, which is the ground potential of the circuit.

Although the element structure itself constituting the illustrated EEFROM is not shown because it is not directly related to the present invention, its outline is as follows.

That is, like the static RAM, it is formed on a semiconductor substrate made of N-type single crystal silicon.

The MNOS transistor is of an N-channel type, and is formed on a P-type well region formed on the surface of the semiconductor substrate. An N-channel MOSFET is similarly formed on the P-type well region. P channel type MO
A 3FET is formed on the semiconductor substrate.

One memory cell can be one MN, although it is not particularly limited.
O3I - transistor and two M connected in series with it
It is composed of OSFET. In one memory cell, one MNO3I-transistor and two MOS F
The ET has a so-called stacked gate structure in which, for example, a part of the gate electrode of each of the two MOS FETs is overlapping with respect to the gate electrode of the MNOS transistor. As a result, the size of the memory cell is reduced to one MNOS transistor and two
The two MOS FETs are substantially integrated into one structure, resulting in miniaturization.

Although not particularly limited, each memory cell is formed in a common well region. N-channel MOSFETs for constructing the 0M03 circuit, such as the X-decoder, are formed in P-type well regions that are made independent of the common P-type well region for each memory cell.

In this structure, the N-type semiconductor substrate constitutes a common base gate for a plurality of P-channel MOSFE''F formed thereon, and is set to the circuit power supply voltage Vcc level.A CMO3 circuit is constituted. The well region as the substrate gate of N-channel MO3FET for
The circuit ground potential is maintained at O volts.

The memory array includes a plurality of memory cells arranged in a matrix. One memory cell includes an MNOS) transistor Q2, an address selection MOS FETQl provided between its drain and data vA (bit line or digit line) Dl, and, although not particularly limited, the above-mentioned MNO3) transistor Q2. The isolation MO3FET Q3 is provided between the source of the source and the common source line.

Note that when a stacked gate structure is adopted, the MNO
S) MOS F in the channel formation region of transistor Q2
The channel forming regions of ETQ1 and Q3 are directly adjacent to each other. Therefore, the drain and source of the MNOS transistor Q2 should be understood as terms of convenience.

The gates of the address selection MO3FETQI, etc. of the memory cells arranged in the same row are connected to the first word line W.
The gates of the MNOS transistors Q2 and the like that are commonly connected to the second word line W12 are commonly connected to the second word line W12. Similarly, the gates of the memory cell address selection MO3FET and MNOS transistor arranged in the same row are connected to the first word line W21. W22
are commonly connected.

MO for selecting addresses of memory cells arranged in the same column
The drains of the 3FETQI and the like are commonly connected to the data line DO. Similarly, the drains of the address selection MO3FETs of other memory cells arranged in the same column are commonly connected to the data line DI.

The source of the isolation MO3FET Q3 in each memory cell is shared, forming a common source' line C8.

The memory array of this embodiment is operated by the following potential.

In the read operation, the potential Vw of the well region WELL
is set to a low level equal to the ground potential of the solenoid circuit, O volts. The common source line C8 is set to a low level substantially equal to the ground potential. The control line coupled to the gate of isolation MO3FETQ3 connects these MO3FETQ3
is set to a high level equal to the y power supply voltage Vcc so as to turn it on. The second word lines W12 to W22, each coupled to the gate electrode of the MNOS transistor, are at a potential equal to the ground potential, i.e. a voltage between the high and low threshold voltages of the MNOS transistor. It is said that The word line to be selected among the first word lines Wll to W21 is set to a selection level or high level equal to the power supply voltage Vcc, and the remaining word lines, that is, unselected word lines, are set to the ground potential. set to a similar non-select level or low level. A sense current is supplied to the data lines Do to Dl from an appropriate load circuit (not shown).

M in the memory cell selected by the first word line
If the NOS transistor has a low threshold voltage, the memory cell will form a current path to the data line to which it is coupled. If the MNOS transistor in a selected memory cell has a high threshold voltage, that memory cell forms substantially no current path. Therefore, reading data from a memory cell appears as voltages on the data lines Do and Di depending on the presence or absence of a sense current. This voltage is applied to the switch MOS FETQ26, Q2 during data transfer from EEPROM to RAM.
7, etc., to a latch circuit FF having an amplification function.

In the write operation, the well region WELL is Q-
A negative high voltage equal to Vpp is applied to the isolation MO3.
The control lines coupled to the gate electrodes of FETs Q3 are brought to a high negative potential to turn those MO3FETs Q3 off. The first word lines Wll to W21 are set to a non-select level or low level equal to the ground potential.

One of the second word lines W12 to W22 is set to a selection level equal to the power supply voltage Vcc, and the remaining second word lines are set to a high negative voltage close to the voltage -Vl). be done. The data line is set to a high level equal to the power supply voltage Vcc or to a low level with a negative high voltage close to the negative voltage -vpp, depending on the data to be written into the memory cell.

In the erase operation, the well region WELL and the common source line C8 are set to an erase level equal to the power supply voltage Vcc or to a high level. First word line Wll
to W21 and the second word lines W12 to W'22
are basically set to a level equal to the power supply voltage Vcc of the circuit and to a level substantially equal to the voltage -vpp, respectively, for erasing. However, according to this embodiment, the levels of the first and second word lines are determined so that erasing of memory cells in each memory row is possible, although this is not particularly limited. The first word line corresponding to the memory row that needs to be erased among W11 to W21 is set to an erase level equal to the power supply voltage Vcc, and the first word line that corresponds to the memory row that needs to be erased is The corresponding first word line is brought to a non-erasing level, such as the ground potential of the \' circuit. Second word vAW12 to W22
The second word line corresponding to the first word line set to the erase level is set to an erase level equal to the negative voltage -vpp, and the first word line is set to the non-erasing level. The corresponding second word line is connected to the power supply voltage Vc.
to a non-erasing level equal to c.

According to this embodiment, the power supply voltage Vcc is applied to the well region (ie, MNOS) transistor substrate gate as described above.
A configuration is adopted in which the stored information of each MNOS transistor is erased by applying .

On the other hand, the N-channel MO3FE that constitutes the CMO3 circuit
The body gate of T is required to be brought to a potential, such as 0 volts, independently of the body gate of the MNO3I-transistor. Therefore, as mentioned above, the base gate of each memory cell, that is, the semiconductor region WELL in which the memory array is formed, is the semiconductor region (well region) in which the N-channel MO3FET forming the peripheral circuit such as the X decoder is formed. electrically isolated.

It is formed in the area WELL.

The first and second '7-FvAWl 1 1LW21 and W12 to W22 are each an X decoder X-DCR.
driven by. Although not particularly limited, the X-decoder X-DCR includes a plurality of unit decoder circuits in one-to-one correspondence with memory rows of the memory array. One unit decoder circuit is a NOR (N) which receives an address signal, for example as shown in the figure.

R) Consists of a gate circuit N0R1, a gate circuit G, and a level conversion circuit LVC.

At least during the read operation, the gate circuit G
The output of the corresponding NOR gate circuit is
The first word line is transmitted to the word line, and the first word line is made to have a level substantially equal to the ground potential of the circuit in a write operation, regardless of the output of the corresponding NOR gate circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G connects the output of the corresponding NOR gate circuit to the corresponding first word line during the read operation as well as during the erase operation. configured to transmit.

During a write operation, if the output of the corresponding NOR gate circuit is at a high selection level, the level conversion circuit LVC changes the second word line to a selection level equal to y' power supply voltage VCC in response to the output of the NOR gate circuit. If the output is a low level non-selection level, the second
The word line is brought to a non-select level equal to a negative voltage -Vl). During the erase operation, the level conversion circuit LVC also changes the second word line to an erase selection level equal to the negative voltage -vpp if the output of the corresponding NOR gate circuit is at a high selection level;
If the output of the NOR gate circuit is at a low non-selection level, the second word line is accordingly brought to an erase non-selection level equal to the power supply voltage Vcc.

The gates of the isolation MO3FETQ3 and the like are commonly coupled to a control line to which a control voltage ig generated by a control voltage generation circuit Vig-G is supplied. MO3 for these separations
The sources of the FETQ3 and the like are shared and constitute a common source line CS.

Control voltage Vi supplied to the separation MO3FETQ3
In a write operation as described later, the word line to which the memory cell to be selected among the second word lines W21 and W22 is connected is set to a high level (5■), and is used as a base gate. When the well region WELL of the MOS F E is set to about -12■ and the data line DO is set to about 10V, for example,
A low potential, such as about -10V, is applied to turn TQ 3 off. As a result, even if the data line DI is +
Even if it is set to a high level like 5■, the data 4iD
1, current is prevented from flowing into the memory cell side to which the above writing is to be performed.

The common source line CS is coupled to an output terminal of a common source line drive circuit DVR.

Basically, the drive circuit DVR can drive the common source line CS to the null power supply voltage Vcc level during the erase operation, and also drives the common source line CS to the ground potential of the circuit during the read operation. It is sufficient to have output characteristics that allow for As a result, in the erase operation, when the well region WELL is brought to the power supply voltage Vcc level, M
It is possible to prevent the junction between the electrode coupled to the common source line C8 of the OSFET Q3 and the well region WELL from being biased in the forward direction. Furthermore, a current path required for a read operation can be formed between the common source line C8 and the ground point of the circuit.

Although not particularly limited, the drive circuit DVR is an MO3 provided between the power supply terminal Vcc of the circuit and the common source line CS.
FETQ6, MO3FETQ7 and Q8 connected in parallel between the common source line C8 and the circuit ground point, and CMO
It consists of an S inverter circuit IV.

Above MO3FETQ7. A control signal e is applied to the gate of Q8.
r is supplied, and the control signal er is inverted by an inverter circuit IV and supplied to the gate of MO3FETQ6. As a result, the above MO3FETQ7. Q8 and Q6 are turned on/off in a complementary manner depending on the level of the control signal er. The control signal er is basically:
In order to turn on the MOSFET Q6 and turn on the MO3FETQ7 and Q8 during the erase operation, the voltage is set to a high level equal to the electric voltage Vcc, and during the read and write operations. , is set to a low level equal to \'O volts. According to this embodiment, the control signal er is the well region W
In order to prevent a PN junction formed by a MOSFET or the like formed in the ELL from being put into a forward bias state, its output timing is controlled in accordance with the timing of change in the potential of the well region.

According to this embodiment, the second word line W12. MOSFET Q4.W22 and the common source line C8, respectively.
Q5 is provided. These MO3FETQ4. Q
5 is switch-controlled by control signals er/we. Although not particularly limited, the control signal e r /
The high level of we is set equal to the power supply voltage Vcc, and the low level is set equal to the V ground potential.

MO3FETQ4. Q5 is the second word line W12°W2
It is made into a P-channel type so that it can be turned off well even when a negative potential is applied to 2.

Switch MO3FETQ4. During a read operation, transistors Q5 and the like are turned on so as to short-circuit the gates of the MNOS l-transistors Q2 and the like and the common source line CS to make them both at the same potential. These suis.

CH MO3FETQ4. Q5 is different from each second for the following reasons.
It is provided between the word line and the common source vAC8.

That is, MO3FETQ7. in the drive circuit DVR.
Q8 is turned on by setting the control signal er to a low level equal to 10 volts during a read operation. In this case, MO3FETs Q7 and Q8 have non-negligible on-resistance even though they are connected in parallel as shown. As a result, the potential of the common source line C8 increases due to the current flowing therein during reading. Especially MOSFETQ? , Q8 are of P-channel type, these MO3FETQ7゜Q8 are:
Since it does not have the driving ability to change the common source line CS to the ground potential of the circuit, the amount of rise in the potential of the common source line C8 becomes large. That is, MO3FET
Q7. Q8 has a current transfer electrode coupled to the common source line C8 in the memory array and the common source line C8.
Since the common source vAC8 acts as a source electrode with respect to the positive potential applied through the common source vAC8, when the potential of the common source vAC8 becomes equal to or lower than the respective threshold voltage, the common source vAC8 is substantially turned off. Such an increase in the potential of the common source line C8 causes an increase in the effective threshold voltage due to the substrate effect of the MNOS transistor, and reduces the conductance of the MNO3 transistor, which should have a low threshold voltage.

In other words, the read current flowing through the MNOS transistor with a low threshold voltage is reduced. The above shorted MO3FETQ4. Q5 is connected to each second
Word line W12. The potential of W22 is made substantially equal to the potential of common source line C8, thereby preventing an increase in the effective threshold voltage of the MNO3 transistor.

In the well region WELL where the memory array is formed, a control voltage 41U formed by a control voltage generation circuit Vw-G is provided.
A voltage Vw-G is supplied. This voltage Vw is set to a negative high voltage such as about -12 V during a write operation, set to a potential of about +5 cm during an erase operation, and set to about 0 cm at other times.

In this embodiment, in order to enable high-speed data transfer with the RAM, each data line Do, DI, etc. is connected to the switch M.
O3FETQ26. It is coupled to the unit latch circuit UFF via Q27 and the like. Each data line Do, D1, etc. is provided with a level conversion circuit LVC that selectively changes the potential of the data line to a negative high voltage -vpp in accordance with the information stored in the latch circuit FF during a write operation. With these,
Simultaneous writing of data into multiple memory cells coupled to one selected word line is enabled.

The effects obtained from the above examples are as follows. In other words, (1) it is equipped with a static type RAM having the same storage capacity as the EEPROM, and in the normal operating state it performs memory access to the RAM to speed up data rewriting, while also By mutually transferring data between the EEPROM and the nonvolatile memory circuit, it is possible to make the held data nonvolatile and to reduce the number of times the EEPROM is rewritten.

+21 E E F By transferring data between the ROM and RAM in units of word lines, it is possible to achieve the effect that data transfer can be performed in a relatively short period of time.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, in addition to the above-mentioned static type RAM, a dynamic type RAM may be used as the RAM. By using such a Guinamisoku type RAM, the area occupied by the memory array section can be reduced.

EEPROMs include those that use MNOS transistors as mentioned above, those that use FLOTOX (floating gate tunnel oxide) type storage elements, or those that use stacked gate transistors like the memory cells of EPROMs and have hot spots on the drain side. It is also possible to use an element having a configuration in which writing is performed by generating electrons, and erasing is performed by providing a tunnel insulating film on the source side and utilizing the tunnel phenomenon.

Data transfer between the EEPROM and RAM may be performed in units of 8 bits or the like by connecting the input/output circuit on the RAM side to an internal lot, instead of being performed in units of word lines as described above. In this case, on the EEPROM side, a latch circuit is provided on the data line, the first stage write operation is a write operation to the latch circuit, and the second stage write operation is based on the data taken into the latch circuit. It may also be a page write operation in which a write operation is performed on an element. In this configuration, the EEPR
A column selection circuit is also provided on the OM side.

The data transfer between the RAM and the EEPROM may be performed for all bits, or may be a partial transfer in which data is transferred only for the portion where the data has been changed. In this case, means for storing the address at which data has been rewritten on the RAM side is required. Also, RAM and E
The data at the same address as the EPROM may be read out, and if they do not match, the data in the EEFROM may be rewritten in accordance with the data in the RAM, thereby performing partial rewriting as a whole.

The present invention can be widely used as a semiconductor memory device that realizes high-speed operation and non-volatility.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, it is equipped with a static RAM that has the same storage capacity as the EEPROM, and during normal operation, memory access is made to the RAM to speed up data rewriting. By mutually transferring data between the two, it is possible to make the held data non-volatile and to reduce the number of times the EEFROM is rewritten.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a main circuit diagram showing a specific embodiment of the RAM section, and FIG. 3 is a specific implementation of the EEFROM section. FIG. 2 is a main part circuit diagram showing an example. RAM...Random access memory, EEPROM
・・Non-volatile memory, FF・・Latch circuit, C0NT・
・Control circuit, ADC・Address generation circuit, XDCR・
・X address decoder, YDCR ・・Y address decoder, X-DCR ・・X decoder, LVC ・Level conversion circuit, VigG, Vw-G ・・Control voltage generation circuit, IO
B...Input/output circuit, WELL...well area, DV...
Frequency divider circuit

Claims (1)

[Claims] 1. A non-volatile memory circuit that can be electrically written and erased, a RAM having the same storage capacity as the non-volatile memory circuit, and a memory access to the RAM in a normal operating state. 1. A semiconductor memory device comprising: a memory control circuit for selectively transferring data between a RAM and a nonvolatile memory circuit as necessary. 2. Claims characterized in that the memory control circuit transfers the data in the RAM to the non-volatile memory circuit when the power is turned off, and transfers the data in the non-volatile memory circuit to the RAM when the power is turned on. 2. The semiconductor memory device according to item 1. 3. The semiconductor memory device according to claim 1 or 2, wherein data transfer between the nonvolatile memory circuit and the RAM is performed on a word line basis via a latch circuit.