JP4872976B2 - Ferroelectric memory device - Google Patents

Ferroelectric memory device Download PDF

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JP4872976B2
JP4872976B2 JP2008176859A JP2008176859A JP4872976B2 JP 4872976 B2 JP4872976 B2 JP 4872976B2 JP 2008176859 A JP2008176859 A JP 2008176859A JP 2008176859 A JP2008176859 A JP 2008176859A JP 4872976 B2 JP4872976 B2 JP 4872976B2
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voltage
plate line
switch
plate
line
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JP2010015659A (en
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克之 黒川
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セイコーエプソン株式会社
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Description

  The present invention relates to a ferroelectric memory device. In particular, the present invention relates to a ferroelectric memory device with a small leakage current flowing through a ferroelectric capacitor.

  A conventional ferroelectric memory device is disclosed in Japanese Patent Laid-Open No. 2003-338172 (Patent Document 1). As shown in FIG. 5, the ferroelectric memory device disclosed in Patent Document 1 includes a memory cell MC including a switching transistor Tr and a ferroelectric capacitor Cf. A word line WL and a bit line BL are connected to the switching transistor Tr, and a plate line PL is connected to the ferroelectric capacitor Cf.

JP 2003-338172 A

  However, in the ferroelectric memory device disclosed in Patent Document 1, the switching transistor Tr is off when the word line WL is not selected, but the bit line is written when data is written to another memory cell MC. During this time, there is a problem that a leakage current flows through the switching transistor Tr and the ferroelectric capacitor Cf. In particular, when the leakage current flowing through the switching transistor Tr is larger than the leakage current flowing through the ferroelectric capacitor Cf, there is a problem that the polarization of the ferroelectric capacitor Cf decreases and the data deteriorates.

  Therefore, an object of the present invention is to provide a ferroelectric memory device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  To achieve the above object, according to the first aspect of the present invention, a memory cell, a plate line connected to one end of the memory cell, and a first voltage or a second voltage to be supplied to the plate line. A ferroelectric memory device comprising a plate line control circuit for setting a plate line to high impedance is provided. Further, it is preferable that the plate line control circuit supplies the first voltage or the second voltage to a predetermined plate line among the plurality of plate lines and makes the other plate lines have high impedance.

  According to the above aspect, since the plate line can be set to high impedance as necessary, it is not necessary to hold the plate line at the first voltage (for example, drive voltage) and the second voltage (for example, ground voltage). In this case, the plate line can be held at high impedance. As a result, the leakage current flowing through the memory cell can be reduced, so that a ferroelectric memory device with little deterioration of stored data can be provided.

  The ferroelectric memory device further includes a bit line and a word line for switching whether or not the bit line is connected to the memory cell, and the plate line control circuit is configured to display the plate line when the word line is not selected. May be set to high impedance.

  In the above embodiment, when a word line is not selected, for example, when a write operation or a read operation is not performed on the memory cell, the plate line connected to the memory cell becomes high impedance. Therefore, a potential difference is unlikely to occur at both ends of the memory cell, in particular, the ferroelectric capacitor. Therefore, according to the above embodiment, the leakage current flowing through the memory cell, in particular, the ferroelectric capacitor can be reduced, so that deterioration of stored data can be further suppressed.

  The plate line control circuit may switch whether or not to set the plate line to high impedance according to the timing at which the voltage of the word line changes.

  In the above configuration, whether or not the plate line is set to high impedance is switched according to the timing at which the voltage of the word line changes, for example, the timing at which the memory cell connected to the word line is selected. The period of high impedance is further increased. Therefore, according to the above embodiment, it is possible to further suppress deterioration of stored data.

  The plate line control circuit includes an output terminal to which the plate line is connected, a first terminal to which a first voltage is supplied, a first switch provided between the output terminal and the first terminal, A second switch and a third switch provided in series between the output terminal and the second terminal, and supplying the first voltage or the second voltage to the output terminal; You may control a 1st switch, a 2nd switch, and a 3rd switch so that it may become high impedance.

  According to the said form, it can switch whether a plate line is made into a high impedance by a very simple structure.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

  FIG. 1 is a diagram showing an example of a ferroelectric memory device 100 according to an embodiment of the present invention. The ferroelectric memory device 100 includes a memory cell array 110, a word line control circuit 120 that controls voltages of a plurality of word lines WL, a plate line control circuit 130 that controls voltages of a plurality of plate lines PL, and a plurality of bits. A sense amplifier 140 that controls the voltage of the line BL and detects data read out to the bit line BL is provided.

  The memory cell array 110 has a plurality of memory cells arranged in an array. Each memory cell is connected to a word line WL, a bit line BL, and a plate line PL. The word line control circuit 120, the plate line control circuit 130, and the sense amplifier 140 are connected to a plurality of word lines WL, a plurality of plate lines PL, and a plurality of bit lines BL, respectively. The word line control circuit 120, the plate line control circuit 130, and the sense amplifier 140 are connected to the voltages of the word line WL, the plate line PL, and the bit line BL based on an address signal supplied from the outside of the ferroelectric memory device 100. And a predetermined memory cell is selected from the memory cell array 110. Thus, data stored in the memory cell can be read and predetermined data can be written in the memory cell.

  FIG. 2 is a diagram showing a part of the configuration of the memory cell array 110 and the plate line control circuit 130. In the configuration shown in FIG. 2, only four memory cells MC are shown for convenience of explanation. Each memory cell MC included in the memory cell array 110 has an n-type MOS transistor TR and a ferroelectric capacitor C. The n-type MOS transistor TR has a gate connected to one of the plurality of word lines WL, a source connected to one of the plurality of bit lines BL, and a drain connected to one end of the ferroelectric capacitor C. . The n-type MOS transistor TR switches whether to connect the bit line BL connected to the source to the ferroelectric capacitor C based on the voltage of the word line WL connected to the gate. The other end of the ferroelectric capacitor C is connected to one of the plurality of plate lines PL. The ferroelectric capacitor C stores predetermined data based on the potential difference between one end and the other end, that is, the potential difference between the bit line BL and the plate line PL.

  The plate line control circuit 130 has a plurality of driver circuits 132 connected to each plate line PL. The driver circuit 132 includes a p-type MOS transistor 134 and n-type MOS transistors 136 and 138. The p-type MOS transistor 134 has a source connected to the power supply and a drain connected to the plate line PL. The source of the n-type MOS transistor 136 is grounded, and the drain is connected to the source of the n-type MOS transistor 138. N-type MOS transistor 138 has a drain connected to the drain of p-type MOS transistor 134 and plate line PL.

  A plate line control signal PLb for controlling the voltage of the plate line PL is supplied to the gates of the p-type MOS transistor 134 and the n-type MOS transistor 136, and the gate of the n-type MOS transistor 138 has its drain connected to its drain. A floating control signal PLF for controlling whether or not the connected plate line PL is to be floated is supplied. That is, the p-type MOS transistor 134 and the n-type MOS transistor 136 constitute an inverter, and based on the plate line control signal PLb, the voltage of the corresponding plate line PL is changed to the power supply voltage which is an example of the first voltage. Or, it operates so as to be a ground voltage which is an example of the second voltage.

  On the other hand, the n-type MOS transistor 138 switches whether to connect the corresponding plate line PL to the drain of the n-type MOS transistor 136 based on the floating control signal PLF. That is, the n-type MOS transistor 138 switches between setting the corresponding plate line PL to the ground voltage or the high impedance when the plate line control signal PLb is the ground voltage.

  FIG. 3 is a timing chart showing the operation of the ferroelectric memory device 100 of this embodiment. 1 to 3, data “1” is written to memory cell MC1 connected to word line WL1, plate line PL1, and bit line BL1, and word line WL2, plate line PL2, and bit line are written. The operation of the ferroelectric memory device 100 will be described by taking as an example a case where data stored in the memory cell MC2 connected to BL1 is held as it is.

  In the following example, each signal is a digital signal indicating L logic or H logic. In the following example, when each signal indicates L logic, the voltage of the signal (or voltage of the word line WL, etc.) is the ground voltage, and when each signal indicates H logic, the voltage of the signal (or word line) Voltage such as WL) is VCC, VDD or VPP which is a driving voltage of the ferroelectric memory device 100. Note that the voltage of each signal is not limited to this, and the voltage of the signal (or the voltage of the word line WL or the like) when indicating H logic is the voltage of the signal (or the word line WL) when indicating the L logic. Or any other voltage). Further, in the example of FIG. 3, the case where the plate line PL is in a high impedance state is illustrated by hatching.

  First, before the ferroelectric memory device 100 starts a write operation, the word line control circuit 120 sets the voltages of the word lines WL1 and WL2 to the ground voltage and turns off the n-type MOS transistors TR in the memory cells MC1 and MC2. To do. Since plate line control signals PLb-1 and 2 supplied to driver circuits 132-1 and 2 are both H logic, p-type MOS transistors 134-1 and 2 are turned off, and n-type MOS transistor 136-1 and 2 are turned on. On the other hand, since floating control signals PLF-1 and 2 are L logic, n-type MOS transistors 138-1 and 2 are both turned off. That is, before starting the write operation, the plate lines PL-1 and PL-2 are in a floating state, and the potential thereof becomes high impedance.

  Next, when the floating control signal PLF-1 changes from L logic to H logic shortly before the word line WL1 is selected, the n-type MOS transistor 138-1 is turned on accordingly. As a result, plate line PL1 is grounded via n-type MOS transistors 138-1 and 136-1. On the other hand, since the floating control signal PLF-2 supplied to the driver circuit 132-2 remains L logic, the plate line PL2 remains high impedance.

  Next, the word line control circuit 120 raises the voltage of the word line WL1, turns on the n-type MOS transistor TR of the memory cell MC1, and connects one end of the ferroelectric capacitor C and the bit line BL1. On the other hand, since the plate line control signal PLb-1 changes from the H logic to the L logic, a voltage of + VCC is applied with reference to the point A of the ferroelectric capacitor C, and "0" data is once written.

  Then, the plate line control signal PLb-1 changes from L logic to H logic, the driver circuit 132-1 sets the plate line PL1 to the ground voltage, and the sense amplifier 140 increases the voltage of the bit line BL1. As a result, a voltage of −VCC is applied to the ferroelectric capacitor C of the memory cell MC1 with respect to the point A, and “1” data is written into the ferroelectric capacitor C.

  When “1” data is written in the ferroelectric capacitor C, the word line control circuit 120 sets the word line WL1 to the ground voltage and turns off the n-type MOS transistor TR. In addition, the sense amplifier 140 sets the voltage of the bit line BL1 to the ground voltage. Then, the floating control signal PLF-1 changes from H logic to L logic, and the n-type MOS transistor 138 is turned off, so that the plate line PL1, which is the ground voltage, becomes high impedance.

  On the other hand, since the plate line control signal PLb-2 remains at H logic and the floating control signal PLF-2 remains at L logic during the period when data is written in the memory cell MC1, the plate line PL2 remains high. The impedance is maintained.

  In the present embodiment, the floating control signal PLF-1 changes from L logic to H logic before the voltage of the word line WL1 rises from the ground voltage, and the word line WL falls to the ground voltage. The driver circuit 132-1 controls whether or not the plate line PL1 is set to a high impedance in synchronization with the timing at which the voltage of the word line WL1 changes, although it changes from the H logic to the L logic after the timing. Also good.

  As described above, according to the present embodiment, the plate line can be set to high impedance as necessary. Therefore, when the plate line PL does not need to be held at VCC or the ground voltage, the plate line PL is set to high impedance. Can hold. Thus, the leakage current flowing through the memory cell MC connected to the plate line PL, in particular, the ferroelectric capacitor C can be reduced, so that a ferroelectric memory device with little deterioration of stored data can be provided. it can.

  In the present embodiment, when the word line WL is not selected, that is, when the write operation or the read operation is not performed on the memory cell MC connected to the word line WL, the memory cell MC is connected. The plate line PL becomes high impedance. Therefore, a potential difference is unlikely to occur at both ends of the memory cell MC, in particular, the ferroelectric capacitor C. Therefore, according to the present embodiment, the leakage current flowing through the ferroelectric capacitor C can be reduced, so that deterioration of stored data can be further suppressed.

  Whether the plate line PL connected to the memory cell MC has a high impedance according to the timing at which the voltage of the word line WL changes, for example, the timing at which the memory cell MC connected to the word line WL is selected. You may switch whether or not. As a result, the period during which the plate line PL becomes high impedance can be further extended. Therefore, according to the above embodiment, it is possible to further suppress deterioration of stored data.

  In the present embodiment, the driver circuit 132 has an extremely simple configuration in which an n-type MOS transistor 138 is added in addition to an inverter composed of a p-type MOS transistor 134 and an n-type MOS transistor 136, and the plate line PL is connected to a high impedance. It can be switched whether or not.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

1 is a diagram showing an example of a ferroelectric memory device 100 according to an embodiment of the present invention. 2 is a diagram showing a part of the configuration of a memory cell array 110 and a plate line control circuit 130. FIG. 3 is a timing chart showing the operation of the ferroelectric memory device 100 of the present embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 110 ... Memory cell array, 120 ... Word line control circuit, 130 ... Plate line control circuit, 132 ... Driver circuit, 134 ... P-type MOS transistor 136, 138 ... n-type MOS transistor, 140 ... sense amplifier, BL ... bit line, C ... ferroelectric capacitor, MC ... memory cell, PL ... plate line, PLb ... Plate line control signal, PLF ... Floating control signal, WL ... Word line

Claims (1)

  1. A plurality of memory cells;
    Multiple bit lines,
    A plurality of word lines for switching whether or not each of the plurality of bit lines is connected to one end of the corresponding memory cell; a plurality of plate lines connected to the other end of each of the plurality of memory cells;
    A plurality of plate line control circuits for supplying a first voltage or a second voltage to the plurality of plate lines or making the plate line high impedance,
    Each of the plurality of plate line control circuits includes:
    An output terminal to which the plate wire is connected;
    A first terminal to which the first voltage is supplied;
    A second terminal to which the second voltage is supplied;
    A first switch provided between the output terminal and the first terminal;
    A second switch and a third switch provided in series between the output terminal and the second terminal;
    The third switch is provided between the output terminal and the second switch,
    Each plate line control circuit
    In synchronization with the timing at which the word line corresponding to a plate line connected to the plate line control circuit is selected so as to supply the first voltage to (1) the output terminal, said first switch turns, turns off the second switch, either on the third switch, or turns off the first switch to supply the second voltage to the (2) the output terminal, wherein Turn on the second switch, turn on the third switch,
    The first switch is turned off , the second switch is turned on, and the third switch is turned off so that the output terminal is set to high impedance in synchronization with the timing at which the word line is not selected. And a ferroelectric memory device.
JP2008176859A 2008-07-07 2008-07-07 Ferroelectric memory device Expired - Fee Related JP4872976B2 (en)

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JP5500051B2 (en) * 2010-11-22 2014-05-21 富士通セミコンダクター株式会社 Ferroelectric memory

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JPH06236969A (en) * 1993-02-12 1994-08-23 Hitachi Ltd Ferroelectric memory
JP3020422B2 (en) * 1994-12-22 2000-03-15 松下電器産業株式会社 Semiconductor storage device
KR100261221B1 (en) * 1997-12-31 2000-07-01 윤종용 Single transistor unit cell, method for manufacturing thereof,memory circuit constructed the aboved cell and method for driving memory circuit
JP3495905B2 (en) * 1998-02-19 2004-02-09 シャープ株式会社 Semiconductor storage device
JP2000215676A (en) * 1999-01-14 2000-08-04 Sharp Corp Semiconductor memory device
JP2004303293A (en) * 2003-03-28 2004-10-28 Seiko Epson Corp Data readout method for ferroelectric storage device and ferroelectric storage device

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