KR20050113303A - Sub word line driver in semiconductor memory device - Google Patents

Abstract

A memory device having a CMOS type sub word line driver is disclosed. The semiconductor memory device according to the present invention has a ground level or a negative voltage level when the gate node of the sub wordline driver is in an inactive steady state state. Thus, leakage current between the word line enable signal line and another signal line is prevented, thereby improving the reliability of the memory device and maintaining the internal boosted power supply voltage level, thereby preventing unnecessary waste of internal power consumption.

Description

Sub word line driver in semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a CMOS type sub word line driver of a semiconductor memory device.

In the conventional CMOS type sub word line driver 200, when the sub word line driver is inactive, the gate node of the word line driver has an internal boost power supply voltage level. Therefore, a bridge or defect is generated between the word line enable signal NWEB line occupied by the internal boost power supply voltage and another signal line occupied at a logic low level, resulting in a leakage source. source). Therefore, this causes the level of the internal boosted power supply voltage to be reduced, and the internal boosted power generation circuit which senses this continues to operate, thereby increasing the internal power consumption.

An object of the present invention is to provide a signal line in a memory device such that a word line enable signal line input to the sub word line driver has a ground voltage or a negative voltage level when the sub word line driver is in an inactive state. It is to provide a semiconductor memory device that prevents bridge or defects occurring in between.

In order to achieve the object of the present invention as described above, according to an embodiment of the present invention, the semiconductor memory device, the plurality of sub word line driver, and one normal word line enable signal (NWE) by the plurality of A word line enable signal driver for driving two word line drivers, wherein the sub word line driver comprises a PMOS transistor and an NMOS transistor, and activates the word line through the PMOS transistor; And an inverter connected in common to the gate node of the PMOS type transistor and the NMOS type transistor of the sub word line driver to invert an electrode of the gate node.

In one embodiment of the present invention, the sub word line driver, the first inverter to invert the normal word line enable signal (NWE) output from the word line enable signal driver, the output of the first inverter to the gate terminal Of the first PMOS transistor connected to the drain word terminal and the sub word line driver driving signal PXiD, and the output of the first inverter is connected to the gate terminal and the output terminal of the source terminal of the first PMOS transistor is connected to the drain terminal. Is connected, a first NMOS transistor having a second voltage connected to a source terminal, an inverted sub word line driver driving signal PXiB is connected to a gate terminal, and a drain terminal is a source terminal of the first PMOS transistor; A second NMOS transistor connected to the drain terminal of the first NMOS transistor and the sub word line, and having a second voltage connected to the source terminal. It includes.

Preferably, in the first inverter of the sub word line driver, a normal word line enable signal NWE output from the word line enable signal driver is connected to a gate terminal, and a first power supply voltage is connected to a drain terminal. A second PMOS transistor, a normal word line enable signal NWE output from the word line enable signal driver, is connected to a gate terminal, a source terminal of the second PMOS transistor is connected to a drain terminal, and a source terminal The third NMOS transistor may be connected to a second voltage.

In an embodiment, the word line enable signal driver may include a third PMOS transistor having a gate terminal connected to a precharge control signal, a source terminal connected to the power supply voltage, and a gate terminal connected to an address signal; And a plurality of NMOS transistors connected in series to the third PMOS transistor, and a second inverter connected to a drain terminal of the third PMOS transistor.

In one embodiment of the present invention, when the sub word line drivers are inactive, the level of the normal word line enable signal NWE line output from the word line enable signal driver is ground level. Keep it.

In order to fully understand the present invention, the advantages of the operability of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a diagram illustrating a part of a cell block structure of a memory having a conventional sub word line.

1 illustrates a memory cell block 100 having a sub word line (SWD) structure of a conventional CMOS type. The memory cell block 100 includes a plurality of memory cell arrays 101, a sub word line driver 103, and a word line enable signal driver 105. Include. The memory cell array 101 stores or reads data in a memory cell in response to a word line signal output from the sub word line driver 103. The sub word line driver block (SWD BLK) 103 transitions the word line to a logic high level in response to a signal output from the word line enable signal driver block (NWE Driver BLK) 105. As a result, data of the memory cell connected to the corresponding word line is loaded on the bit line. The word line enable signal driver block 105 receives an externally input address Ai and applies a normal word line enable signal NWE to a word line corresponding to the address.

The number of signal lines output from the word line enable signal driver block 105 depends on the cell density of the semiconductor memory device and the circuit structure of the memory device, and one word line enable signal driver block (NWEB) signal line. Four word lines per charge may be charged. At this time, one word line is selected and charged from four word lines connected to one signal line according to coding of the sub word line driver driving signals PXiD and PXjD of FIG. 1. Typically, a memory device with a data cell size of 512M has 4K signal lines. In addition, the signal line output from the word line enable signal driver block NWEB has a structure arranged throughout the cell block of the semiconductor memory device.

FIG. 2 is an enlarged circuit diagram of a sub word line driver of the CMOS type of FIG. 1.

Referring to FIG. 2, the sub word line driver 200 drives the inverted word line enable signal NWEiB, the sub word line driver drive signal PXiD, and the inverted sub word line driver output from the word line enable signal driver. The signal PXiB is input to activate the corresponding word line WL.

In the conventional sub word line driver 200, the gate of the first PMOS transistor 201, the gate terminal of which is connected to the inverted word line enable signal NWEiB and the drain terminal of the sub word line driver driving signal PXiD, A first NMOS transistor 203 whose terminal is connected to an inverted word line enable signal NWEiB, a drain terminal is connected to a source terminal of the first PMOS transistor 201, and a source terminal is connected to a ground voltage, and a gate The terminal is connected to the inverted sub word line driver driving signal PXiB, the drain terminal is connected to the source terminal of the first PMOS transistor 201 and the source terminal is composed of the second NMOS transistor 205 connected to the ground voltage. do. The word line WL is output from the common connection contact between the source terminal of the first PMOS transistor 201, the drain terminal of the first NMOS transistor 203, and the drain terminal of the second NMOS transistor 205.

The inverted word line enable signal NWEiB input to the sub word line driver 200 has a logic high level, that is, the gate terminals of the first PMOS transistor 201 and the first NMOS transistor 203 have an internal boosted power supply voltage level. (VPP), the first PMOS transistor 201 is turned off and the first NMOS transistor 203 is turned on. Therefore, the ground voltage and the word line WL are connected. The sub word line driver 200 is in an inactive state, the word line WL maintains a logic low level, and the memory cell connected to the word line WL is not selected.

The inverted word line enable signal NWEiB input to the sub word line driver 200 is at a logic low level, that is, the gate terminals of the first PMOS transistor 201 and the first NMOS transistor 203 are ground level or negative voltage. If the level VSS is present, the first PMOS transistor 201 is turned on and the first NMOS transistor 203 is turned off. At this time, the sub word line driver driving signal PXiD of the selected sub word line driver 200 has a logic high level, and the inverted sub word line driver driving signal PXiB has a logic low level. Accordingly, the second NMOS transistor 205 also maintains turn off. Accordingly, the logic high level sub word line driver driving signal PXiD is output to the word line WL. In addition, the sub word line driver 200 becomes active, the word line WL maintains a logic high level, and a memory cell connected to the word line WL is selected so that data of the memory cell is a bit line. It is output as (BL).

3 is a circuit diagram illustrating a word line enable signal driver driving a plurality of sub word lines.

The word line enable signal NWE driver 300 shown in FIG. 3 generates an inverted word line enable signal NWEiB input to the word line driver 200 of FIG. 2 in response to an externally input address signal. Function to output The word line enable signal driver 300 includes a PMOS transistor having a gate terminal connected to a precharge control signal PRE, a drain terminal connected to a power supply voltage, and a source terminal connected in series to a plurality of NMOS transistors 303 to 309. 301, a plurality of NMOS transistors 303 to 309 and a source of the PMOS transistor 301 having a gate terminal connected to an address signal Ai and connected in series between the PMOS transistor 301 and a ground voltage VSS. A first inverter 311 connected to the terminal and a second inverter 313 connected to the first inverter.

The precharge control signal PRE connected to the gate terminal of the PMOS transistor 301 maintains a logic low level when the PMOS transistor 301 is inactive, thereby turning on the PMOS transistor 301 and powering up the word line enable signal driver 300. Precharge to voltage (VPP). Thus, the inverted word line enable signal NWEiB maintains a logic high level.

When the address signals Ai inputted to the gate terminals of the NMOS transistors 303 to 309 connected in series are all at the logic high level, and the precharge control signal PRE is at the logic high level, the plurality of NMOS transistors ( 303 through 309 are all turned on and the PMOS transistor 301 is turned off. Thus, the inverted word line enable signal NWEiB maintains a logic low level.

4 is a timing diagram of a conventional CMOS type sub word line driver.

Referring to FIGS. 2 to 4, when an operation of the sub word line driver 200 is described, when the sub word line driver 200 is in an inactive state, an address signal Ai, a precharge control signal PRE, The sub word line driver driving signal PXiD and the word line WL have a logic low level, and the inversion word line enable signal NWEiB and the inverting sub word line driver driving signal PXiB maintain a logic high level. Therefore, the signal line NWEiB connected from the word line enable signal driver 300 to the word line driver 200 maintains a logic high level when the word line is inactive.

When the sub word line driver 200 becomes active, the address signal Ai and the precharge control signal PRE transition to a logic high level. Thereafter, the inverted sub-word enable signal NWEiB output from the word line enable signal driver 300 transitions to a logic low level and is output to the word line driver 200. At the same time, the sub word line driver driving signal PXiD and its inverting signal PXiB transition to a logic high level and a logic low level, respectively, to drive the word line driver 200. Thereafter, the word line driver 200 is activated, and the word line WL transitions to a logic high level.

The conventional sub word line driver 200 has a gate node of a word line driver, that is, a gate node of a first PMOS transistor and a first NMOS transistor when the sub word line driver is in an inactive steady state. Has a boosted power supply voltage level. In addition, when the sub word line driver is active, the gate node of the word line driver, that is, the gate nodes of the first PMOS transistor and the first NMOS transistor has a ground level or a negative voltage level.

That is, when the word line driver is inactive, the word line enable signal line from the word line enable signal driver to the word line driver maintains a logic high level with an internal boost power supply level (VPP). A bridge or defect may occur between the line enable signal line and another signal line having a logic low level.

Fig. 5 is a diagram showing generation of leakage current in a memory device having a conventional word line driver structure.

In the arrangement of the metal bus line layout in the semiconductor memory device illustrated in FIG. 5, the signal line NWEB output from the word line enable signal driver and another signal line and the ground power line VSS cross each other. Are arranged.

In order to select a predetermined word line of the memory device, a word line enable signal line connected to a corresponding word line driver among the signal lines output from the word line enable signal driver transitions to a logic low level (VSS), and the remaining words Line Enable The signal line maintains a logic high level (VPP). In this case, since most of the unselected word line enable signal lines are set to a logic high level (VPP), as shown in FIG. 5, between other signal lines having logic low levels (VSS) connected to each other. A bridge or defect will occur and cause leakage current. In addition, this causes the level of the internal boosted power supply voltage VPP to be reduced, so that the internal boosted power supply voltage generation circuit must continue to operate, and as a result, the internal power consumption increases. This may be a problem of decreasing the reliability of the memory device.

According to the present invention, a memory device having a sub word line driver of CMOS type is set to have a ground level or a negative voltage level when a gate node of the sub word line driver is in an inactive state.

6 is a view illustrating a part of a cell block structure of a memory having a sub word line according to the present invention.

The memory cell block 600 illustrated in FIG. 6 includes a CMOS word sub word line driver block (SWD BLK) 603 and a word line enable signal driver block (NWE Drive BLK) 605 according to the present invention. Include. The sub word line driver block (SWD BLK) 603 according to the present invention has a word line enable signal (NWEi) output from the word line enable signal driver block (NWE Driver BLK) 605 from a logic low level to a logic high level. Transitioning causes the corresponding word line to transition to a logic high level. Accordingly, data of the memory cell 601 connected to the corresponding word line is loaded on the bit line.

The word line enable signal driver block 605 outputs the word line enable signal NWEi of the logic low level VSS when the sub word line driver 603 is in an inactive state. In addition, when an address Ai corresponding to the sub word line driver 603 is externally input, the word line enable signal NWEi of the logic high level VPP is input to the word line driver 603 corresponding to the address. By applying the to activate the corresponding sub word line driver 603, the word line transitions to a logic high level.

FIG. 7 is an enlarged circuit diagram of a sub word line driver of the CMOS type of FIG. 6.

Referring to FIG. 7, the sub word line driver 700 according to the present invention includes a word line enable signal NWEi output from a word line enable signal driver, a sub word line driver drive signal PXiD, and an inverted sub word. The line driver driving signal PXiB is input to activate a corresponding word line WL.

The sub word line driver 200 according to the present invention includes a first PMOS transistor 701 having a normal word line enable signal NWEi connected to a gate terminal thereof, and an internal boosted power supply voltage VPP connected to a drain terminal thereof; A first NMOS transistor 703 in which the normal word line enable signal NWE is connected to a gate terminal, a source terminal of the first PMOS transistor 701 is connected to a drain terminal, and a ground voltage VSS is connected to a source terminal. ), A second PMOS transistor 705 having a source terminal of the first PMOS transistor 701 connected to a gate terminal, and a sub word line driver driving signal PXiD connected to a drain terminal thereof, and a first PMOS transistor connected to a gate terminal thereof; A second NMOS transistor 707 having a source terminal of 701 connected, a source terminal of the second PMOS transistor 705 connected to a drain terminal, and a ground voltage VSS connected to a source terminal; A third NMOS transistor connected to an inverted sub word line driver driving signal PXiB through a gate terminal, a source terminal of the second PMOS transistor 705 connected to a drain terminal, and a ground voltage VSS connected to a source terminal 709). A word line WL is connected to a common connection contact between a source terminal of the second PMOS transistor 705, a drain terminal of the second NMOS transistor 707, and a drain terminal of the third NMOS transistor 709.

The first PMOS transistor 701 and the first NMOS transistor 703 serve as inverters, thereby inverting the normal word line enable signal NWEi input to the sub word line driver 700 to thereby invert the second PMOS transistor. 705 and the gate node of the second NMOS transistor 707.

The normal word line enable signal NWEi input to the sub word line driver 700 is at a logic low level, that is, a ground level or a negative voltage level to the gate terminals of the first PMOS transistor 701 and the first NMOS transistor 703. When VSS is applied, the first PMOS transistor 701 is turned on and the first NMOS transistor 703 is turned off. Accordingly, the internal boosted power supply voltage VPP input to the drain terminal of the first PMOS transistor 701 is connected to the gate terminal of the second PMOS transistor 705 and the second NMOS transistor 707. The second PMOS transistor 705 is turned off and the second NMOS transistor 707 is turned on due to the application of the logic high level internal boosted power supply voltage VPP. Therefore, the ground voltage VSS and the word line WL are connected. In addition, the sub word line driver 700 is in an inactive state, the word line WL maintains a logic low level due to the ground voltage VSS, and the memory cell connected to the word line WL is not selected. .

The normal word line enable signal NWEi input to the sub word line driver 700 is at a logic high level, that is, an internal boosted power supply voltage level to the gate terminals of the first PMOS transistor 701 and the first NMOS transistor 703. When VPP is applied, the first PMOS transistor 701 is turned off and the first NMOS transistor 703 is turned on. Therefore, the ground voltage VSS connected to the source terminal of the first NMOS transistor 703 is connected to the gate terminal of the second PMOS transistor 705 and the second NMOS transistor 707. In addition, due to the application of the logic low level ground voltage VSS, the second PMOS transistor 705 is turned on and the second NMOS transistor 707 is turned off. At this time, the sub word line driver driving signal PXiD input to the selected sub word line driver 700 has a logic high level, and the inverted sub word line driver driving signal PXiB has a logic low level. Accordingly, the third NMOS transistor 709 also maintains turn off. As a result, the logic high level sub word line driver driving signal PXiD is connected to the word line WL. In addition, the sub word line driver 700 becomes active, the word line WL maintains a logic high level, and a memory cell connected to the word line WL is selected so that data of the memory cell is a bit line. It is output as (BL).

8 is a circuit diagram illustrating a word line enable signal driver according to the present invention.

The word line enable signal NWE driver 800 illustrated in FIG. 8 generates a normal word line enable signal NWEi input to the word line driver 700 of FIG. 7 in response to an externally input address signal. Function to output The word line enable signal driver 800 is a PMOS having a precharge control signal PRE connected to a gate terminal, a power supply voltage connected to a drain terminal, and a plurality of NMOS transistors 803 to 809 connected in series to a source terminal. Transistor 801, a plurality of NMOS transistors 803 to 809 connected in series between the PMOS transistor 801 and the ground voltage VSS, and an address signal Ai connected to a gate terminal, and the PMOS transistor 801. Inverter 811 connected to the source terminal of the.

The precharge control signal PRE connected to the gate terminal of the PMOS transistor 301 maintains a logic low level when the PMOS transistor 301 is inactive, thereby turning on the PMOS transistor 801 and internalizing the word line enable signal driver 800. Precharge to rising power supply voltage (VPP). Therefore, the source terminal of the PMOS transistor 801 becomes the internal rising power supply voltage VPP level, and the normal word line enable signal NWEi output from the inverter 811 becomes the ground voltage or the negative voltage level.

When the address signals Ai input to the gate terminals of the NMOS transistors 803 to 809 connected in series are all at the logic high level, and the precharge control signal PRE is at the logic high level, the plurality of NMOS transistors ( 803 to 809 are all turned on and the PMOS transistor 801 is turned off. Accordingly, the source terminal of the PMOS transistor 801 becomes the ground voltage level, and the normal word line enable signal NWEi output from the inverter 811 maintains a logic high level, that is, an internal rising power supply voltage level VPP.

9 is a timing diagram of a conventional CMOS type sub word line driver.

7 to 9, when an operation of the sub word line driver 7000 is performed, when the sub word line driver 700 is in an inactive state, an address signal Ai, a precharge control signal PRE, and a normal state are described. The word line enable signal NWE, the sub word line driver drive signal PXiD, and the word line WL have a logic low level, and the inverted sub word line driver drive signal PXiB maintains a logic high level. Accordingly, the signal line NWEi connected from the word line enable signal driver 800 to the word line driver 700 maintains a logic low level when the word line is inactive.

When the sub word line driver 200 becomes active, the address signal Ai and the precharge control signal PRE transition to a logic low level. Then, the word line enable signal driver 800 transitions the normal sub word line enable signal NWEi to a logic high level. At the same time, at the same time, the sub word line driver drive signal PXiD and its inverted signal PXiB transition to a logic high level and a logic low level, respectively, to drive the word line driver 700. Thereafter, the word line driver 700 is activated and the word line WL transitions to a logic high level.

In the sub word line driver 700 according to the present invention, when the sub word line driver is in an inactive steady state, the gate node of the word line driver has a ground level or a negative voltage level VSS. In addition, when the sub word line driver is active, the gate node of the word line driver has an internal boosted power supply voltage level VPP.

That is, in the semiconductor memory device having the word line driver structure according to the present invention, when the word line driver is inactive, the word line enable is connected from the word line enable signal driver 800 to the word line driver 700. The signal NWE line maintains a logic low level with ground level or negative voltage level VSS. Therefore, since the voltage difference is the same as other signal lines having the ground level or the negative voltage level, there is no problem of bridges or defects between the signal lines arranged alternately in the semiconductor memory device.

That is, in the arrangement of other signal lines and ground power lines (VSS) arranged intersecting with the word line enable signal lines, most word line enable signal lines maintain a logic low level to keep the word line driver inactive. Have Accordingly, bridges or defects occur between different signal lines so that no leakage current occurs, thereby improving the reliability of the memory device. In addition, by maintaining the level of the internal boosted power supply voltage VPP, the unnecessary operation of the internal boosted power supply voltage generation circuit can be stopped, and unnecessary waste of internal power consumption can be prevented.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the semiconductor memory device according to the present invention, the leakage current between the word line enable signal line and another signal line is prevented, thereby improving the reliability of the memory device, maintaining the internal boosted power supply voltage level, and wasting unnecessary internal power consumption. To prevent.

1 is a diagram illustrating a part of a cell block structure of a memory having a conventional sub word line.

FIG. 2 is an enlarged circuit diagram of a sub word line driver of the CMOS type of FIG. 1.

3 is a circuit diagram illustrating a word line enable signal driver driving a plurality of sub word lines.

4 is a timing diagram of a conventional CMOS type sub word line driver.

Fig. 5 is a diagram showing generation of leakage current in a memory device having a conventional CMOS type sub word line driver structure.

6 is a view illustrating a part of a cell block structure of a memory having a sub word line according to the present invention.

FIG. 7 is an enlarged circuit diagram of a sub word line driver of the CMOS type of FIG. 6.

8 is a circuit diagram illustrating a word line enable signal driver according to the present invention.

9 is a timing diagram of a conventional CMOS type sub word line driver.

Claims (10)

In a semiconductor memory device, A plurality of sub word line drivers; And A word line enable signal driver for driving the plurality of word line drivers by one normal word line enable signal (NWE), The sub word line driver is configured of a PMOS type transistor and an NMOS type transistor, and activates the word line through the PMOS type transistor, and the gate node of the PMOS type transistor and the NMOS type transistor of the sub word line driver. And an inverter connected in common and inverting an electrode of the gate node. The method of claim 1, The sub word line driver A first inverter for inverting a normal word line enable signal (NWE) output from the word line enable signal driver; A first PMOS transistor having a gate terminal connected to an output of the first inverter and a drain terminal connected to a sub word line driver driving signal PXiD; A first NMOS transistor connected to an output of the first inverter through a gate terminal, an output of a source terminal of the first PMOS transistor to a drain terminal, and a second voltage connected to a source terminal; And An inverted sub word line driver driving signal PXiB is connected to a gate terminal, and a drain terminal is connected to a source terminal of the first PMOS transistor, a drain terminal of the first NMOS transistor, and the sub word line, and a source terminal. And a second NMOS transistor coupled to two voltages. The method of claim 2, The first inverter A second PMOS transistor connected to a normal word line enable signal NWE output from the word line enable signal driver to a gate terminal, and a first power supply voltage to a drain terminal; And A normal word line enable signal NWE output from the word line enable signal driver is connected to a gate terminal, a source terminal of the second PMOS transistor is connected to a drain terminal, and a second voltage is connected to a source terminal. And a third NMOS transistor. The method of claim 1, The sub word line driver is a semiconductor, characterized in that when the sub word line drivers are inactive, the level of the normal word line enable signal (NWE) line output from the word line enable signal driver maintains a ground level. Memory device. The method of claim 1, When the sub word line drivers are inactive, the sub word line driver maintains a power supply voltage level at which the level of the normal word line enable signal NWE output from the word line enable signal driver is lower than the ground level. A semiconductor memory device, characterized in that. The method of claim 3, The word line enable signal driver, A third PMOS transistor having a gate terminal connected to a precharge control signal and a source terminal connected to the power supply voltage; A gate terminal connected to the address signal, the plurality of NMOS transistors connected in series with the third PMOS transistor; And And a second inverter connected to the drain terminal of the third PMOS transistor. The method of claim 2, And the second voltage is a ground voltage. The method of claim 3, And the second voltage is a ground voltage. In the sub word line driver of a memory device, A first inverter for inverting the normal word line enable signal NWE output from the word line enable signal driver; A first PMOS transistor having a gate terminal connected to an output of the first inverter and a drain terminal connected to a sub word line driver driving signal PXiD; A first NMOS transistor connected to an output of the first inverter through a gate terminal, an output of a source terminal of the first PMOS transistor to a drain terminal, and a second voltage connected to a source terminal; And An inverted sub word line driver driving signal PXiB is connected to a gate terminal, and a drain terminal is connected to a source terminal of the first PMOS transistor, a drain terminal of the first NMOS transistor, and the sub word line, and a source terminal. And a second NMOS transistor coupled to two voltages. The method of claim 9, The sub word line driver, when the sub word line drivers are inactive, the level of the normal word line enable signal (NWE) line output from the word line enable signal driver maintains the ground level. Word line driver.