JPH1069796A - Semiconductor integrated circuit with high-speed test function - Google Patents

Abstract

(57) [Summary] [Problem] To improve test reliability. In a normal mode, a transfer gate is turned on and a transfer gate is turned off, and a clock generated by a ring oscillator is selected by a selection circuit.
The charge is supplied to the charge pump circuit 20 as a pumping pulse via the inverter 50. In the test mode, the transfer gate 41 is turned off and the transfer gate 42 is turned on. The clock generated by the ring oscillator 30 is selected by the selection circuit 40 and supplied to the charge pump circuit 20 as a pumping pulse via the inverter 50. Is done. Since the frequency of the pumping pulse in the test mode is higher than that in the normal mode, the charge pump circuit 20 pumps the charge at a higher speed. The configuration may be such that the number of inverter connection stages of one ring oscillator is variable or the capacity of the charge pump circuit is variable depending on the mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit with a high-speed test function.

[0002]

2. Description of the Related Art With the spread of personal computers and the enlargement of operating systems and programs, demand for memories has increased, and the capacity of single memories has been increasing. With this increase in capacity, the time for testing a single memory before shipment has increased. FIG.
1 shows a schematic configuration of a conventional semiconductor integrated circuit with a high-speed test function. This semiconductor integrated circuit includes an internal booster circuit and another circuit 1. The circuit 1 operates with an external power supply voltage Vcc and an internal power supply voltage Vpp obtained by boosting the same. The internal rising circuit includes a ring oscillator 10 and a charge pump circuit 20 to which a clock generated by the ring oscillator 10 is supplied as a pumping pulse.

The ring oscillator 10 includes an inverter 11
To 17 are connected in a ring shape. Charge pump circuit 2
Numeral 0 is provided with a pumping capacitor 21, a level shift diode 22, a diode 23 for backflow prevention and level shift, and analog changeover switches 24 and 25 for switching and connecting the pumping capacitor 21.

FIG. 6 shows an example of a configuration of a main part when the circuit 1 is a DRAM. In this circuit 1, the output of the row address buffer register 2 is decoded by row decoders 3A and 3B for different memory cell array blocks.
In the normal mode in which the mode signal TEST supplied to the external terminal is at the low level, the pMOS transistor of the word driver 4A is turned on by the row decoder 3A, for example, and the voltage Vpp is supplied to the word line Wl and connected to the word line Wl. The transfer gate of the memory cell 5A is opened, and the data stored in the memory cell 5A is read through the bit line Bl.

The external power supply voltage is as low as 3.3 V, for example, due to the miniaturization of memory cells. The potential rise of the bit line due to the read charge is slight, and it is necessary to reduce the potential drop at the transfer gate of the memory cell. Further, the word line is formed of polysilicon having a higher resistance than metal, and a large number of gate capacitances are connected, so that the operation becomes slow. Therefore,
Word line drive voltage Vpp is set to about 5V.

In the test mode in which the mode signal TEST is at a high level, for example, the pMOS transistors of the word driver 4A and the word driver 4B are simultaneously turned on to reduce the test time, and the voltage Vpp is applied to the word lines W1 and W2.
Is supplied, and the data stored in the memory cells 5A and 5B are read from the bit lines B1 and B2, respectively.
Further, in order to further reduce the test time, the system clock cycle is set to a minimum value in an allowable range.

[0007]

In the test mode, a plurality of word lines are simultaneously selected as described above and the system clock cycle is minimized, so that the boosted voltage Vpp decreases and the stress of the memory cells decreases. Invite
There is a possibility that the defective memory cell cannot be detected in the test.

An object of the present invention is to provide a semiconductor integrated circuit with a high-speed test function capable of improving the reliability of a test in view of such problems.

[0009]

[Means for Solving the Overload and Operation and Effect] According to the first invention, the device operates with an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and operates at a higher speed than in the normal mode. In a semiconductor integrated circuit with a high-speed test function having a test mode in which a test can be performed, the internal booster circuit includes:
A first clock generation circuit for generating a first clock, a second clock generation circuit for generating a second clock having a higher frequency than the first clock, and selecting the first clock in the normal mode to generate a pumping pulse. A selection circuit for supplying the charge pump to the charge pump, selecting the second clock in the test mode and supplying the same to the charge pump as a pumping pulse, and charging the pumping capacitor with the pumping pulse. A charge pump circuit that generates the internal power supply voltage by adding to a predetermined voltage.

According to the first aspect of the invention, since the frequency of the pumping pulse in the test mode is higher than that in the normal mode, the charge pump is performed at a higher speed in the test mode by the charge pump circuit. It is possible to sufficiently compensate for the current consumption of the voltage, thereby preventing the internal power supply voltage from decreasing in the test mode,
This has the effect of improving the reliability of the high-speed test.

According to the second aspect of the present invention, a high-speed test function having a test mode which operates at an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and can perform a test faster than in a normal mode. In the integrated semiconductor integrated circuit, the internal booster circuit includes a plurality of inverters connected in a ring shape in the normal mode, and a part of the plurality of inverters is bypassed by wiring in the test mode to reduce the number of inverter stages. A ring oscillator that generates a clock as a pumping pulse, a pumping capacitor that is charged with the pumping pulse, and adds the charged voltage of the pumping capacitor to a predetermined voltage to generate the internal power supply voltage; Having.

According to the second aspect, in the test mode, a part of the plurality of inverters constituting the ring oscillator is bypassed by the wiring, and the clock frequency becomes higher than in the normal mode. The same effect as the effect of the first invention is obtained. According to the third aspect of the present invention, a semiconductor integrated circuit with a high-speed test function is provided, which operates with an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and is capable of performing a test faster than in the normal mode. In the circuit, the internal boosting circuit includes a clock generation circuit that generates a clock as a pumping pulse, and a first value when the capacitance is in the normal mode and the first value is in the test mode.
A pumping capacitor that is switched to a second value greater than a value, the pumping pulse charges the pumping capacitor, and adds the charged voltage of the pumping capacitor to a predetermined voltage to generate the internal power supply voltage And a charge pump circuit.

According to the third aspect of the invention, the capacity of the pumping capacitor is increased in the test mode as compared with the normal mode, and the amount of charge charged to the pumping capacitor is increased for each pumping pulse. Since the current supply capability of the circuit is increased, the same effects as those of the first invention can be obtained. According to the fourth aspect of the present invention, a semiconductor integrated circuit with a high-speed test function is provided which operates with an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and is capable of performing a test faster than in a normal mode. In the circuit, the internal booster circuit includes a plurality of inverters connected in a ring in the normal mode, a part of the plurality of inverters is bypassed by wiring in the test mode, the number of stages of the inverter is reduced, and As a pumping pulse, and a pumping capacitor whose capacitance is switched to a first value in the normal mode and to a second value larger than the first value in the test mode. The pumping capacitor is charged, and a voltage of the charged pumping capacitor is added to a predetermined voltage, and Having a charge pump circuit for generating a source voltage.

According to the fourth aspect, in the test mode, the frequency of the clock output from the ring oscillator increases compared to the normal mode, and the capacity of the pumping capacitor of the charge pump circuit increases compared to the normal mode. Therefore, there is an effect that the current compensation capability of the internal power supply voltage is larger than in the case of the second or third invention.

In the first aspect of the first to fourth inventions, the semiconductor integrated circuit with a high-speed test function is a semiconductor memory device, and a plurality of word lines are simultaneously selected in the test mode. The internal power supply voltage is supplied to a word line via a word driver.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a schematic configuration of a semiconductor integrated circuit with a high-speed test function according to a first embodiment of the present invention.

This semiconductor integrated circuit includes an internal boosting circuit and another circuit 1 as in FIG. 5, and the circuit 1 includes an external power supply voltage Vcc and an internal power supply voltage Vp obtained by boosting the same.
Works with p. In the booster circuit, one of the output of the ring oscillator 10 and the output of the ring oscillator 30 is selected by the selection circuit 40 in response to the mode signal TEST supplied to the external terminal, and is supplied to the charge pump circuit 20 via the inverter 50. Supplied. The ring oscillator 10
Inverters 11 to 17 are connected in a ring shape, and ring oscillator 30 has inverters 31 to 33 connected in a ring shape. The ring oscillator 30 is the ring oscillator 1
Since the number of inverter connection stages is smaller than 0, the frequency of the clock generated by the ring oscillator 30 is higher than that of the ring oscillator 10.

The selection circuit 40 includes transfer gates 41 and 42.
Are connected to the output terminals of the ring oscillators 10 and 30, respectively, and the other ends of the transfer gates 41 and 42 are connected to the input terminal of the inverter 50. Each of the transfer gates 41 and 42 has a configuration in which an nMOS transistor and a pMOS transistor are connected in parallel.
The mode signal TEST is applied to the gate of the pMOS transistor 1 and the gate of the nMOS transistor of the transfer gate 42.
Is supplied to the gate of the nMOS transistor of the transfer gate 41 and the gate of the pMOS transistor of the transfer gate 42. The signal obtained by inverting the mode signal TEST by the inverter 43 is supplied.

The charge pump circuit 20 has the same configuration as that of FIG. 5, and the output of the inverter 50 is supplied to the analog changeover switch 24. The circuit 1 is, for example, a DRAM as described above. In the test mode, a plurality of word lines driven by the internal power supply voltage Vpp are simultaneously selected in order to reduce the test time, and the system clock cycle is set to a minimum allowable value. , The current consumption of the internal power supply voltage Vpp becomes larger than in the normal mode.

In the above configuration, when the mode signal TEST is at a low level in the normal mode, the transfer gate 41 is turned on, the transfer gate 42 is turned off, and the ring oscillator 1 is turned off.
The clock generated at 0 is selected by the selection circuit 40 and supplied to the charge pump circuit 20 via the inverter 50 as a pumping pulse. When the output of the inverter 16 is at a low level, the analog changeover switches 24 and 25 are in the state shown in the figure, and the pumping capacitor 21 is charged with the output of the inverter 17. 24 and 25 are switched, and the voltage between the terminals of the pumping capacitor 21 is added to the external power supply voltage Vcc. Such an operation is repeated, and voltage Vpp = 2 (Vcc−2Vth)
Is generated by the charge pump circuit 20. Where Vt
h is the threshold value of the diode. For example, Vcc = 3.
3V, Vth = 0.7V, and at this time, Vpp = 5.
2V.

When the mode signal TEST is at a high level in the test mode, the transfer gate 41 is turned off and the transfer gate 4 is turned off.
2 is turned on, the clock generated by the ring oscillator 30 is selected by the selection circuit 40, and is supplied to the charge pump circuit 20 as a pumping pulse via the inverter 50. Since the pumping pulse in the test mode has a higher frequency than that in the normal mode, the charge is pumped faster in the charge pump circuit 20, and the voltage Vpp sufficiently compensates for the current consumed in the circuit 1. Thus, the voltage Vpp in the test mode is prevented from lowering, and the reliability of the high-speed test is improved.

[Second Embodiment] FIG. 2 shows a schematic configuration of a semiconductor integrated circuit with a high-speed test function according to a second embodiment of the present invention. In this booster circuit, the ring oscillator 10A includes a first unit 10a, a second unit 10b, a third unit 10c, and a selection circuit 40A. The first part 10a includes the inverter 1
1 to 13 are connected in cascade. In the second part 10b, an inverter 14 and an inverter 15 are cascade-connected, and a smaller inverter 18 is circularly connected to the inverter 14. In the third part 10c, the inverter 16 and the inverter 17 are connected in cascade. The output terminal of the inverter 15 is connected to the input terminal of the inverter 16 and the inverter 1
The output terminal of the inverter 7 is connected to the input terminal of the inverter 11.

In the selection circuit 40, the transfer gate 41 is connected between the output terminal of the inverter 13 and the input terminal of the inverter 14, and the transfer gate 42 is connected between the output terminal of the inverter 13 and the output terminal of the inverter 15. Have been. The on / off of the transfer gates 41 and 42 is determined by the mode signal TEST
1 and a signal obtained by inverting the inverted signal by the inverter 43, FIG.
Is controlled in the same manner as in the case of

When the transfer gate 41 is turned off, the input end of the inverter 14 becomes floating near the potential Vcc / 2, and the inverter 18 receives a current flowing from the power supply line to the ground line. This is to prevent it. Other points are the same as the first embodiment. In the above configuration, when the mode signal TEST is at a low level in the normal mode, the transfer gate 41 is turned on, the transfer gate 42 is turned off, and the first unit 10a, the second unit 10b, and the third
A ring oscillator having seven stages of inverters is constituted by the unit 10c, and operates in the same manner as the ring oscillator 10 of FIG.

When the mode signal TEST is at a high level in the test mode, the transfer gate 41 is turned off and the transfer gate 4 is turned off.
2 is turned on, the output terminal of the inverter 13 is bypassed to the input terminal of the inverter 16 via the transfer gate 42,
A ring oscillator having five stages of inverters is configured, and the clock frequency is higher than in the normal mode. Thereby, the same effect as the effect described in the first embodiment can be obtained.

Third Embodiment FIG. 3 shows a schematic configuration of a semiconductor integrated circuit with a high-speed test function according to a third embodiment of the present invention. In this booster circuit, the capacity of the pumping capacitor can be switched according to the mode.

That is, the pumping capacitor 26 is connected to the positive terminal of the pumping capacitor 21 which is an electrolytic capacitor.
Of the pumping capacitor 26 is connected to the negative terminal of the pumping capacitor 26 via the transfer gate 27.
Is connected to the negative terminal of the. NMOS of transfer gate 27
The mode signal TEST and a signal obtained by inverting the mode signal TEST by the inverter 28 are supplied to the gates of the transistor and the pMOS transistor, respectively.

The other points are the same as those in FIG. In the above configuration, when the mode signal TEST is at a low level in the normal mode, the transfer gate 27 is turned off, and the operation is the same as that in FIG. When the mode signal TEST is high and the test mode is set, the transfer gate 27 is turned on,
The pumping capacitor 21 is connected to the pumping capacitor 21.
Are connected in parallel. As a result, the amount of charge charged to the pumping capacitor for each pumping pulse is increased as compared with the case of the normal mode, the current supply capability of the charge pump circuit 20A is increased, and the same effect as described in the first embodiment is obtained. The effect is obtained.

Fourth Embodiment FIG. 4 shows a schematic configuration of a semiconductor integrated circuit with a high-speed test function according to a fourth embodiment of the present invention. In this booster circuit, the ring oscillator 10A shown in FIG.
And the charge pump circuit 20A of FIG.

The operation in the normal mode is the same as that in FIG. In the test mode, the frequency of the clock output from the ring oscillator 10A is increased and the charge pump circuit 2
Due to the increase in the capacity of the pumping capacitor of 0 A, the internal power supply voltage Vp is higher than that of the second embodiment or the third embodiment.
The current compensation capability of p increases.

The present invention includes various other modifications. For example, the circuit 1 only needs to have a test mode that operates at an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage and can perform a test at a higher speed than in the normal mode. . Various types of charge pump circuits can be used.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit with a high-speed test function according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a semiconductor integrated circuit with a high-speed test function according to a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a semiconductor integrated circuit with a high-speed test function according to a third embodiment of the present invention.

FIG. 4 is a schematic configuration diagram of a semiconductor integrated circuit with a high-speed test function according to a fourth embodiment of the present invention.

FIG. 5 is a schematic configuration of a conventional semiconductor integrated circuit with a high-speed test function.

FIG. 6 is a diagram showing a main configuration of the circuit 1 of FIG. 5;

[Explanation of symbols]

 10, 10A Ring oscillator 11-18, 28, 41-43, 50 Inverter 20, 20A Charge pump circuit 21, 26 Pumping capacitor 22, 23 Diode 24, 25 Analog switch 27, 41, 42 Transfer gate TEST Mode signal Vcc External Power supply voltage Vpp Internal power supply voltage

Claims (5)

[Claims] 1. A semiconductor integrated circuit with a high-speed test function which operates at an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and has a test mode capable of performing a test faster than in a normal mode. In the circuit, the internal booster circuit includes: a first clock generation circuit that generates a first clock; a second clock generation circuit that generates a second clock having a frequency higher than the first clock; A selection circuit for selecting one clock and supplying the same as the pumping pulse to the charge pump, and selecting the second clock and supplying the same as the pumping pulse to the charge pump in the test mode; and a pumping capacitor charged by the pumping pulse; A charge pump for adding the charged voltage of the pumping capacitor to a predetermined voltage to generate the internal power supply voltage The semiconductor integrated circuit with high-speed test function characterized by having and circuitry. 2. A semiconductor integrated circuit having a high-speed test function, which operates at an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and has a test mode capable of performing a test faster than in a normal mode. In the circuit, the internal booster circuit includes a plurality of inverters connected in a ring shape in the normal mode, and a part of the plurality of inverters is bypassed by wiring in the test mode to reduce the number of stages of the inverter;
A ring oscillator that generates a clock as a pumping pulse, and a charge pump circuit that charges a pumping capacitor with the pumping pulse and adds the charged voltage of the pumping capacitor to a predetermined voltage to generate the internal power supply voltage. A semiconductor integrated circuit with a high-speed test function. 3. A semiconductor integrated circuit having a high-speed test function, which operates at an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and has a test mode in which a test can be performed faster than in a normal mode. In the circuit, the internal booster circuit includes: a clock generation circuit that generates a clock as a pumping pulse; and a capacitor that has a first value in the normal mode and a second value larger than the first value in the test mode. A charge pump circuit that includes a pumping capacitor that can be switched, the pumping capacitor is charged with the pumping pulse, and a voltage of the charged pumping capacitor is added to a predetermined voltage to generate the internal power supply voltage. Semiconductor integrated circuit with high-speed test function. 4. A semiconductor integrated circuit having a high-speed test function, which operates at an external power supply voltage and an internal power supply voltage obtained by boosting the external power supply voltage by an internal booster circuit, and has a test mode in which a test can be performed faster than in a normal mode. In the circuit, the internal booster circuit includes a plurality of inverters connected in a ring shape in the normal mode, and a part of the plurality of inverters is bypassed by wiring in the test mode to reduce the number of stages of the inverter;
A ring oscillator that generates a clock as a pumping pulse; and a pumping capacitor whose capacity is switched to a first value in the normal mode and to a second value larger than the first value in the test mode. A charge pump circuit that charges the pumping capacitor and adds the charged voltage of the pumping capacitor to a predetermined voltage to generate the internal power supply voltage. 5. The semiconductor integrated circuit with high-speed test function is a semiconductor memory device, wherein a plurality of word lines are simultaneously selected in the test mode, and the internal power supply voltage is applied to the selected plurality of word lines. The semiconductor integrated circuit with a high-speed test function according to claim 1, wherein the semiconductor integrated circuit is supplied via a driver.