KR100218247B1 - High voltage generator - Google Patents

Abstract

The present invention relates to a high voltage generator for providing a high voltage higher than the chip internal power supply voltage. According to the present invention, each of the first and second high voltage kickers for generating a high voltage for a predetermined purpose during operation of the semiconductor memory device, and the first and second control pulses for sensing the high voltage to maintain the generation of the high voltage, respectively. A first pulse to enable only the second high voltage kicker in a standby state and connected to an output terminal of the first and second high voltage detectors; A logic circuit for outputting a second pulse for enabling the second high voltage kicker; A first oscillator connected between an output terminal of the first high voltage detector and an input terminal of the first high voltage kicker and outputting a pulse of a predetermined period; A second oscillator is connected between the output terminal of the logic circuit and the work terminal of the second high voltage kicker and outputs a pulse of a constant period, thereby generating a high voltage dip in the activation mode while overcoming the limitation of the layout area. It can be suppressed.

Description

High voltage generator

The present invention relates to a semiconductor memory device, and more particularly, to a high voltage generator for providing a high voltage higher than a chip internal power supply voltage.

In general DRAM, one transistor and one capacitor structure are integrated to store data, and the transistor used here is mainly an EnMOS transistor, and when reading high-level data of a cell, To overcome the threshold voltage drop, a bias higher than the voltage level used in the array is used. Of course, not only the cell but also some NMOS transistors used in the peripheral circuit use a bias higher than the voltage level of the peripheral circuit.

As such, in general, the low-address signal or the TTL-level clock is activated in a manner used to make a higher bias than the voltage level used, and a predetermined blasting operation is performed by an artificial pumping capacitor after a predetermined time delay. High bias is generated only during the interval and the pump is periodically repeated from the power-on state by the oscillator to generate a certain level of DC bias, which is used as a power source when needed. There is a way. The DC bias generated in the latter case is referred to as VPP, and a block diagram of a conventional high voltage generator is shown in FIG.

1 is a specific circuit diagram of a high voltage generator constructed in accordance with one embodiment of the prior art. Referring to FIG. 1, the high voltage generator detects the VPP level while the device is in the Stand-By state from the time of power-on to generate and maintain a predetermined VPP level. And a dashed high voltage kicker 103 composed of capacitors necessary for pumping and a standby oscillator 102 for driving the high voltage kicker 103 periodically to generate a DC level. The standby high voltage generator is operated in a long cycle in consideration of the standby current (Stand_by current), so the pumping efficiency is inferior to the active high voltage generator.

The high voltage detector 101, the oscillator 102, and the high voltage kicker 103 described above are divided into standby and active states to limit the standby current, and when used for driving large loading in an activation cycle. In order to supply the resulting charge consumption immediately, an activation high voltage kicker with a large pumping capacitor is used. In addition, an activation high voltage detector is used to prevent the VPP level from being boosted to a level higher than necessary in the activation cycle, and compared to the standby oscillator 102 for compensation of the VPP level when the VPP level is down in the long cycle. A short cycle activation oscillator will be used. The activating high voltage kicker 103 may input the low address signal as an input so that it can be driven once when the low address signal is active or precharged regardless of the high voltage level VPP.

Noise generation of high voltage power lines is a problem due to VPP dip caused by the charge consumption generated when driving large loads such as word lines, and its rapid recovery ensures stable characteristics when the device is operated in short cycles. For this purpose, the pumping capacitor used in the high voltage kicker 103 for activation is inevitably as large as possible. However, the size of the pumping capacitor can no longer be largely related to the area of the device, which is solved by minimizing VPP loading.

Second (a) degree FIG. 2 (c) shows a detailed circuit diagram of the high voltage detector 101, the oscillator 102 and the high voltage kicker 103 shown in FIG.

The high voltage detector 101 is shown in FIG. 2 (a). This circuit uses a high voltage VPP as input and cuts or transistors 201 of fuses F1 ?? F4. A circuit driven by a method of passing a power supply voltage through 211.

An oscillator 102 is shown in FIG. 2 (b), and the oscillator 102 is for outputting a pulse VPPOSC of a predetermined period by inputting the output signal φVPP of the high voltage detector 102, and the NAND gate ( 213) and inverters 214 218, 223, 224 and transistors 219 222.

A detailed circuit diagram of the high voltage kicker 103 is shown in FIG. 2 (c). The high voltage kicker 103 inputs VPPOSC as an input to provide a high voltage VPP by a charge pumping operation. A pulse generator comprising inverters 225 and 226, a NOA gate 227, and a NAND gate 228, and inverters 229, 230 and 234 which use an output signal of the NOA gate 227 as an input. A first pumping circuit composed of 236, capacitors 231, 237, and transistors 232, 233, and 238, 239, and inverters 240 for inputting an output signal of the NAND gate. (242), (246) And a second pumping circuit composed of 248, capacitors 243, 249, and transistors 244, 245, and 250, 251.

Accordingly, an object of the present invention is to provide a high voltage generator capable of suppressing the generation of a high voltage dip in an activation mode while overcoming the limitation of the layout area.

1 is a block diagram of a high voltage generator implemented according to one embodiment of the prior art.

Second (a) degree FIG. 2 (c) is a detailed circuit diagram of the block diagram shown in FIG.

3 is a block diagram of a high voltage generator implemented in accordance with an embodiment of the invention.

Hereinafter, the detailed description of the preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

3 is a block diagram of a high voltage generator implemented in accordance with an embodiment of the invention.

Referring to FIG. 3, the semiconductor memory device may generate a high voltage VPP during a predetermined operation, for example, to perform a program operation, a read operation, and an operation for supplying a peripheral circuit using a high voltage. Active and standby high voltage kickers 303 and 306, and active and standby high voltage detectors 301 and 304 respectively providing first and second control pulses for sensing the high voltage VPP and maintaining the generation of the high voltage VPP. Is connected to the output terminals of the high voltage detectors 301 and 304 for the activation and standby state, and outputs a first pulse for enabling only the high voltage kicker 306 for the standby state in the standby state, and the activation and standby state in the activated state. Logic circuits 307 and 308 for outputting second pulses for enabling the high voltage kickers 303 and 306, and the high voltage detector 301 for the activation state. An active state oscillator 302 connected between an output terminal and an input terminal of the high-voltage kicker 303 for an activation state and outputting a pulse of a predetermined period, and an output terminal of the logic circuits 307 and 308 for the standby state. It is comprised between the oscillator 305 for standby states connected between the input terminals of the high voltage kicker 306, and outputting a pulse of a fixed period.

In the present invention, when the high voltage kicker 303 for the active state is pumped by the low address signal or by the high voltage detectors 301 and 304 in the activation cycle, the high voltage kicker 306 for the standby state is also driven to improve the pumping efficiency. In order to improve, the high voltage kicker 303 driving signal for the active state is also input to the high voltage kicker 306 for the standby state by using a logic circuit (a circuit composed of the noar gate 307 and the inverter 308).

In the power-on and standby states, only the standby high voltage kicker 306 operates, and when the VPP charge is consumed in the activation cycle, e.g., when the word line is enabled, the active high voltage kicker 303 is used to replenish the charge. When it is to be driven, the output signal of the active state detector 301 and the oscillator 302 also drives the high-state kicker 36 for standby in addition to the high-voltage kicker 303 for the active state to obtain the effect of increasing the actual active high voltage pumping capacitance. Benefits can be gained in terms of layout area.

As described above, according to the present invention, the effect of suppressing the generation of the high voltage dip in the activation operation mode is obtained while overcoming the limitation of the layout area.

Claims (3)

A high voltage generator of a semiconductor memory device; First and second high voltage kickers for generating a high voltage in order to achieve a predetermined purpose during operation of the semiconductor memory device; First and second high voltage detectors respectively sensing the high voltage and providing first and second control pulses for maintaining the generation of the high voltage; A second pulse connected to an output terminal of the first and second high voltage detectors to output a first pulse for enabling only the second high voltage kicker in a standby state, and to enable the first and second high voltage kickers in an activated state A logic circuit for outputting a pulse; A first oscillator connected between an output terminal of the first high voltage detector and an input terminal of the first high voltage kicker and outputting a pulse of a predetermined period; And a second oscillator connected between an output terminal of the logic circuit and an input terminal of the second high voltage kicker and outputting a pulse of a predetermined period. 2. The high voltage generator of claim 1, wherein the capacity of the pumping capacitor in the first high voltage kicker is greater than the capacity of the pumping capacitor in the second high voltage kicker. The high voltage generator as claimed in claim 1, wherein the logic circuit comprises a noah gate having the first and second control pulses as an input and an inverter having the output signal of the noah gate as an input.