JP2828942B2 - Semiconductor memory booster circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a booster circuit for generating a boosted voltage Vpp in a low power consumption type highly integrated semiconductor memory.

[0002]

2. Description of the Related Art Most semiconductor chips are provided with a booster circuit in order to compensate for a reduction in efficiency such as word line driving as semiconductor memories become more highly integrated and consume less power. The boosted voltage Vpp thus generated is a voltage (potential) higher than the power supply voltage Vcc used inside the semiconductor memory, and is used to prevent a reduction in the word line drive voltage due to the lowering of the memory voltage. That is, in a DRAM in particular, a voltage sufficient for forming a voltage difference necessary for sensing by charge distribution between the memory cell and the bit line when reading data (especially data "1") stored in the memory cell. To the word line to turn on the cell transistor sufficiently. This effect is becoming difficult to obtain with the power supply voltage Vcc, which tends to lower the voltage, and recently, at least Vcc +
The boosted voltage Vpp at a level equal to or higher than Vth (Vth is, for example, the threshold voltage of the cell transistor) is used.

A general method for generating such a boosted voltage Vpp is as follows. In the standby state (standby cycle) of the semiconductor memory, the required minimum boosted voltage Vpp is generated by the boosting action of the small-capacity standby booster circuit, and in the active state (active cycle), it is consumed in the cycle. The boosting is performed by an activation boosting circuit having a large capacity enough to make up for a certain amount of power. FIG.
FIG. 2 is a block diagram showing such a booster circuit.

A chip master clock generation circuit 1 generates a chip master clock φR in response to a row address strobe signal RASB (B means inversion). For example, the boost control circuit 2 waits using the chip master clock φR. A cycle and an active cycle are determined, and a boost control signal φPC is generated for each of these cycles. The activation booster circuit 3 is controlled by the booster control signal φPC.
In addition, the boosting function of the standby booster circuit 4 is caused to function. Figure 2
As can be seen by referring to the signal waveforms and the detailed circuits shown in FIG. 5, the activation booster circuit 3 and the standby booster circuit 4 operate complementarily according to the boost control signal φPC, and are active in the active cycle in which the signal RASB is in the low state. The booster circuit 3 boosts the boosted voltage Vpp, and the standby booster circuit 4 boosts the boosted voltage Vpp in a standby cycle in which the signal RASB is high.

More specifically, in the activation booster circuit 3 shown in FIG.
While boost control signal φPC is in a low state (standby cycle), MOS capacitor 7 boosts node 5, and this is transmitted to node 6 through diode NMOS transistor 10 for transmission. And the boost control signal φ
When the PC changes from the low state to the high state (active cycle), the potential of the node 6 is generated as the boosted voltage Vpp through the NMOS transistor 11 while being boosted again by the MOS capacitor 12. Standby booster circuit 4 shown in FIG.
In this case, the logic of the boost control signal φPC is used in reverse.

[0006]

In the above booster circuit, the capacity of the activation booster circuit 3 should be set such that the amount of power consumed for each active state can be accurately detected and a corresponding power supply can be performed. is there. However, in the configuration shown in FIG. 1, it is difficult to accurately match the power consumption with the booster circuit capacity. If the booster circuit capacity is larger than the power consumption, problems such as excessive current consumption and a high electric field are caused, and the reliability is reduced. Could lead to

Therefore, the present invention provides a booster circuit capable of generating a boosted voltage corresponding to the power consumption in an active state. Further, the present invention provides a booster circuit capable of suppressing current consumption.

[0008]

According to the present invention, a boosting control circuit for determining a standby state and an active state and generating a complementary boosting control signal for each of these states, and boosting according to the boosting control signal A standby booster circuit and an active booster circuit;
A booster circuit of a semiconductor memory comprising: a sense control circuit that determines a standby state and an active state, generates a sense control signal at the beginning of the active state, and generates a latch control signal during generation of the sense control signal; A boosting voltage sensing circuit for sensing a level of the boosted voltage in response to the sensing control signal and latching the sensing result in response to the latch control signal to generate a sensing signal. Circuit
The boosting is performed according to the boosting control signal and the sensing signal. At this time, the standby booster circuit can also perform boosting according to the boosting control signal and the sensing signal.

In the case of a DRAM, it is sufficient to use the chip master clock corresponding to the row address strobe signal as described above to determine the standby state and the active state, and the boosting control circuit and the sensing control circuit operate in accordance with the chip master clock. Good. Also, the boost control signal and the sensing signal may be adjusted to be generated at the same timing in the active state, or may be generated at the start of the next active state by storing the sensing signal once. Once the sensing signal is stored, it can be easily performed simply by using a general register connected to the boosted voltage sensing circuit. If the chip master clock is used, the register stores and outputs the sensing signal according to the chip master clock. You should be able to do so.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 6 is a block diagram showing an embodiment of a booster circuit according to the present invention. A chip master clock generating circuit 1 for generating a chip master clock φR in response to a row address strobe signal RASB; a standby state (standby cycle) and an active state (active cycle) are determined based on the chip master clock φR; A sensing control circuit 20 for generating a sensing control signal φDET and a latch control signal φLAT; a sensing boosting circuit 40 for sensing the level of the boosted voltage Vpp and controlling the sensing signal φPD by controlling the sensing control signal φDET and the latch control signal φLAT; A boosting voltage sensing circuit 30 provided to the boosting circuit 60 for use, a boosting control circuit 50 that determines a standby cycle and an active cycle based on a chip master clock φR to generate a boosting control signal φPC, and a boosting control signal φPC and a sensing signal φPD. Active booster circuit for boosting boosted voltage Vpp by control 40 and a standby booster circuit 60 are used.

FIG. 7 shows a specific example of the sensing control circuit 20.
The sense control signal φDET inputs the chip master clock φR to a pulse shaping circuit including a NAND gate ND31 and an odd number of inverters I21 to I25 connected in series connected to one input terminal of the NAND gate ND31. The output is generated by inverting the output by an inverter I26. The latch control signal φLAT is
An odd number of directly connected inverters I27 connected to one input terminal of the ND gate ND32 and the NAND gate ND32
The clock signal is generated by inputting the chip master clock φR to a pulse shaping circuit consisting of .about.I29 and passing the output of this pulse shaping circuit to serially connected inverters I30-I32.

FIG. 8 shows a specific example of the boosted voltage sensing circuit 30. N provided between the power supply voltage Vcc and the sensing node 31
The boosted voltage Vp is applied to the gate electrode of the MOS transistor N31.
p has been entered. Also, an NMOS transistor N32 and an NMOS transistor N33 are provided in series from the sensing node 31 to the ground voltage Vss, and a sensing control signal φDET is applied to the gate electrode of the NMOS transistor N32.
The boosted voltage V is applied to the gate electrode of the NMOS transistor N33.
pp are input. Sensing node 31 is connected to node 32 via transmission gate T31. The latch control signal φLAT is applied to the N-type control electrode of the transmission gate T31.
, And the latch control signal φLAT is inverted and input to the P-type control electrode by the inverter I33. A latch circuit including inverters I34 and I35 connected in series is connected to the node 32, and a sense signal φPD is generated from the node 32 via the inverter I36.

FIG. 9 shows a specific example of the activation booster circuit 40. The activation booster circuit 40 has the same configuration as the activation booster circuit 3 of FIG. 4 described above, except that the booster control signal φPC
Gate ND41 for inputting a sensing signal φPD
And an inverter I41 for inverting the output of the NAND gate ND41. FIG. 10 shows a specific example of the boost control circuit 50, which includes inverters I51 to I51 connected in series.
56. The reason why the number of inverters is increased as compared with the conventional example shown in FIG. 3 is that the boosting circuits 40 and 60 are operated after the detection signal φPD is generated by the boosted voltage sensing circuit 30, that is, the timing is adjusted. FIG.
Shows a specific example of the standby booster circuit 60. The standby booster circuit 60 operates complementarily to the active booster circuit 40. Therefore, instead of the inverter I4 of the standby booster circuit 4 in FIG. 5, a NAND gate ND61 for inputting the boost control signal φPC and the sensing signal φPD is provided. used.

FIG. 12 is a waveform diagram of a main part signal in the above circuit, and shows a timing when the boosted voltage Vpp changes from a level lower than the reference value to a higher level.

At time t1, signal RASB changes from a high state to a low state, and in response to this, chip master clock φ
When R goes high at time t2, the sensing control signal 20 generates a pulse that goes high from time t3 due to pulse shaping by the sense control circuit 20, and then the latch control signal φLAT goes high from time t4. Generated as a pulse.

In the boosted voltage sensing circuit 30, the signal R
During a standby cycle in which ASB is high, the sense control signal φ
Since the DET and the latch control signal φLAT are in a low state, the potential of the sensing node 31 becomes the NMOS transistor N3
1, the power supply voltage Vcc is precharged, and the transmission gate T31 is off. Then, when the active cycle starts and the high pulse of the sensing control signal φDET is applied to the gate electrode of the NMOS transistor N32 at time t3, the potential of the sensing node 31 is affected according to the level of the boosted voltage Vpp. That is, the boost voltage Vp
When the level of p is high, the potential of the sensing node 31 is high, and when the level of the boosted voltage Vpp is low, the potential of the sensing node 31 is low. Thereafter, at time t4, when the latch control signal φLAT goes high, the transmission gate T31 turns on. When the level of the boosted voltage Vpp is high, the sensing signal φPD is low, and when the level of the boosted voltage Vpp is low, The sensing signal φPD is generated in a high state. After the latch control signal φLAT returns to the low state, the transmission gate T31 is turned off.
4, I35. The reason why the sensing control signal φDET and the latch control signal φLAT are pulsed in this way is to prevent unnecessary power consumption by operating the boosted voltage sensing circuit 30 only during the active cycle necessary for sensing the level of the boosted voltage Vpp. That's why.

The activation booster circuit 40 can be boosted when the signal RASB transitions from a high state to a low state, and the standby booster circuit 60 can be boosted when the signal RASB transitions from a low state to a high state. When the boosted voltage Vpp is at a high level, the sense signal φPD is applied in a low state, so that each of the boosting circuits 40 and 60 applies the boosted voltage Vpp.
, And when the boosted voltage Vpp is at a low level, the sensing signal φPD is applied in a high state. Therefore, the boosting circuits 40 and 60 are alternately switched according to a boosting control signal φPC toggled by the signal RASB. A boost is performed. That is, the boosted voltage Vp in the active cycle
Only when the level of p decreases, the boosting function of the booster circuit functions to compensate for the decrease. Therefore, the generation of the boosted voltage more than necessary is suppressed, and the boosted voltage can be generated according to the power consumption of the active cycle. Moreover,
Unnecessary circuit operations are kept to a minimum, which leads to suppression of current consumption. However, as described above, since the standby booster circuit 60 has a minimum necessary small capacity, the sensing signal φ
The same advantage can be obtained even when the control by the PD is performed only by the activation booster circuit 40. The operation of each of the booster circuits 40 and 60 is the same as in the above-described conventional case.

FIG. 13 is a block diagram showing another embodiment of the booster circuit. This embodiment has a configuration in which a register 70 is further arranged between the boosted voltage sensing circuit 30 shown in FIG. That is, the sensing signal φPD generated from the boosted voltage sensing circuit 30 is applied to each of the boosting circuits 40 and 60 after passing through the register 70.

The register 70 is, as shown in FIG. 14, a normal shift register composed of transmission gates T71 and T72 whose transmission is controlled by the chip master clock φR and inversion latches L71 and L72. This register 7
0, the transmission gate T71 is turned on while the chip master clock φR is in the low state, and the sensing signal φP generated from the boosted voltage sensing circuit 30 in the previous active cycle.
D is stored in the inverting latch L71. When the chip master clock φR goes high, the transmission gate T72
Turns ON and the storage content of the inversion latch L71 is changed to the inversion latch L
72, and is output as a signal φSPD. Thereafter, when the chip master clock φR goes low again, the transmission gate T71 turns on and the transmission gate T72 turns off,
The stored content of the inverting latch L71 is the sensing signal φP at that time.
D. That is, register 70 has a role of determining the boosting action of each booster circuit 40, 60 in the current active cycle according to sensing signal φPD set in the immediately preceding active cycle.

As shown in FIGS. 15 and 16, the signal φSPD is replaced with NAND gates ND41 and ND41 instead of the sensing signal φPD in each of the boosting circuits 40 and 60 in FIGS.
It is input to D61. Further, as shown in FIG. 17, the boost control circuit 80 includes two inverters I81,
I82. That is, by using the register 70, the sense signal φ is changed like the boosting control circuit 50 of FIG.
Six inverters for adjusting to the PD generation timing are not required. This leads to a longer operation time of the booster circuit in the active cycle than in the booster circuit of FIG.

As can be seen from FIG. 18 showing the operation timing of the booster circuit of FIG. 13, boosted voltage Vpp which has become low in the active cycle starts boosting from the beginning of the next active cycle. . Thus, even if the booster circuit 40 operates with a delay of about one cycle, the boosted voltage Vpp has a large load characteristic, so that a sufficient effect can be obtained.

[0023]

As described above, according to the present invention, it is possible to provide a booster circuit for boosting the boosted voltage Vpp in accordance with the consumption in the active state, so that excessive supply of the boosted voltage in the active state can be accurately performed. This makes it possible to generate a boosted voltage consistent with the amount of power consumption in the active state, and also to suppress current consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional booster circuit.

FIG. 2 is a waveform diagram of signals used in the circuit of FIG.

FIG. 3 is a circuit diagram of a boost control circuit 2 in FIG. 1;

FIG. 4 is a circuit diagram of an activation booster circuit 3 in FIG. 1;

FIG. 5 is a circuit diagram of a standby booster circuit 4 in FIG. 1;

FIG. 6 is a block diagram showing an embodiment of a booster circuit according to the present invention.

FIG. 7 is a circuit diagram of the sensing control circuit 20 in FIG. 6;

FIG. 8 is a circuit diagram of a boosted voltage sensing circuit 30 in FIG. 6;

FIG. 9 is a circuit diagram of an activation booster circuit 40 in FIG. 6;

FIG. 10 is a circuit diagram of a boost control circuit 50 in FIG. 6;

FIG. 11 is a circuit diagram of a standby booster circuit in FIG. 6;

FIG. 12 is a waveform chart of a signal used in the circuit of FIG. 6;

FIG. 13 is a block diagram showing another embodiment of the booster circuit according to the present invention.

FIG. 14 is a circuit diagram of a register 70 in FIG.

FIG. 15 is a circuit diagram of an activation booster circuit 40 in FIG. 13;

FIG. 16 is a circuit diagram of a standby booster circuit 60 in FIG. 13;

17 is a circuit diagram of the boost control circuit 80 in FIG.

FIG. 18 is a waveform diagram of signals used in the circuit of FIG.

[Explanation of symbols]

 1 Chip Master Clock Generation Circuit 2, 50, 80 Boost Control Circuit 3, 40 Boost Circuit for Activation 4, 60 Standby Boost Circuit 20 Sensing Control Circuit 30 Boost Voltage Sensing Circuit 70 Register φR Chip Master Clock φPC Boost Control Signal φPD Sensing Signal φDET sensing control signal φLAT Latch control signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/40-11/409

Claims (6)

(57) [Claims] 1. A boosting control circuit for distinguishing between a standby state and an active state and generating a complementary boosting control signal for each of these states, a standby boosting circuit and an active boosting circuit for performing boosting according to the boosting control signal. in the booster circuit of a semiconductor memory with a pulse at the beginning of the active state to determine the standby state and an active state
A sensing control signal having a pulse shape, and a pulse width of the sensing control signal.
A sense control circuit for generating a latch control signal therein, a boost voltage for sensing a level of the boosted voltage in response to the sense control signal, and latching the sensing result in response to the latch control signal to generate a sense signal A booster circuit for activation, wherein the booster circuit for activation performs boosting in accordance with the booster control signal and the sense signal. 2. The booster circuit according to claim 1, wherein the standby booster circuit also boosts the voltage in accordance with the boost control signal and the sense signal. 3. The boosting circuit according to claim 1, wherein the boosting control signal and the sensing signal are generated at the same timing in an active state. 4. The boosting circuit according to claim 1, wherein the boosting control circuit and the sensing control circuit operate according to a chip master clock corresponding to a row address strobe signal. 5. The booster circuit according to claim 1, wherein the sense signal is temporarily stored and generated at the start of the next active state. 6. A boosting control circuit and a sensing control circuit operate according to a chip master clock according to a row address strobe signal, and a register for storing and outputting a sensing signal according to the chip master clock is connected to a boosting voltage sensing circuit. The booster circuit according to claim 5, which is used.