JPH05174591A - Charge pumping circuit - Google Patents

Abstract

PURPOSE:To realize a charge pumping circuit which can supply a sufficiently high VPP level to a VPP terminal of a semiconductor memory. CONSTITUTION:A transistor Q24 for charging a charge pump capacity in a capacitor C26 is forcibly turned ON by a driving circuit 20 having an inverter 120A, a transistor Q27 connected to the inverter 120A via a node 31, and a capacitor C30 connected at one end side to a terminal 22 and at the other to a gate of the transistor Q24 through a node 32. More particularly, the transistor Q24 is forcibly turned ON by a gate punch through capacity of a capacitor C33 to be charged by the transistor Q27 to be controlled by the inverter 120A. Thus, the capacitor C26 can be sufficiently charged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit for generating an internal boosted level (V _PP level) of a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example of this type of charge pump circuit. The circuit configuration will be described below together with the operation. In this charge pump circuit, first, the terminals 11 and 12 are grounded to turn on the transistor Q13, thereby charging the capacitor C15. At this time, the inverter I in which the gate of the transistor Q13 and the power supply are connected
V _PP to the transistor Q14 from 16 through node 17
Since the potential is supplied, the node 17 becomes the V _PP level. On the other hand, the node 1 connecting the capacitor C15 and the transistors Q13 and Q14
8 becomes the V _CC level.

Then, the terminals 11 and 12 are connected to a power source, and the level of the node 18 which is pushed up by the capacitor C15, that is, the electric charge charged in the capacitor C15 is added, is supplied to the V _PP terminal of the semiconductor memory device. To do.

[0004]

By the way, in the conventional charge pump circuit described above, the potential of the node 17 is lowered in a state where the V _PP level at the time of power-on has not reached a sufficiently high level, so that the transistor Q13 is sufficiently charged. It has the drawback of not turning on. Therefore, the charging of the capacitor C15 becomes incomplete, and there is a problem that the V _PP level becomes shallow especially at a low power supply voltage.

The present invention solves the problems of the prior art as described above, and the transistor for charging the charge pump capacitance is forcibly turned on irrespective of the internal boost level V _PP level, resulting in It is an object of the present invention to provide a charge pump circuit capable of supplying a sufficiently high V _PP level to the V _PP terminal of a semiconductor memory device.

[0006]

According to the charge pump circuit of the present invention, in a charge pump circuit for generating an internal boost level of a semiconductor memory device, a first transistor for charging the charge pump capacitance to a first capacitor is connected to V _PP. A driving circuit for forcibly turning on regardless of a level, the driving circuit supplying a voltage to the gate of the first transistor; a gate of the first transistor and a power supply; Connected to an inverter and a second capacitor pushing up the gate of the first transistor, the second capacitor being charged by the second transistor controlled by the inverter The transistor is forcibly turned on, thereby achieving the above object.

[0007]

According to the above structure, the first transistor for charging the charge pump capacitance to the first capacitor is forcibly turned on by the drive circuit regardless of the V _PP level, that is, the second transistor controlled by the inverter. Since the first transistor is forcibly turned on by the gate pushing-up capacitance of the second capacitor charged by the transistor, the first transistor can be reliably turned on.

As a result, the charge pump capacitance is sufficiently charged in the first capacitor, so that the V _PP level can be efficiently generated.

[0009]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows a charge pump circuit of the present invention.
This charge pump circuit includes a drive circuit 20 for forcibly turning on a transistor Q24 for charging the capacitor C26 with a charge pump capacitance regardless of the V _PP level.

The drive circuit 20 includes an inverter I20A formed of transistors Q28 and Q29 whose gates are connected to a terminal 23, and an inverter I2 having a node 31.
A transistor Q27 connected to 0A and a capacitor C30 having one end connected to the terminal 22 and the other end connected to the gate of the transistor Q24 via the node 32. The gate of the transistor Q24 and the inverter I20A are connected to the same power supply.

One end is connected to the transistor Q24,
The terminal 21 is connected to the other end of the capacitor C26 whose charge pump capacitance is charged by the transistor Q24. A transistor Q25 is connected to one end of the capacitor C26, and a V _PP potential is supplied to the transistor Q25 from an inverter I33. The terminal 34 is connected to the input terminal of the inverter I33.

Here, the transistors Q24 and Q29 are n
-MOS transistors, and transistors Q25 and Q
27 and Q28 are p-MOS transistors.

The operation of this charge pump circuit is performed as follows. First, set terminals 21 and 22 to L
It is set to the level (low level) and the terminal 23 is set to the H level (high level). At this time, the node 31 becomes L level and the transistor Q27 is turned on. As a result, the node 32 becomes H level and the capacitor C30 is charged.

Then, the terminal 23 is switched to the L level and the transistor Q28 is turned on. This shorts nodes 31 and 32. After that, the terminal 22 is switched to the H level and the node 32 is pushed up. That is, the capacitor C
The charge charged in 30 is added to node 32. As a result, the transistor Q24 is completely turned on, and the capacitor C
Fully charge 26. At this time, since the node 31 remains short-circuited with the node 32, the transistor Q
27 remains off.

When the charging of the capacitor C26 is completed, the terminal 22 is switched to the L level and the terminal 23 is switched to the H level, whereby the node 31 is switched to the L level and the node 3 is switched.
Set 2 to H level.

Then, after that, the terminal 21 and the terminal 34
Is set to the H level, and the V _PP level generated by this charge pump circuit is supplied to the V _PP terminal of the semiconductor memory device.

According to the charge pump circuit having such a configuration, by providing the drive circuit 20, the transistor Q24 is forcibly forced by the gate pushing capacity of the capacitor C33 charged by the transistor Q27 controlled by the inverter I20A. Since it is turned on, the ON operation of the transistor Q24 can be surely performed. Therefore, the capacitor C26 can be sufficiently charged.

[0019]

According to the above-described charge pump circuit of the present invention, the first transistor for charging the charge pump capacitance in the first capacitor is forcibly turned on by the drive circuit regardless of the V _PP level. The charge pump capacitance is sufficiently charged in the first capacitor. Therefore, there is an advantage that a sufficient level of V _PP level can be generated even when the power supply voltage is low.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a charge pump circuit of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing a conventional example of a charge pump circuit.

[Explanation of symbols]

20 drive circuit 31, 32 node C26 charge pump capacitance capacitor for charging (first
Capacitor) C30 A capacitor (second capacitor) for charging the capacitance for pushing up the gate I20A Inverter Q24 Transistor (first transistor) Q27 Transistor (second transistor) Q28, Q29 Transistor forming inverter I20A

Claims (1)

[Claims] 1. A charge pump circuit for generating an internal boosting level of a semiconductor memory device, comprising: charging a first capacitor with a charge pump capacitance;
Transistor is forcibly turned on regardless of V _PP level
A second transistor that supplies a voltage to the gate of the first transistor, an inverter that connects the gate of the first transistor to the power supply, and the first transistor, A second capacitor which pushes up the gate of the transistor of the second transistor, the second capacitor being charged by the second transistor controlled by the inverter to forcefully turn on the first transistor. Charge pump circuit.