JPS6182529A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a desired boosting potential in a short time without increasing an area of a boosting capacitor by using a potential whose polarity is opposite to a power supply potential, as a reference voltage applied through a switching circuit to the other end of the boosting capacitor whose one end has been connected to a node to be boosted. CONSTITUTION:A threshold value of an MOSFET to be used is denotes as VT. First of all, a clock phi11 is set to a power supply potential VDD, MOSFETs Q15, Q14 of the first switching circuit SW1 are turned on, and a reference bias potential VBB whose polarity is opposite to VDD is applied to an input node A1 of a boosting capacitor CP. Subsequently, a clock phi12 is set to >=VDD+VT, and a node B is charged up to VDD. Next, the clock phi12 and phi11 are set to are set to VSS, and a clock phi13 is set to >=VDD+VT by holding the node B in a floating state. In this case, in the SW1, the Q15 becomes on, the Q14 becomes off and a flip-flop is inverted, the node A1 is charged up to VDD through an MOSFET-Q13 of the second switching circuit SW2, and the node B is boosted by VDD+(VDD-VBB)CP/(CL+CP).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device including a booster circuit.

[Technical background of the invention and its problems]

In a semiconductor memory device, when an E-type MOSFET is used as a data transfer gate, this MOSFET
In order to prevent a voltage drop equivalent to the threshold voltage at T and improve the transfer speed, the gate potential is boosted. A general configuration of such a booster circuit is shown in FIG. B is the node to be boosted, and CL is its load capacitance. This node B has a charging MOSFET.
ET-041 and discharge MOSFET-042 are connected. Cp is a boosting capacitor, one end of which is connected to node B, and the other end connected to power supply potential VDD via MOSFET-043 and to ground potential Vss via MOSFET-Q44. There is. This booster circuit first turns on MOSFET-Q44 to set node A to Vss, then turns on MOSFET-041 to charge node B to VDD. And M.O.
After turning off S FET T-041 and leaving Node B floating, turn off MOSFET-Q44 and turn off MOSFET-Q44.
By turning on SFET-043 and applying Voo to node A, a boosted potential higher than Voo is obtained at node 8.

This booster circuit includes a load capacitor OL, a booster capacitor Cp
When the capacitance values of node B are expressed as CL and CP, respectively, node B
The boost valve Δ■ from VDD is ΔV-(Vo o -V
s s )Cp / (Cp +OL). Therefore, when the load is large, the capacitance value of the boost capacitor Cp must be increased in order to increase the boost valve Δ■. As a result, the area of the boost capacitor increases, leading to an increase in chip cost. In addition, in order to shorten the rise time of the boost output, it is necessary to charge node A in a short time, and to do so, it is necessary to charge the charging MOSFET-
The dimension of 043 must be increased.

This also results in an increase in chip area and cost.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor integrated circuit device equipped with a booster circuit that can obtain a desired boosted potential in a short time without increasing the area of a boosting capacitor. With the goal.

[Summary of the invention]

A boosting circuit according to the present invention includes first and second switch circuits for selectively connecting the other end of a boosting capacitor, one end of which is connected to a node to be boosted, to a reference potential and a power supply potential. The present invention is characterized in that, as the reference potential applied through the first switch circuit, a potential having a polarity opposite to that of the power supply potential is used.

For example, an MO8 integrated circuit usually has a built-in substrate bias circuit to apply a substrate bias of opposite polarity to the power supply potential, so this substrate bias may be used as the reference potential.

〔Effect of the invention〕

If the booster circuit according to the present invention is used, the difference in potential applied to the input terminal of the booster capacitor becomes larger, so the area of the booster capacitor may be smaller than the conventional one in order to obtain the same level of boosted potential as the conventional one. Conversely, if the capacitor area is the same as that of the conventional one, a boosted potential higher than that of the conventional one can be obtained.

Further, a desired boosted potential can be obtained in a short time without increasing the size of the charging transistor. Therefore, by incorporating this booster circuit, it is possible to reduce the cost and improve the performance of the integrated circuit chip.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows the configuration of a booster circuit according to an embodiment in which the present invention is applied to an n-channel MO8 integrated circuit. (7) n-channel MO for charging to the node B to be boosted when the load capacitance CL is
SFET-Qlt, n-channel MOSFET for discharge
-Ql 2 is provided, and one end of the boosting capacitor Cp is connected to this node B, as in the conventional case. The other end of the boosting capacitor Cp is connected to the reference potential, in this embodiment, the substrate bias potential VBB, which is the output of the substrate bias circuit, via the first switch circuit SW2, and is connected to the substrate bias potential VBB, which is the output of the substrate bias circuit, via the first switch circuit SW2. Connected to power supply potential ■DD. The first switch circuit S W 1 is composed of a flip-flop consisting of an n-channel MOSFET-014, Qls, whose sources are commonly connected to VBB and whose gates are cross-connected, and an n-channel MOSFET-〇16 as a load. . The second switch circuit SW2 uses an n-channel MOSFET-Ql 3 as in the conventional case.

FIG. 5 shows the operation timing of this booster circuit.

To explain the operation assuming that the threshold value of the MOSFET used is VT, first, the clock ΦL! is VDD, and the first
MOSFET-Gh a , Q of the switch circuit SWt of
Turn on t4 and apply Vaa to the input node A1 of the boosting capacitor Cp. In this state, the output voltage 12 is made higher than Voo+VT, and the node B is charged to VDD.

Next, during operation, 12 and Ql1 are set to Vss, node B is kept in the 70-ting state, and clock Φ13 is set to Vss.
o+Vt or higher. At this time, the first switch circuit SW
At L, MOSFET-Qss is turned on, Ql4 is turned off and the flip-flop is inverted, and node A1 is the second switch circuit SW2, MOSFET-Qss.
Charged to vDD via Ql 3. This results in
Node B is boosted by Voo + (Voo-VaB)Cp/(CL+Cp).

As described above, according to this embodiment, the boost capacitor C
The substrate bias potential VBB is used as the reference potential given to the input terminal of p, and normally Vaa
= about -3V, so if the boosting capacitor Cp has the same capacitance value as the conventional one, a higher boosted potential than the conventional one can be obtained.

Furthermore, since the potential difference applied to the input terminal of the boosting capacitor Cp is large, the rise time of the boosted potential is short even if the charging MOSFET-Q13 is not made large. Furthermore, in order to obtain the same boosted potential as in the conventional case, the area of the boost capacitor Cp can be made smaller than in the conventional case.

Furthermore, in this embodiment, although VaB is used as the reference potential, the MO
As SFET, the threshold value is different from other parts of MOSFE.
There is no need to use one higher than T. That is, the first switch circuit SW1 constitutes 9 flip-flops, and when MOSFET-Ql4 is turned off, MOSFET-Qls is turned on and 7MOSFEs are turned on.
T-Qt 41) This is because Vaa is given to the gate. Therefore, no special ion implantation or the like is required to increase the threshold value, which is advantageous in terms of manufacturing process.

FIG. 2 shows another embodiment of a booster circuit similarly applied to an n-channel MOS integrated circuit. January MOS charged to Node B
FET-02t and discharge MOSFET-022 are connected, and Vaa and Voo are selectively applied to the input terminal of the boost capacitor Cp via the first switch circuit SW1 and the second switch circuit SW2. This is the same as in the previous embodiment. The difference from the previous embodiment is the first
One p-channel MOSF is used as the switch circuit SW1 of
The reason is that ET-024 is used.

FIG. 6 shows the operation timing of this booster circuit.

The basic boost operation is the same as the previous embodiment, but in this embodiment, the clock Φ21 is set to Vss and the 7MOSFE
Turn on T-Q24 and turn on T/- door A1. :Give Van, set 21 during drive to VDD + VT or higher, and set MOSFE
Turn off T-024.

This embodiment also provides the same effects as the previous embodiment. Further, in the case of this embodiment, the first switch circuit SW
Although the manufacturing process is more complicated than that of the embodiment shown in FIG. 1 because a p-channel MOSFET is used in the construction, it is advantageous in terms of the number of constituent elements.

FIG. 3 shows a booster circuit according to yet another embodiment. This embodiment is also a case of an n-channel MO5FET integrated circuit, and its basic configuration is the same as the previous two embodiments. That is, charge MOSFET-031 and discharge MOS are connected to boost node B.
FET-032 is provided, and the first switch circuit SW1. A second switch circuit SW2 is provided. The difference from the previous two embodiments is that one n-channel MOSFET 34 is used as the first switch circuit SW1. Since Vaa is used as the reference potential here, MOSFET-034'c of the first switch circuit SW1 (D gate is turned off at Vs s (7)R, so this MOSFET
It is necessary to use a T-034 with a higher threshold than other MOS FETs.

FIG. 7 shows the operation timing of the booster circuit of this embodiment. Its basic operation is the same as the previous embodiment. That is, after charging the node B with ■DD with the clock Φ31 set to ■DD and the MOS FET-Q34 of the first switch circuit SWs turned on, the clock Φ31 is set to Vss, and the clock Φ33 is set to Vo o +VT. In the above manner, DD is applied to node A, and a boosted potential is obtained at node B.

This embodiment also provides the same effects as the previous two embodiments. One MOSFE as the first switch circuit SW1
Although T is used, it is necessary to make the threshold value different from the others, so the manufacturing process is slightly more efficient than the embodiment shown in FIG. 1, just like the embodiment shown in FIG.

Note that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the spirit thereof.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a booster circuit of one embodiment of the present invention, Section 2 is a diagram showing a booster circuit of another embodiment, FIG. 3 is a diagram showing a booster circuit of still another embodiment, and Section 4 is a diagram showing a booster circuit of another embodiment. The figure shows a conventional booster circuit, Figure 5 shows the operation timing of the booster circuit in Figure 1, Figure 6 shows the operation timing of the booster circuit in Figure 2, and Figure 7 shows the operation timing of the booster circuit in Figure 2. FIG. 3 is a diagram showing the operation timing of the booster circuit shown in the figure. B...Node to be boosted, CL...Load capacity, Cp
...boosting capacitor, SWl...first switch circuit, SW2...second switch circuit, ■BB...
Substrate bias potential (reference potential), Vo o...power supply potential. Applicant's agent Patent attorney Takehiko Suzue Figure 1 To. 1llll BB Fig. 4 vSS Fig. 5 Fig. 6 Fig. 7

Claims (5)

[Claims] (1) A capacitor having one end connected to a node to be boosted on a semiconductor substrate, a first switch circuit for connecting the other end of this capacitor to a reference potential, and a second switch circuit for connecting to a power supply potential. 1. A semiconductor integrated circuit device comprising a step-up circuit integrated therein, characterized in that a potential having a polarity opposite to the power supply potential is used as the reference potential. (2) The semiconductor integrated circuit device according to claim 1, wherein the potential having a polarity opposite to the power supply potential is an output potential of a substrate bias generation circuit integrated on the same semiconductor substrate. (3) The integrated circuit is constituted by a first conductive channel MOSFET, and the first switch circuit is constituted by a flip-flop in which the gates of two MOSFETs of the first conductive channel are cross-connected and the sources are connected to a reference potential. A semiconductor integrated circuit device according to claim 1. (4) The semiconductor integrated circuit device according to claim 1, wherein the integrated circuit is constituted by a first conductive channel MOSFET, and a second conductive channel MOSFET is used as the first switch circuit. (5) The semiconductor integrated circuit device according to claim 1, wherein the integrated circuit is constituted by a first conductive channel MOSFET, and the first conductive channel MOSFET with a high threshold is used as the first switch circuit. .