JP2792018B2 - Level booster circuit for differential amplifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a level booster circuit, and more particularly to a level booster circuit for a differential amplifier circuit used in a semiconductor memory. (Prior Art) Among conventional semiconductor memories, Ito et al. Particularly describe a sense amplifier circuit with a level booster circuit for amplifying a small signal read from a memory cell to a bit line to a ground level or a supply voltage level. Electronic Materials, November 1984, p. 43, and Fujishima et al., Transactions of the Institute of Electronics, Information and Communication Engineers, March 1982.
Some are shown on page 159. The former is to supply the precharge level of the bit line when the chip is not selected. Supply voltage (VC)
Level (hereinafter simply referred to as VC precharge method), and the latter method is to set the bit line precharge level to about half of the supply voltage (VC / 2) when the chip is not selected (hereinafter simply referred to as VC precharge method). VC / 2 precharge system) and a level booster circuit. FIG. 7 shows a circuit diagram of a conventional semiconductor memory of this type, and FIG. 8 shows an operation waveform diagram thereof. However, the conventional example shown here is a case where a simple level booster circuit having the circuit configuration shown by Ito et al. Is used for the VC / 2 precharge system. In the following description, it is assumed that an N-channel MOSFET is used as the MISFET, and the threshold voltage is set unless otherwise specified.
Performed as VT (> 0). First, when the chip is not selected, the bit lines B0 and B1 and the sense signal line SE0 are connected to the level VB of about half of the power supply voltage VC.
And keeps the clock signal line P1 at high level (VP11> VB + VT), and the node in the level booster AP
1 and 2 also precharge to the same level VB as the bit lines B0 and B1.
However, the precharge circuit for the bit lines B0 and B1 and the sense signal line SE0 is omitted here. When the chip is selected, the level of the clock signal line P1 is changed.
Reduce MOSFET from VP11 to VP10 (VB + VT>VP10> VT)
After T3 and T4 are turned off and the electrical connection between the bit lines B0 and B1 and the nodes 1 and 2 is cut off, the memory cells MC0 and M0 are placed on the bit lines B0 and B1.
Binary information is read from one of C1. FIG. 8 shows an operation waveform when "1" information is read from the memory cell MC0 onto the bit line B0. Thereafter, the sense signal line SE0 is lowered to the ground level to activate the flip-flop circuit FF, and amplify the minute difference signal read on the bit lines B0 and B1. That is, of the bit lines B0 and B1, the lower bit line B1
Level to ground level. At this time, since the level of the clock signal line P1 is VP10 (a level lower than VB + VT and higher than VT), the MOSFET T3 remains non-conductive, but the MOSFET T4 is conductive and the level of the node 2 is set to the bit line B1. It becomes the same potential (ground level). Here, the clock signal line P0 is set to a high level, and the level of the node 1 is boosted to V1. This boost level V1 is determined by setting the size of the boost capacitors C1 and C2 to C
0, the size of the parasitic capacitances C10 and C20 at nodes 1 and 2 is C00, MOSFET
Assuming that the gate capacitances of T1 and T2 are CG and the level change amount of the clock signal line P0 is VP0, Becomes At this time, the level VBH of the bit line B0 becomes V1−VT. To raise the level VBH to the power supply voltage VC, if VP0 = VC, VB = VC / 2, then V1−VT> VC Further, assuming that VC / VT = 7, Becomes That is, the boost capacitors C1 and C2 need to be at least 1.8 times as large as the total capacitance of the nodes 1 and 2. This capacity increase increases as VC / VT decreases and the initial level VB of the nodes 1 and 2 decreases. After the above operation, when the chip is deselected, the clock signal line P0 is set to low level and the clock signal line P1 is set to high level (VP11) to deactivate the level booster AP. Further, the sense signal line SE0 and the bit lines B0 and B1 are set to the initial level VB.
(VC / 2) and keep that state. At this time, since the clock signal line P1 is at a high level, the MOSFET T
3, T4 becomes conductive and nodes 1 and 2 are at the same level (VB) as bit lines B0 and B1. (Problems to be Solved by the Invention) Increasing the capacity of semiconductor memories has been achieved by miniaturization of devices. Accordingly, in order to ensure long-term reliability of device characteristics, it is necessary to lower the supply power supply voltage VC at the same time. When a conventional level booster circuit for a differential amplifier circuit as described above is used for such a semiconductor memory, the booster capacitors C1 and C2 must be rapidly increased with a decrease in the power supply voltage VC. The size of the booster circuit AP increases,
There is a significant disadvantage that results in an increase in chip area. SUMMARY OF THE INVENTION An object of the present invention is to provide a level booster circuit for a differential amplifier circuit, which can have a higher performance and a smaller size than conventional ones. (Means for Solving the Problems) In order to solve the above problems and achieve the above object, the present invention provides first and second MISFETs, and first and second MISFETs. Third and fourth MISFETs each having a drain connected to the gate of the first MISFET; first and second boosting capacitors each having one electrode connected to the gates of the first and the second MISFETs; Fifth and sixth MISFETs, which are continuously connected to drains or sources of the first and second MISFETs and have respective gates connected to the other electrodes of the first and second boosting capacitors,
And a means for charging the gate of the second MISFET to a constant voltage.
The voltage of the charge supply line for supplying charges through the first, second, fifth, and sixth MISFETs is a power supply voltage used during operation.
VC or a first level close to VC, the first level when not operating
And a second level intermediate the ground voltage and the ground voltage. (Operation) As described in the preceding section, the level booster circuit for a differential amplifier circuit of the present invention raises the voltage of the charge supply line for supplying charges through the first and second MISFETs during the operation of the level booster circuit. By changing the level from a high level to a high level, the gate capacitances of the first and second MISFETs can be used as auxiliary boosting capacitances for boosting the gate voltages of the MISFETs. Performance is improved. Further, since the original boosting capacity can be reduced, the chip area can be made smaller than that of the conventional chip. (Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram for explaining the principle of the present invention, and FIG.
The figure is an operation waveform diagram of the level booster circuit for the differential amplifier circuit shown in FIG. The difference between the level boosting circuit shown in FIG. 1 and the conventional level boosting circuit AP shown in FIG. 7 is that the charge supply line SE1 for applying a clock signal including an offset is replaced by a power supply line VC. This is the point connected to the drains of the MOSFETs T1 and T2. The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. The operation is the same as before until the chip is selected and the clock signal line P0 goes high. However, the level of the charge supply line SE1 is maintained at the intermediate level (VS0). Accordingly, the potential of the node 1 is boosted to V1 by the clock signal line P0,
In order for the MOSFET T1 to be sufficiently conductive, the level of the bit line B0 at this time is VS0. The boost level V1 at the node 1 is expressed by the equation (1) as in the conventional case. Thereafter, the level of the charge supply line SE1 is changed to the high level VS1
To At this time, since the MOSFET T1 is conducting,
The level of the node 1 is further boosted through the gate capacitance CG. Assuming that this level is V11, V11 = V1 + ΔV1 And if the condition of V11> VS1 + VT is satisfied, the bit line
The level of B0 is raised to VS1. Here, VS0 = VC / 2, VS1 = VC, and From the equations (1) and (3), V1 = 7/6 · VC, ΔV1
= VC / 9, and the level of the node 1 is about 10% higher than that of the conventional level boosting circuit. After the above operation, when the chip becomes non-selected, the clock signal line P0 is set to the low level and the clock signal line
P1 goes high and bit lines B0, B1 and nodes
With the balance between 1 and 2, the sense signal line SE0 is precharged to the initial level VB. Further, the charge supply line SE1 is set to the intermediate level VS0, and thereafter, this state is maintained. As described above, in the present embodiment, the level booster AP
Is changed from the intermediate level VS0 to the high level VS1 during the operation of this circuit, so that the level of the node 1 can be boosted higher than the conventional one. For this reason, the level boosting circuit of this embodiment can operate at a higher speed than the conventional one. If the level of the node 1 should be the same level as the conventional one, the boosting capacitors C1 and C2 can be reduced, and the chip area can be reduced. FIG. 3 is a circuit diagram of one embodiment of the present invention, and FIG. 4 is an operation waveform diagram of the level booster circuit shown in FIG. The structural difference between the embodiment shown in FIG. 3 and the example shown in FIG. 1 is that a precharge circuit of nodes 1 and 2 is provided,
MOSFETs T5 and T6 have been inserted between T1 and T2 and bit lines B0 and B1. This precharge circuit consists of two MOSFs
ET and clock signal line P2. The level boosting circuit of the present embodiment firstly uses a clock signal line.
Keep P2 high and precharge nodes 1 and 2 to level V10. At this time, the clock signal lines P0 and P3 are kept at a low level, and the MOSFETs T3, T4, T5 and T6 are turned off. The bit lines B0 and B1 precharge to the level VB, and the charge supply line SE1 precharges to the level VS0. Here, since the MOSFETs T5 and T6 are turned off, the MOSFETs T1 and T2 are turned on even if the precharge level of the nodes 1 and 2 is increased, but the bit lines B0 and B1 and the charge supply The lines SE1 are electrically separated and can each independently determine their precharge level. However, these precharge circuits are omitted here. When the chip is selected, the clock signal line P2 is set to the low level, and the clock signal line P3 is set to the intermediate level VP3.
However, since VT <VP3 <VB + VT, the MOSFETs T3 and T4 remain non-conductive. Next, when the memory cell is selected and the binary information is read out on the bit lines B0 and B1, the flip-flop circuit FF is activated, and the lower level bit line (here, B1) is pulled down to the low level. At this time, the MOSFET T4 becomes conductive and the level of the node 2 becomes low. Here, after the clock signal line P0 is set to the high level (VP0) to boost the level of the node 1 to V1 ', the charge supply line SE is supplied as in the example of FIG.
The level of node 1 is increased from VS0 to VS1, the level of node 1 is further boosted to V11 ', and bit line B0 is raised to level VS1. These levels V1 'and V11' can be calculated by replacing VB with V10 in the equations (1) and (3). Compared to the example of FIG. 1, the difference of the precharge level of the node 1 (V10-VB> 0) )
It becomes high by the amount of. Therefore, higher performance or smaller size can be achieved. When the chip is deselected, the clock signal lines P0 and P3 are set to low level to turn off the MOSFETs T3, T4, T5 and T6,
Nodes 1 and 2 and bit lines B0 and B1 are set as initial precharge levels. FIG. 5 is a modification of the principle diagram shown in FIG. 1, and FIG. 6 is a circuit diagram of another embodiment of the present invention. The difference between the embodiment shown in FIG. 1 and the embodiment shown in FIG.
And P3. This makes it possible to simplify the circuit wiring without performance degradation. The basic operation is the same as that of the example shown in FIG. 1 and the embodiment shown in FIG. 3, so that the description is omitted here. Furthermore, in the embodiment of FIGS. 3 and 6, the MOSFET
It is also possible to reverse the arrangement of T1, T2 and the MOSFETs T5, T6. That is, the sources of the MOSFETs T5 and T6 are connected to the charge supply line SE1.
And the drains of the MOSFETs T1 and T2 are connected to the bit lines B0 and B1, respectively. In addition, in the example shown in FIG. 1 and the embodiment shown in FIG. 3, the level of the clock signal lines P1 and P3 can be set to a constant voltage of VT to VB + VT to simplify the drive signal. Also, in the embodiment shown in FIGS.
T3 and T4 are not limited to enhancement type,
It is also possible to use a depletion type MOSFET. Although the above description has been made by using an N-channel MOSFET for convenience, the present invention relates to a P-channel MOSFET.
However, essentially any other insulated gate transistor is equally applicable. (Effects of the Invention) As described above in detail, the level booster circuit for a differential amplifier circuit of the present invention can achieve high speed and high performance, and can secure the same speed and performance as the conventional one. If so, the boosting capacity may be small, and there is an effect that the size can be reduced accordingly.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram for explaining the principle of the present invention, FIG. 2 is an operation waveform diagram of the level booster circuit for a differential amplifier circuit shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing an embodiment of the invention, FIG. 4 is an operation waveform diagram of the level booster circuit for the differential amplifier circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing a modification of the principle diagram shown in FIG. FIG. 6 is a circuit diagram showing another embodiment of the present invention, FIG. 7 is a circuit diagram of a conventional semiconductor memory including a level booster circuit for a differential amplifier circuit, and FIG. 8 is a semiconductor memory shown in FIG. 3 is an operation waveform diagram of FIG. In the figure, AP is a level booster circuit, FF is a flip-flop circuit, MC0 and MC1 are memory cells, B0 and B1 are bit lines, SE0.
Is a sense signal line, SE1 is a charge supply line, P0, P1, P2, and P3 are clock signal lines, VC is a power supply line, C1 and C2 are boost capacitors, C10 and C20 are parasitic capacitors at nodes, T1, T2, T3, and T4, T5, T6 indicate the MOSFET, and VB indicates the precharge level of the bit line.

Claims (1)

(57) [Claims] First and second MISFETs and the first and second MIFETs;
Third and fourth MISFETs each having a drain and source connected to the gate and source of the SFET, and first and second MISFETs each having one electrode connected to the gates of the first and second MISFETs, respectively. Boosting capacity, the first and second
The fifth and the fifth MISFETs each having a source connected to the drain, a drain connected to the charge supply line, and a gate connected to the other electrode of the first and second boost capacitors. A sixth MISFET and the first MISFET;
And a means for charging the gate of the second MISFET to a constant voltage, wherein the voltage of the charge supply line is set to a used power supply voltage or a first level close to the used power supply voltage during operation. A level boosting circuit for a differential amplifier circuit, wherein the second level is intermediate between the first level and the ground voltage during operation. 2. First drains each connected to a charge supply line
And second MISFETs, and third and fourth MISFETs having respective drains connected to the gates of the first and second MISFETs.
MISFET, first and second boost capacitors each having one electrode connected to the gates of the first and second MISFETs, and respective drains connected to the sources of the first and second MISFETs And the third and fourth MISFs
Each source is connected to the source of the ET and the first
A seventh and an eighth MISFET having respective gates connected to the other electrodes of the first and second boosting capacitors, and means for charging the gates of the first and second MISFETs to a constant voltage. In the dynamic booster circuit level booster circuit, the voltage of the charge supply line is set to a used power supply voltage or a first level close to the power supply voltage during operation, and to a second level intermediate between the first level and the ground voltage during non-operation. A level booster circuit for a differential amplifier circuit. 3. 3. The differential amplifier circuit according to claim 1, wherein gates of the third and fourth MISFETs are connected to sources of the fourth and third MISFETs, respectively. Level booster circuit. 4. 3. The level boosting circuit for a differential amplifier circuit according to claim 1, wherein a constant reference voltage is applied to gates of said third and fourth MISFETs. 5. 3. The level boosting circuit for a differential amplifier circuit according to claim 1, wherein a clock signal is applied to gates of said third and fourth MISFETs.