JP2569464B2 - Dynamic memory cell - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly, to a dynamic memory cell having a function of amplifying a storage signal.

(Prior Art and its Problems) As a conventional dynamic memory cell having a function of amplifying information stored therein, that is, a voltage, for example, there is a one-transistor type memory cell as shown in FIG. (Japanese Patent Application No. 54-116479). In FIG. 2, B is a bit line, W is a word line, Z is a storage word line, TG is a selection gate, CS is a cell capacitance, CB is a parasitic capacitance on a bit line, C00 and C01 are parasitic capacitances on a node S. Of these, components distributed in the vicinity of the selection gate TG and the cell capacitance CS are shown as lumped constants, respectively. However, the capacitance value of the cell capacitance CS changes depending on the voltage between the electrodes. For example, the gate electrode of an enhancement type MOS FET is connected to one electrode,
A capacitor having a structure in which a source electrode and a drain electrode are the other electrodes is used. In a capacitor having this structure, when a voltage higher than the threshold voltage of this MOS FET is applied between both electrodes, a channel layer is formed on the substrate opposite to the gate electrode between the source electrode and the drain electrode, and this channel layer is formed. And the source electrode and the drain electrode form one electrode, the capacitance value is large. When a voltage lower than the threshold voltage is applied, the channel layer is not formed and the capacitance value is reduced by the amount of the channel layer.

FIG. 3 is an operation waveform diagram at each location of the memory cell shown in FIG.

Next, the operation of the memory cell shown in FIG. 2 will be described using operation waveforms shown in FIG.

First, the storage word line Z is charged from the low level to the high level VZ at a time t1 before the word line W is set to the high level and the cell information is read onto the bit line B. At this time, the potential VSO of the node S changes due to the coupling via the cell capacitance CS, and the change amount ΔV is Is represented by At this time, the potential VS1 of the node S can be written as VS1 = VS0 + ΔV.

Here, when the threshold voltage is VT as the cell capacitance CS and the voltage applied between the electrodes is VC, the capacitance value between the electrodes is CS = CSL when VC <VT and CS = CSH when VC ≧ VT, Further, assuming that a MOS capacitor satisfying CSL <CSH is used, the potential change amount ΔVH of the node S when the cell information is at a high level (hereinafter referred to as “H”) is given by VS0 = VH0 (> VT). = VH0> VT Becomes When the cell information is at a low level (hereinafter referred to as “L”), the potential change amount ΔVL of the node S is VS0 = VL0 (<V
T), VC = VL0 <VT Becomes Accordingly, comparing the potential change amounts ΔVH, ΔVL at the node S when the cell information is “H”, “L”, CSH> CSL, and thus ΔVH> ΔVL. That is, the level difference (VH-VL) of the "H" and "L" information of the node S is amplified by (.DELTA.VH-.DELTA.VL) by the coupling via the cell capacitance CS. At this time, the potentials VH1 and VL1 of the cell information “H” and “L” stored at the node S
VH1 = VH0 + ΔVH VL1 = VL0 + ΔVL Thereafter, at time t2, the word line W is set to the high level to read the cell information onto the bit line B, and the minute signal is amplified using a sense amplifier (not shown). When the precharge potential of the bit line B is VB, the magnitude ΔVB of this minute signal is Becomes Here, VS1 in this equation indicates the potential VH1 or VL1 of the node S when "H" or "L" information is stored.

Next, at time t3, the storage word line Z is set to low level. At this time, the storage word line Z via the cell capacitance CS
, The potential of the node S tends to decrease due to the coupling from the bit line B because the word line W is at a high level and the selection gate TG is conducting. Therefore, the potential of the node S hardly changes.

The above is the information reading operation of the conventional one-transistor memory cell having the cell information amplifying function. As described above, by using a cell having a voltage dependency on the cell capacity constituting the memory cell, for example, using a capacitor of an enhancement type MOS FET, and changing the potential of one electrode of the capacitor, the cell information “H” is obtained. The effect of increasing the potential difference between "and" L "was obtained.

The amplification characteristics of the memory cell having such a configuration are as shown in FIG. That is, the potential increase ΔV of the node S due to the coupling of the storage word line Z is:
When the initial potential VS0 there is lower than a certain value VSL, it becomes almost 0, and when it is higher than a certain value VSM, it becomes a constant value ΔVS. Then, between them, the voltage increases almost in proportion to the initial potential VS0. Where VSLVT VSMVZ + VT-ΔVS ΔVS at this time corresponds to ΔVH described above. Therefore, to obtain such a ΔVH, VH0> VSM
The initial potential VH0 at the time of "H" information that satisfies the following condition is required. The potential in the cell is reduced due to leakage or the like, and when VH0 <VSM, the amplification efficiency is degraded. Even if such a decrease in the cell potential VH0 occurs, the VSM must be lowered in order to maximize the effect of amplification, and for that purpose ΔV
It is important to set S, that is, CSH / (C00 + C01) to be large.

However, in recent memory cells aiming for ultra-high integration, in order to reduce the cell size, the cell capacity CS
(= CSH) tends to be as small as possible. Therefore, CSH /
(C00 + C01) had a serious disadvantage that it became smaller and the VSM became higher. Further, the same problem occurs when the parasitic capacitances C00 and C01 are large even when the cell capacitance CS is constant.

(Object of the Invention) The object of the present invention is to provide a ratio C of cell capacitance CS and parasitic capacitance C00, C01.
Even if S / (C00 + C01) becomes small, VSM can be set to a low value. Therefore, even if the potential in the cell of "H" information becomes low, an amplification type dynamic memory cell with a large amplification effect is provided. is there.

(Structure of the Invention) In the dynamic memory cell of the present invention, one terminal is connected to a word line and a storage word line arranged in pairs in a row direction, a bit line arranged in a column direction, and the storage word line. A cell capacitance whose capacitance value changes by a voltage applied between the electrodes, a first input / output terminal connected to the other terminal of the cell capacitance, a second input / output terminal connected to the bit line, and the word line connected to the bit line. A select gate to which a control terminal is connected to a line, charging the storage word line paired with the word line before the word line is selected (charged);
In a dynamic memory cell of a system in which the storage word line is discharged during a time when the word line is selectively driven, these terminals are connected between the other terminal of the cell capacitance and a first input / output terminal of the selection gate. By connecting a cell resistor for separating a parasitic capacitance to the cell.

Example Next, an example of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of one embodiment of the present invention.

In this embodiment, one terminal is connected to the word line W and the storage word line Z arranged in pairs in the row direction, the bit line B arranged in the column direction, and the storage word line Z, and the voltage is applied between the electrodes. A cell capacitance CS whose capacitance value changes according to the applied voltage, a first input / output terminal connected to the other terminal of the cell capacitance CS, a second input / output terminal connected to the bit line B, and control over the word line W A selection gate TG to which a terminal is connected, and charges a storage word line Z that is paired with the word line W before the word line W is selected (charged). In the dynamic memory cell of the type in which the storage word line Z is discharged, a cell resistor RS for separating the capacitance parasitic on these terminals is connected between the other terminal of the cell capacitance CS and the first input / output terminal of the selection gate TG. By doing Constructed.

The driving method of this embodiment is exactly the same as that of the conventional example shown in FIG. However, since the cell resistance RS is inserted between the nodes S0 and S1, the parasitic capacitance C0 attached to those nodes is
0 and C01 appear to be transiently separated from each other, and the potential rise ΔV1 generated at the node S1 due to the coupling from the storage word line Z at time t1 is instantaneously And the effect does not appear at the node S0. However, thereafter, charge transfer occurs through the cell resistance RS, and the nodes S0 and S1
Is the final potential rise ΔV0 of ΔV0 (C00 + C01 + CS) = ΔV1 (C01 + CS) = CS × VZ And the same as the above-described conventional value ΔV, but the ΔV and ΔV0 do not consider the value of the cell capacitance CS determined from the relationship between the potential of the node S and the threshold voltage VT of the cell capacitance CS.
At this time, it is clear that ΔV1 is larger than ΔVS described above, and thus VSM is correspondingly lower. This enhances the signal amplification effect of the memory cell when VH0 is low. further,
The parasitic capacitance C00 has a selection gate G from the node S0 to the word line W.
This includes the gate-drain (or source) overlap capacitance of T and the junction capacitance to the substrate, etc.
Includes only the stray capacitance from the node S1 to each wiring section via a thick insulating film, and therefore C00 >> C01. Therefore,
When the memory cell of the present invention is used, the VSM becomes extremely lower than before.

Considering these points, a relatively large value of parasitic capacitance
In the state including C00 (conventional example), ΔVS is small, so that the voltage between the electrodes of the cell capacitance CS does not reach the threshold voltage VT, the value of the cell capacitance CS becomes CSL, and in the present invention, ΔV1 is large. Is higher than the threshold voltage VT, and the value of the cell capacitance CS is CSH. Therefore, the read voltage can be increased from the above expression of ΔV0.

However, the size of the cell resistance RS, when charging of the storage word line (rise) time and t _r, A value that satisfies the degree is appropriate. If the value is larger than this, the amplification efficiency of the signal increases, but the access time (reading and writing of information) to the memory cell becomes longer, which is not practical. On the other hand, if it is smaller than this, the effect of amplifying a signal due to the insertion of the cell resistor RS will not increase.

As described above, in this embodiment, the cell resistance RS is set to the selection gate GT.
By inserting between the cell capacitance CS and the parasitic capacitance attached to the cell capacitance CS so as to be apparently small, the effect of amplifying the information in the cell using the storage word line Z can be enhanced.

In this embodiment, nothing is said about the configuration and structure of the cell resistor RS, but this can be made using polysilicon, depletion and enhancement transistors, etc., and further in the direction perpendicular to the substrate. Placing a cell resistance can also be performed using a conventionally known method.

The present invention is particularly effective for a one-transistor type dynamic memory cell having a signal amplifying function. On the basis of a similar principle, the present invention dynamically amplifies the potential of a node storing "H" information. Obviously, it can be applied to any kind of circuit.

Further, the present invention relates to the N-channel MOSF used in the description herein.
It is not limited to ET, but is applicable to P-channel MOSFETs and any other FETs.

(Effects of the Invention) As described above, according to the present invention, the effect of increasing the potential difference between the cell information “H” and “L” can be obtained. Further, even if the potential of the cell information "H" is greatly reduced by the leak current as compared with the conventional case, the effect of sufficiently amplifying the potential is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a conventional dynamic memory, and FIG. 3 is an operation waveform of each portion during operation of the dynamic memory cell shown in FIG. FIG. 4 is an amplification characteristic diagram of the dynamic memory cell shown in FIG. B: bit line, CB: parasitic capacitance of bit line, C00, C01
... parasitic capacitance distributed in the memory cell, CS ... cell capacitance, RS ... cell resistance, TG ... select gate, W ... word line, Z ... storage word line.

Claims (1)

(57) [Claims] 1. A word line and a storage word line arranged in a row direction, a bit line arranged in a column direction, and one terminal connected to the storage word line and a voltage applied between electrodes. A cell capacitance whose capacitance value changes, and a selection in which a first input / output terminal is connected to the other terminal of the cell capacitance, a second input / output terminal is connected to the bit line, and a control terminal is connected to the word line. A gate for charging the storage word line paired with the word line before the word line is selected (charged), and discharging the storage word line within a time when the word line is selectively driven. In the dynamic memory cell, a cell resistor for separating capacitance parasitic to these terminals is connected between the other terminal of the cell capacitance and the first input / output terminal of the select gate. Dynamic memory cell that.