JPS5813519Y2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a read-only memory (ROM) having memory cells made of MOS transistors.

In a conventional ROM, bit lines B are provided in the X direction as shown in FIG.

, B1...Bm and word lines Wo, W provided in the Y direction
A memory cell MC is arranged at the intersection with l...Wm, a predetermined word line is set to an e-level, and one predetermined row selection transistor T is opened to write data into the selected memory cell. The sense amplifier SA reads and outputs the information.

Normal ROM uses memory cells as N-channel MOS
), and if the transistor is turned on when the gate is set to a no-y level, it is considered to be "information present", and an impurity that gives the same conductivity type as the semiconductor substrate is added near the surface of the semiconductor substrate under the gate insulating film. For example, if the gate does not turn on even at low level or high level due to introducing a gate insulating film or forming a thick gate insulating film, it is regarded as "no information", and such a state of the memory cell MC is defined as sense a/b SA. The information written in the memory cell is read by simply amplifying the information received by the inverter in the memory cell.
Based on the non-uniformity of the characteristics of the MOS transistors that make up the cell, there is a drawback that the voltage level when there is information read out to the bit line or the voltage when there is no information is non-uniform. .

The present invention is a new invention that improves the above-mentioned drawbacks of the conventional technology.The purpose of this invention is to solve the problem that in a ROM using a MOS transistor as a memory cell, the read signal read out to the bit line is somewhat non-uniform. Another object of the present invention is to provide a semiconductor memory device that can accurately read out information that has been written in a memory cell.

In order to achieve this purpose, the semiconductor memory device according to the present invention has an MO at each intersection of a plurality of bit lines and word lines.
S) A semiconductor memory device in which a memory cell consisting of a transistor is arranged, which includes a transistor constituting the memory cell and a dummy cell consisting of a transistor having a dimension smaller than that of the transistor,
It is characterized in that the terminal voltages of the memory cell and the dummy cell are compared at the time of reading, and the information written in the memory cell is read out.The embodiment will be explained in detail below. 1 is a circuit diagram showing an example of a read-only memory; FIG.

In FIG. 2, MC is a memory cell consisting of an N-channel MOS transistor, and m cells are arranged in a matrix in the X direction and n cells in the Y direction.

The MOS transistors that make up these memory cells are MOS transistors that are turned on when the gate is set to a high level, and impurities are introduced near the surface of the semiconductor substrate under the gate insulating film to give it the same conductivity type as the semiconductor substrate. The MOS transistors are constructed such that they do not turn on even when the gate is at a high level by applying a strong force or by forming a thick gate insulating film, and these MOS transistors are arranged according to a predetermined pattern during manufacture.

Note that in FIG. 2, a MOS transistor whose gate is not connected is a MOS transistor that does not turn on even if the gate becomes high level.

Xo -xm-1 is a word line, yo "" my n -
1 is a bit line selection line, 'r.

-Tn-1 is a switching transistor for bit line selection, SA is a sense amplifier, and DC is a dummy cell consisting of a MOS transistor.

The dimension (particularly the channel width) of the MOS transistor constituting the dummy cell DC is about a fraction of that of the MOS transistor constituting the memory cell.

■v0 is an inverter, switching transistor To
-Tn-□ and one input terminal a of sense amplifier 7''SA.

(2) v2 is an inverter connected between the dummy cell DC and the other input terminal of the sense amplifier SA.

Next, the operation of the above embodiment will be explained.

Hood line X.

-Xm-1 and bit line selection line Y. .about.Ym-□ to select a specific memory cell MC, and at the same time, the gate line φ of the dummy cell DC.

MOS that configures dummy cell DC with /% level
) Turn on the transistor.

When the dummy cell DC is turned on, current flows to the dummy cell DC through the load transistor of the inverter V2, so the input terminal of the sense amplifier SA, which has now settled at vthD, the threshold voltage of the driver transistor of the inverter V2. The voltage across the dummy cell DC drops to the voltage VDC across the dummy cell DC.

On the other hand, if the MOS transistor of the selected memory cell MC is on, the dimension of the MO8 transistor is much larger than that of the MOS transistor constituting the dummy cell, so the resistance between the drain and source becomes almost zero. , the current flows through the bit line selection switching transistor T selected from the load transistor of the inverter v1, passes through the MOS transistor of the memory cell, and flows to the power supply line v88.

Then, the voltage at the input terminal a of the sense amplifier SA, which until now had settled at the threshold voltage v, hD of the driver transistor of the inverter vl, drops to almost zero. By comparing the potential difference between the two, it is detected that the selected memory cell MC has information, for example, and this signal is output.

Furthermore, when the MOS transistor of the selected memory cell MC is off, no current flows through the memory cell MC, so the voltage at the input terminal a of the sense amplifier SA is the threshold voltage vthD. .

Therefore, the sense amplifier SA compares the voltage VDC across the dummy cell DC with the threshold voltage VthD, detects that the selected memory cell MC is, for example, 1 "no information", and outputs this signal. In embodiments such as, when a large number of memory cells are connected to one bit line, the bit line length becomes long,
The influence of the stray capacitance associated with the bit line and the resistance of the bit line itself increases, making it difficult to read information,
Alternatively, the read speed may become slow.

The embodiment shown in FIG. 3 is a circuit diagram showing an embodiment that improves the above-mentioned drawbacks, and the same parts as those in the previous embodiment are given the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, each bit line is divided into two, switching transistors for bit line selection are connected to the inner ends of these bit lines, and these are connected to input terminals a and b of a sense amplifier SA, respectively. Inverter IV
1 and IV2.

A dummy cell DC is connected to the outer end of each bit line.

Then, half of the memory cells are connected to the bit line on the left side of the sense amplifier SA, and the other half of the memory cells are connected to the bit line on the right side.

When a memory cell located on the left side of sense amplifier SA is selected, a dummy cell connected to the same bit line on the right side of sense amplifier SA is turned on to sense the potential difference between the left and right bit lines. The information detected by the amplifier SA and written to the selected memory cell is read out.

If a memory cell located on the right side of the sense amplifier SA is selected, the left dummy cell is turned on to read out the information written in the memory cell.

As explained in detail above, the present invention includes a sense amplifier that detects information by comparing two electric potentials, and a sense amplifier that detects information by comparing the potentials of two people. A dummy cell is provided, and during a read operation, the terminal voltages of the memory cell and the dummy cell are compared, and the sense circuit is operated based on the level difference, so that the read operation can be made faster than the conventional one.

The MOS transistors that make up the memory cells are
MOS that constitutes a dummy cell) When comparing the level difference with the transistor, it is sufficient that the level difference is clearly visible, so it is a method that reads information by amplifying the terminal voltage of the memory cell as in the past. The dimensions of the transistors (MOS) constituting the memory cells can be made smaller compared to the conventional method, and the degree of integration of the ROM can be made larger than that of the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a part of a conventional ROM, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment. In the figure, MC is a memory cell, xo"Xm-t is a word line, YO"'n-1 is a bit line selection line, 78 to 7m-1 are switching transistors for bit line selection, SA is a sense amplifier, DC is a dummy cell, ■v1 and ■v2
is an inverter, and a and b are input terminals of a sense amplifier.

Claims (1)

[Scope of utility model registration request] In a semiconductor memory device in which a memory cell consisting of a MOS transistor is arranged at each intersection of a plurality of bit lines and word lines, a dummy cell consisting of a transistor constituting the memory cell and a transistor having a dimension smaller than that of the transistor is used. What is claimed is: 1. A semiconductor memory device comprising: a memory cell and a dummy cell; terminal voltages of a memory cell and a dummy cell are compared during reading to read out information written in a memory cell;