JPS63153791A - Word line drive signal generating circuit - Google Patents
Word line drive signal generating circuitInfo
- Publication number
- JPS63153791A JPS63153791A JP61301965A JP30196586A JPS63153791A JP S63153791 A JPS63153791 A JP S63153791A JP 61301965 A JP61301965 A JP 61301965A JP 30196586 A JP30196586 A JP 30196586A JP S63153791 A JPS63153791 A JP S63153791A
- Authority
- JP
- Japan
- Prior art keywords
- word line
- potential
- line drive
- drive signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 5
- 238000012423 maintenance Methods 0.000 claims description 11
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 9
- 230000004913 activation Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ダイナミックＲＡＭのワード線駆動信号発
生回路に関し、特にワード線駆動信号の電位を電源電圧
以上に昇圧し維持するための回路を備えたものに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a word line drive signal generation circuit for a dynamic RAM, and particularly to a word line drive signal generation circuit that includes a circuit for boosting and maintaining the potential of a word line drive signal above a power supply voltage. It's about things.
ＭＯＳ ＤＲＡＭにおいて、アクセストランジスタの
しきい値電圧Ｖいによる読み出し電圧及び書き込み電圧
の損失を解消するために、ワード線の電位を電源電圧ｖ
ｃｅ以上に昇圧する場合がある。In MOS DRAM, in order to eliminate the loss of read voltage and write voltage due to the threshold voltage V of the access transistor, the potential of the word line is set to the power supply voltage V.
There are cases where the pressure is increased to more than ce.
この場合、ワード線は電気的にフローティングの状態と
なっているため、ＶＣＣ以上の電位で長時間放置してお
くと、自然のリークで電位が下がってい（、これを防ぐ
ために、ワード線を高電位に維持するための回路を備え
たものがある。このような回路を備えた従来のワード線
駆動信号発生回路の一例を第２図に示す。図において、
１はワード線駆動信号昇圧回路、２は高電位維持回路、
ＷＤはワード線駆動信号である。In this case, the word line is in an electrically floating state, so if it is left at a potential higher than VCC for a long time, the potential will drop due to natural leakage. Some devices are equipped with a circuit for maintaining the potential. An example of a conventional word line drive signal generation circuit equipped with such a circuit is shown in FIG. 2. In the figure,
1 is a word line drive signal booster circuit, 2 is a high potential maintenance circuit,
WD is a word line drive signal.
次に動作について説明する。Next, the operation will be explained.
ワード線トリガ信号φ、を受けて、ワード線駆動信号昇
圧回路１が作動し、ワード線駆動信号ＷＤがＶＣＣ＋Δ
Ｖまで昇圧される。このとき、上記φ１信号によって高
電位維持回路２も活性化され、上記ＷＤ倍信号ＶＣＣ＋
Δ■に維持される。φ２は連続パルス信号であり、実際
に上記ＷＤ倍信号電荷を供給する。In response to the word line trigger signal φ, the word line drive signal booster circuit 1 is activated, and the word line drive signal WD increases to VCC+Δ.
The voltage is boosted to V. At this time, the high potential maintaining circuit 2 is also activated by the φ1 signal, and the WD double signal VCC+
Maintained at Δ■. φ2 is a continuous pulse signal, which actually supplies the above-mentioned WD times the signal charge.
従来のワード線駆動信号発生回路は以上のように構成さ
れているので、ワード線駆動信号ＷＤが電源電圧ｖｃｃ
より充分高電位であるにもかかわらず、ワード線がアク
ティブな期間中、常に高電位維持回路が作動しており、
無駄な電力を消費するという問題点があった。Since the conventional word line drive signal generation circuit is configured as described above, the word line drive signal WD is set to the power supply voltage vcc.
Even though the potential is much higher, the high potential maintenance circuit is always active while the word line is active.
There was a problem that power was wasted.
この発明は上記のような問題点を解消するためになされ
たもので、無駄な電力を消費することなく、効率よ（ワ
ード線駆動信号を電源電圧以上に維持することができる
ワード線駆動信号発生回路を得ることを目的とする。This invention was made in order to solve the above-mentioned problems. The purpose is to obtain a circuit.
この発明に係るワード線駆動信号発生回路は、ワード線
駆動信号の電位を検知し、該検知電位が電源電圧以上の
基準電位以上の場合には上記ワード線駆動信号の電位を
電源電圧以上に維持するための高電位維持回路の作動を
停止させ、上記検知電位が上記基準電位以下の場合には
上記高電位維持回路を作動させるようにしたものである
。The word line drive signal generation circuit according to the present invention detects the potential of the word line drive signal, and maintains the potential of the word line drive signal at a level higher than the power supply voltage when the detected potential is equal to or higher than a reference potential higher than the power supply voltage. The high potential sustaining circuit is configured to stop operating, and when the detected potential is below the reference potential, the high potential maintaining circuit is activated.
この発明においては、ワード線駆動信号が基準電位以上
の場合には高電位維持回路の作動を停止させるので、電
力を無駄に消費することなくワード線駆動信号を電源電
圧以上に維持することができる。In this invention, when the word line drive signal is higher than the reference potential, the operation of the high potential maintenance circuit is stopped, so the word line drive signal can be maintained at higher than the power supply voltage without wasting power. .
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例によるワード線駆動信号発
生回路を示し、図において、１はワード線駆動信号昇圧
回路、２ａ＋〜２ａ７は複数個設けられた高電位維持回
路であり、該回路２ａ＋はワード線トリガ信号φｌによ
り活性化されるが、該回路２ａｚ〜２ａａは後述する活
性化信号φ３がなければ活性化されないものである。３
はワード線駆動信号ＷＤの電位を検知して電源電圧以上
の基準電位Ｖ□と比較し、該ＷＤ倍信号該Ｖ□電位以下
の場合に高電位維持回路２ａｔ〜２ａ７に活性化信号φ
３を出力する電位検出回路である。FIG. 1 shows a word line drive signal generation circuit according to an embodiment of the present invention. In the figure, 1 is a word line drive signal booster circuit, 2a+ to 2a7 are a plurality of high potential maintaining circuits, and 2a+ is activated by the word line trigger signal φl, but the circuits 2az to 2aa are not activated unless there is an activation signal φ3, which will be described later. 3
detects the potential of the word line drive signal WD and compares it with a reference potential V□ which is higher than the power supply voltage, and when the WD multiplied signal is lower than the potential V□, an activation signal φ is sent to the high potential maintaining circuits 2at to 2a7.
This is a potential detection circuit that outputs 3.
次に動作について説明する。Next, the operation will be explained.
ワード線トリガ信号φ１を受けて、ワード線駆動信号昇
圧回路１が作動し、ワード線駆動信号ＷＤが電源電圧■
。０以上に昇圧される。この時、上記φ１信号は高電位
維持回路２ａ＋〜２ａ７、及び電位検出回路３にも伝え
られる。電位検出回路３は、上記φ、倍信号受けて活性
化され、上記ＷＤ倍信号電位と電源電位ＶＣｅ以上の基
準電位Ｖ□とを比較し、該ＷＤ倍信号電位が該Ｖ□電位
より低くなった時に高電位維持回路２ａｇ〜２ａｎに活
性化信号φ３を出力する。そして、高電位維持回路２ａ
＋は上記φ１信号がアクティブな期間中、常に作動して
いるが、高電位維持回路２ａｚ〜２ａ７は上記φ、倍信
号上記φ、倍信号共に受けた時に初めて作動し、上記Ｗ
Ｄ倍信号、電位を電源電圧ＶＣＣ以上に維持する。ここ
で、φ２は連続パルス信号であり、実際に高電位維持回
路２ａｌ〜２ａ、内部で電荷を供給する役目を持つ。Upon receiving the word line trigger signal φ1, the word line drive signal booster circuit 1 is activated, and the word line drive signal WD is raised to the power supply voltage ■
. The voltage is increased to 0 or more. At this time, the φ1 signal is also transmitted to the high potential maintaining circuits 2a+ to 2a7 and the potential detecting circuit 3. The potential detection circuit 3 is activated upon receiving the φ double signal, compares the WD double signal potential with a reference potential V□ which is higher than the power supply potential VCe, and detects that the WD double signal potential is lower than the V□ potential. At this time, the activation signal φ3 is output to the high potential maintaining circuits 2ag to 2an. And high potential maintenance circuit 2a
+ is always active during the period when the φ1 signal is active, but the high potential sustaining circuits 2az to 2a7 are activated for the first time when they receive both the φ, double signal, and the double signal.
The potential of the D-fold signal is maintained above the power supply voltage VCC. Here, φ2 is a continuous pulse signal, which actually has the role of supplying charges inside the high potential maintaining circuits 2al to 2a.
このように本実施例では、ワード線駆動信号ＷＤの電位
が基準電位Ｖｓｔ以上ある場合には高電位維持回路２ａ
ｚ〜２ａａの作動を停止させ、上記ＷＤ倍信号電位が上
記Ｖ□電位以下の場合には全ての高電位維持回路２ａＩ
〜２ａ９を作動させるようにしたので、電力を無駄に消
費することなくワード線駆動信号ＷＤを電源電圧以上に
維持することができる。As described above, in this embodiment, when the potential of the word line drive signal WD is equal to or higher than the reference potential Vst, the high potential maintenance circuit 2a
The operation of z~2aa is stopped, and when the WD double signal potential is below the V□ potential, all high potential maintaining circuits 2aI
2a9 is activated, the word line drive signal WD can be maintained at a voltage higher than the power supply voltage without wasting power.
なお、上記実施例では、高電位維持回路を複数個設けた
ものについて述べたが、該回路は１個であってもよく、
該回路の活性化の切換えを上記実施例と同様に活性化信
号φ、によって行なうことにより、上記実施例と同様の
効果を奏する。In the above embodiment, a plurality of high potential sustaining circuits are provided, but the number of the circuits may be one.
By switching the activation of the circuit using the activation signal φ as in the above embodiment, the same effects as in the above embodiment can be obtained.
以上のように、この発明によれば、ワード線駆動信号の
電位を検知し、該検知電位が基準電位以上の場合には、
高電位維持回路の作動を停止させ、上記検知電位が上記
基準電位以下の場合には上記高電位維持回路を作動させ
るようにしたので、低消費電力でワード線駆動信号を電
源電圧以上に維持することができるワード線駆動信号発
生回路を得ることができる。As described above, according to the present invention, the potential of the word line drive signal is detected, and when the detected potential is equal to or higher than the reference potential,
Since the operation of the high potential maintenance circuit is stopped and the high potential maintenance circuit is activated when the detected potential is below the reference potential, the word line drive signal can be maintained above the power supply voltage with low power consumption. Accordingly, a word line drive signal generation circuit that can generate a word line drive signal can be obtained.
第１図はこの発明の一実施例によるワード線駆動信号発
生回路を示す構成図、第２図は従来のワード線駆動信号
発生回路を示す構成図である。
図において、１はワード線駆動信号昇圧回路、２．２ａ
、〜２ａｍは高電位維持回路、３は電位検知回路、ＷＤ
はワード線駆動信号、φ、はワード線トリガ信号、φ２
は連続パルス信号、φ、は活性化信号である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a block diagram showing a word line drive signal generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional word line drive signal generation circuit. In the figure, 1 is a word line drive signal booster circuit, 2.2a
, ~2am is a high potential maintenance circuit, 3 is a potential detection circuit, WD
is the word line drive signal, φ is the word line trigger signal, φ2
is a continuous pulse signal, and φ is an activation signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ためのワード線駆動信号昇圧回路と、上記ワード線駆動
信号の電位を電源電圧以上に維持するための高電位維持
回路と、 上記ワード線駆動信号の電位を検知し、該検知電位が電
源電圧以上の基準電位以上の場合には上記高電位維持回
路の作動を停止させ、上記検知電位が上記基準電位以下
の場合には上記高電位維持回路を作動させる電位検知作
動手段とを備えたことを特徴とするワード線駆動信号発
生回路。 （２）上記高電位維持回路は、複数個設けられており、
少なくとも１個は常に作動するものであることを特徴と
する特許請求の範囲第１項記載のワード線駆動信号発生
回路。[Scope of Claims] 1) A word line drive signal booster circuit for boosting the potential of the word line drive signal above the power supply voltage, and a high potential maintenance circuit for maintaining the potential of the word line drive signal above the power supply voltage. A circuit that detects the potential of the word line drive signal, stops the operation of the high potential maintenance circuit when the detected potential is equal to or higher than a reference potential that is equal to or higher than the power supply voltage, and when the detected potential is equal to or lower than the reference potential. A word line drive signal generating circuit comprising: potential detection operating means for operating the high potential maintenance circuit. (2) A plurality of the above-mentioned high potential sustaining circuits are provided,
2. The word line drive signal generating circuit according to claim 1, wherein at least one of the word line drive signal generating circuits is always activated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61301965A JPS63153791A (en) | 1986-12-17 | 1986-12-17 | Word line drive signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61301965A JPS63153791A (en) | 1986-12-17 | 1986-12-17 | Word line drive signal generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63153791A true JPS63153791A (en) | 1988-06-27 |
Family
ID=17903257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61301965A Pending JPS63153791A (en) | 1986-12-17 | 1986-12-17 | Word line drive signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63153791A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393091A (en) * | 1989-09-06 | 1991-04-18 | Fujitsu Ltd | Semiconductor integrated circuit device and semiconductor memory device |
| JPH0554649A (en) * | 1991-08-26 | 1993-03-05 | Nec Corp | Semiconductor memory |
| JPH0581859A (en) * | 1991-09-25 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH08235859A (en) * | 1994-12-29 | 1996-09-13 | Samsung Electron Co Ltd | Step-up circuit of semiconductor memory |
| US7999439B2 (en) | 2008-04-24 | 2011-08-16 | Olympus Corporation | Linear drive ultrasonic motor |
-
1986
- 1986-12-17 JP JP61301965A patent/JPS63153791A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0393091A (en) * | 1989-09-06 | 1991-04-18 | Fujitsu Ltd | Semiconductor integrated circuit device and semiconductor memory device |
| JPH0554649A (en) * | 1991-08-26 | 1993-03-05 | Nec Corp | Semiconductor memory |
| JPH0581859A (en) * | 1991-09-25 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH08235859A (en) * | 1994-12-29 | 1996-09-13 | Samsung Electron Co Ltd | Step-up circuit of semiconductor memory |
| US7999439B2 (en) | 2008-04-24 | 2011-08-16 | Olympus Corporation | Linear drive ultrasonic motor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2697412B2 (en) | Dynamic RAM | |
| US5262998A (en) | Dynamic random access memory with operational sleep mode | |
| KR960003534B1 (en) | Step-down circuit of source voltage | |
| KR920018772A (en) | Semiconductor memory | |
| JPH0370317B2 (en) | ||
| KR970051074A (en) | Internal boost power control method for each refresh of semiconductor memory device | |
| TW374930B (en) | A RAM device having a self-refresh mode | |
| TWI239531B (en) | Ripple refresh circuit and method for sequentially refreshing a semiconductor memory system | |
| TW346629B (en) | Semiconductor memory device | |
| KR940001163A (en) | Dynamic Random Access Memory Device Suitable for Shortening the Time Required to Test Self-Refresh Functions | |
| US5208779A (en) | Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs | |
| JP3006014B2 (en) | Semiconductor memory | |
| KR930010987A (en) | Special mode control method of dynamic RAM | |
| KR950007089A (en) | Semiconductor integrated circuit device with low power consumption signal input circuit responsive to high amplitude input signals with small amplitude | |
| KR960019712A (en) | Semiconductor memory | |
| KR900002304A (en) | Semiconductor memory | |
| JPS63153791A (en) | Word line drive signal generating circuit | |
| KR860008561A (en) | Booster circuit | |
| KR900001806B1 (en) | Clock signal generator for dynamic semiconductor memroy | |
| TW286404B (en) | Semiconductor memory device for reducing operating power consumption amount | |
| KR930010999A (en) | Semiconductor memory device and its driving method | |
| KR950014256B1 (en) | Semiconductor memory device using low source voltage | |
| US6172932B1 (en) | On-chip voltage generating device for semiconductor memory with reduced stand-by current | |
| EP0276854A3 (en) | Semiconductor memory device with improved column selection scheme | |
| JPH05298884A (en) | Semiconductor memory |