KR100771810B1 - Apparatus for supplying high voltage and method for supplying high voltage using the same - Google Patents

Abstract

The present invention relates to a high voltage supply device and a high voltage supply method using the same. The bootstrap circuit and the charge pump circuit for generating a high voltage are disposed together, and the bootstrap circuit can be used to minimize the current in the self-refresh mode. In other modes, the present invention provides a high voltage supply device and a high voltage supply method using the same by minimizing a current consumed in the self refresh mode by generating a high voltage using a charge pump circuit.

Self-Refresh, Charge Pump Circuit, Bootstrap Circuit

Description

High voltage supply device and high voltage supply method using same {Apparatus for supplying high voltage and method for supplying high voltage using the same}             

1 is a block diagram showing the configuration of a high voltage supply apparatus according to an embodiment of the present invention.

FIG. 2 is a characteristic waveform diagram of the high voltage supply device shown in FIG. 1. FIG.

 <Explanation of symbols for main parts of the drawings>

10: command buffer unit 20: command decoding unit

30: self refresh flag signal generator

40: charge pump circuit portion 50: bootstrap circuit portion

60: memory cell array

The present invention relates to a high voltage supply device and a high voltage supply method using the same, and more particularly, to a high voltage supply device capable of minimizing a current consumed when entering a self refresh mode in a semiconductor device and a high voltage supply method using the same.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output devices that lose data over time. It can maintain state, but it can be divided into ROM (read only memory) products with slow input / output of data. These ROM products can be categorized into ROM, programmable ROM (PROM), erasable PROM (EPROM), and electrically EPROM (EEPROM), of which DRAM is the most representative semiconductor memory device, from low-cost personal computers to high-performance server-class workstations. It is widely used as a main memory device for obtaining proper performance at the lowest price.

DRAM is a compact and highly integrated unit consisting of one capacitor and one transistor, and has the lowest cost per bit, making it a highly competitive product. A plurality of word lines and a plurality of bit line pairs are defined. Here, the array of word lines is named Row, and the array of bit line pairs is named Column.

The memory capacity of a DRAM is determined by the product of multiple rows and multiple columns, and a special address code is required to specify each single row and each single column. The corresponding address codes are provided under the names of row addresses and column addresses. Thus, a DRAM needs half the address pins to specify its capacity.

Several command pins are required to drive the DRAM.The ras (#RAS) pin, which handles the input of the row address, performs the chip selection role, and the casing (#CAS), which manages the input of the column address and especially the data input / output. The write enable (#WE) pin, which acts as a flag to specify the pin and read / write operations, is the flagship of the DRAM command pin. However, such a DRAM has a disadvantage in that a refresh operation configuration must be provided because data stored in a cell is not periodically recharged and thus stored data is lost. Therefore, even if the DRAM chip is in the standby state without accessing it for a long time, a refresh operation must be essentially performed in any form.

As the typical refresh method of DRAM, CBR refresh method and auto refresh method are widely used. Since these refresh methods execute commands directly in the memory controller, the command buffers, which are means for receiving the corresponding commands, operate. You will be in standby. As a result, the current consumed by these buffers affects the overall power consumption of the DRAM. Therefore, in order to solve this drawback of DRAM, an operation method called self refresh has been invented and used. The self-refresh method applies a special command called self-refresh, and the DRAM chip turns off most of the buffers, which are means for receiving the command, and generates the refresh command by itself. This self-refresh method is an essential element for low-power DRAM products, and during the self-refresh period, it is basic to design all unnecessary components of DRAM internally to be turned off.

In addition, the DRAM uses a high voltage in an operation method for reading and writing the cell and the data stored in the cell. In other words, a DRAM cell is composed of one NMOS transistor and one capacitor, and the voltage drop caused by driving the NMOS transistor is an obstacle in reading / writing cell data. In other words, since the word line driven by the power supply voltage Vcc is approached at the level of 'Vcc-Vt', the cell data is not read as a complete value. Therefore, DRAM generates and uses a high voltage (Vpp) that activates a word line.

The high voltage Vpp may be generated by using a charge pump circuit, or by using a bootstrap circuit. The method of creating a high voltage (Vpp) by using the charge pump circuit has a disadvantage of consuming a lot of current about 30 to 40% efficiency based on an external power source, by using a bootstrap circuit to make a high voltage (Vpp) The dispensing method consumes a very small amount of current but has a disadvantage in that it is difficult to guarantee a long tRAS (RAS pulse width). In particular, in the case of DRAM, since the portion where the high voltage (Vpp) is used is mostly a low pass, most of the current is consumed in the self refresh mode.

Accordingly, the present invention has been made to solve the above problem, and has an object of minimizing the current consumed when entering the self refresh mode by minimizing the high voltage (Vpp) current used in the semiconductor memory device.

The present invention provides a command buffer unit for receiving a command signal from the outside; A command decoding unit for generating an active command signal and an auto refresh command signal according to the signal output from the command buffer; A charge pump circuit unit configured to supply a first high voltage to a memory cell array when the active signal is activated; A self refresh flag signal generator for outputting a self refresh flag signal according to a clock enable signal when the auto refresh command signal is activated; And a bootstrap circuit unit for supplying a second high voltage to the memory cell array according to the self refresh flag signal.

The method may further include: supplying a first high voltage to the memory cell array from the charge pump circuit unit when an active command signal is generated according to a command signal input from the outside; And supplying a second high voltage to the memory cell array from a bootstrap circuit unit when a self refresh flag signal is generated according to the command signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.                     

1 is a block diagram schematically showing the configuration of a high voltage supply device according to an embodiment of the present invention.

Referring to FIG. 1, the present invention provides a command buffer unit 10 for receiving and buffering a plurality of command signals input from an external device, and an output signal of the command buffer unit 10. The command decoding unit 20 for receiving and decoding the data and the first high voltage Vpp1 are driven in response to an active command signal ACOM output from the command decoding unit 20. The self-refresh flag by receiving the charge pump circuit 40 for outputting the signal, the auto refresh command signal AREF and the external clock enable signal CKE output from the command decoding unit 20. A second high voltage is received by receiving the self refresh flag signal generator 30 for outputting the signal SRF and the self refresh flag signal AREF output from the self refresh flag signal generator 30. And a bootstrap circuit unit 50 for outputting Vpp2 to the memory cell array 60.

The command buffer unit 10 manages input of a plurality of command signals applied from the outside, for example, a clock signal CLK for synchronizing, a chip selector signal #CS for selecting a chip, and a row address. Write enable the chip to act as a raster signal (#RAS) that plays the role of chip selection, a cas signal (#CAS) that manages the input and output of column addresses, and a read / write operation. The signal #WE is received and buffered and output to the command decoding unit 20.

The command decoding unit 20 is a command signal input from the command buffer unit 10, that is, a chip selector signal #CS, a ras signal #RAS, a cas signal #CAS, and a write enable signal ( The #WE) is combined to output the active command signal ACOM and the auto refresh command signal AREF. The active command signal ACOM is a signal for performing a read / write operation of a general memory cell, and the command signal input from the outside enables the active mode and the column line to enable the row line. Enabled when driven in read / write mode. The auto refresh command signal AREF is a signal for performing a self-refresh operation. The ras signal #RAS and the cas signal #CAS are logic low, and the write enable signal #WE is logic. Enabled in the self refresh mode which is HIGH.

The self refresh flag signal generation unit 30 receives the auto refresh command signal AREF and the external input clock enable signal CKE generated from the command decoding unit 20 to recognize the self refresh command, and recognizes the self refresh flag. Output the signal SRF.

The charge pump circuit 40 is driven by the active command signal ACOM output from the command decoding unit 20 to output the first high voltage Vpp1 to the memory cell array 60.

The bootstrap circuit unit 50 is driven by the self refresh flag signal SRF input from the self refresh flag signal generator 30 to output a second high voltage Vpp2 to the memory cell array 60. .

The high voltage supply method using the high voltage supply device of the present invention described above will be described with reference to the characteristic waveform diagram of the high voltage supply device shown in FIG. 2.

Referring to FIG. 2, the chip selector signal #CS is low, the ras signal #RAS is low, the cas signal #CAS is high, and the write enable signal #WE is applied from the outside during the period T1 to T2. Is input to the command decoding unit 20 through the command buffer unit 10 in the high state, the command decoding unit 20 is the active command signal (ACOM) and the auto state of the low state (that is, not enabled) The refresh command signal AREF is output.

Subsequently, while the chip selector signal #CS and the ras signal #RAS remain low and the write enable signal #WE remains high in the T2 period, the cas signal #CAS is high. When the transition is made low, the command decoding unit 20 outputs an active command signal ACOM in a low state, and outputs an auto refresh command signal AREF in a high state (ie, an enabled state).

On the other hand, when the auto refresh command signal AREF of the high state is output from the command decoding unit 20 and input to the self refresh flag signal generator 30, the self refresh flag signal generator 30 is clock enabled. When the signal CKE is input in the low state, the high self-refresh flag signal SRF is output to the bootstrap circuit unit 50 to drive the bootstrap circuit unit 50. Accordingly, the bootstrap circuit unit 50 generates the second high voltage Vpp2 and supplies it to the memory cell array 60.

Thereafter, in the T3 period, if the write enable signal #WE transitions from high to low while the chip selector signal #CS, the ras signal #RAS, and the cas signal #CAS are held low, The command decoding unit 20 outputs an active command signal ACOM in a high state and an auto refresh command signal AREF in a low state.

Meanwhile, the active command signal ACOM of the high state output from the command decoding unit 20 is input to the charge pump circuit unit 40 to drive the charge pump circuit unit 40. Therefore, the charge pump circuit 40 generates a first high voltage Vpp1 and supplies it to the memory cell array 60. .

That is, in the present invention, any one of the charge pump circuit portion and the bootstrap circuit portion is selected to generate a high voltage according to an external command signal. In the self-refresh mode, the bootstrap circuit portion is driven to output a second high voltage Vpp2. In other modes, the charge pump circuit unit is driven to output the first high voltage Vpp1.

In detail, the present invention selects and uses a bootstrap circuit using capacitance instead of the charge pump circuit in order to minimize the current consumed in the self-refresh mode, which consumes more current in the bootstrap circuit than in the charge pump circuit. This is because it is consumed small.

When the charge pump circuit is closely related to the efficiency, and when the external power source is 3.3V, when the internal power source generates 5V, the efficiency is about 30 to 40%, so as to generate high voltage (Vpp). Current consumed from an external power source is increased by about 2.5 to 3 times higher than the input high voltage (IVpp). On the contrary, in the bootstrap circuit, when the capacitor capacity is constant according to a formula of 'Q = CV' (where Q is capacitance, C is charge, and V is an external power source), a certain amount of charge is given. In order to maintain the voltage change of one node of the capacitor is represented by the change amount of the other node, the current consumption can be minimized.

As described above, the present invention minimizes the high voltage (Vpp) current used in the semiconductor memory device, thereby minimizing the current consumed when entering the self-response mode.

Furthermore, reducing the self-refresh current can provide a competitive advantage for low power DRAMs.

Claims (3)

A command buffer unit for receiving a command signal from the outside; A command decoding unit for generating an active command signal and an auto refresh command signal according to the signal output from the command buffer; A charge pump circuit unit configured to supply a first high voltage to a memory cell array when the active signal is activated; A self refresh flag signal generator for outputting a self refresh flag signal according to a clock enable signal when the auto refresh command signal is activated; And And a bootstrap circuit unit configured to supply a second high voltage to the memory cell array in response to the self refresh flag signal. A method of supplying a high voltage to a memory device comprising a high voltage supply device including a charge pump circuit portion generating a first high voltage and a bootstrap circuit portion generating a second high voltage according to a control signal, When the active command signal is generated according to a command signal input from an external source, supplying a first high voltage to the memory cell array of the memory device from the charge pump circuit unit; And And when a self refresh flag signal is generated according to the command signal, supplying a second high voltage to the memory cell array from the bootstrap circuit unit. The method of claim 2, The self refresh flag signal is generated according to an auto refresh command signal and a clock enable signal generated according to the command signal.

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