KR0172404B1 - Refresh boosting source control method of semiconductor memory device - Google Patents
Refresh boosting source control method of semiconductor memory device Download PDFInfo
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- KR0172404B1 KR0172404B1 KR1019950053533A KR19950053533A KR0172404B1 KR 0172404 B1 KR0172404 B1 KR 0172404B1 KR 1019950053533 A KR1019950053533 A KR 1019950053533A KR 19950053533 A KR19950053533 A KR 19950053533A KR 0172404 B1 KR0172404 B1 KR 0172404B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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Abstract
1. 청구범위에 기재된 발명이 속하는 기술 분야 :1. The technical field to which the invention described in the claims belongs:
본 발명은 반도체 메모리 장치의 내부승압전원 제어방법에 관한 것이다.The present invention relates to a method of controlling an internal boost power supply of a semiconductor memory device.
2. 발명이 해결하려고 하는 기술적 과제 :2. The technical problem to be solved by the invention:
본 발명은 리프레쉬 싸이클에 대해 승압전압 액티브 킥커의 동작 개수를 가변시켜 불필요한 전원공급을 줄여 이에 따른 칩의 오동작 또는 과다한 공급 전하 소모를 제거할 수 있는 리프레쉬 싸이클시 내부전원전압의 제어방법을 제공한다.The present invention provides a control method of the internal power supply voltage during a refresh cycle that can reduce the unnecessary power supply by changing the number of operation of the boost voltage active kicker with respect to the refresh cycle, thereby eliminating chip malfunction or excessive supply charge consumption.
3. 발명의 해결방법의 요지 :3. Summary of the solution of the invention:
본 발명은 시스템으로부터의 로우어드레스스트로우브 신호 및 승압전압 제어신호에 응답하여 승압전압 발생기에서 승압한 전압을 내부 파워 라인에 공급하며 동시에 리프레쉬 동작을 포함하는 반도체 메모리 장치의 내부승압전원 제어방법에 있어서, 상기 로우어드레스스트로우브 신호가 인에이블된 상태에서 승압전압 액티브 킥커 제어신호와 리프레쉬 싸이클 제어신호로서 제어하여 복수개의 승압전압 액티브 킥커가 동작하는 제1과정과, 상기 로우어드레스스트로우브 신호가 인에이블된 상태에서 상기 승압 전압 액티브 킥커 제어신호와 리프레쉬 싸이클 제어신호를 논리조합하여 상기 복수개의 승압전압 액티브 킥커중 소정 개수의 상기 승압전압 액티브 킥커는 동작되지 않게 제어하는 제2과정을 포함한다.The present invention provides a method for controlling an internal boost power supply of a semiconductor memory device including a refresh operation by supplying a voltage boosted by a boost voltage generator to an internal power line in response to a low address strobe signal and a boost voltage control signal from a system. And controlling the boost voltage active kicker control signal and the refresh cycle control signal while the low address strobe signal is enabled to operate a plurality of boost voltage active kickers, and the low address strobe signal is enabled. And a second process of logically combining the boosted voltage active kicker control signal and the refresh cycle control signal to control a predetermined number of the boosted voltage active kickers out of the plurality of boosted voltage active kickers.
4. 발명의 중요한 용도 :4. Important uses of the invention:
반도체 메모리 장치에 적합하게 사용된다.It is suitably used for semiconductor memory devices.
Description
제1도는 종래 기술에 따른 내부승압전압 제어방법을 나타낸 블럭도.1 is a block diagram showing an internal boost voltage control method according to the prior art.
제2도는 제1도의 동작 타이밍도.2 is an operation timing diagram of FIG.
제3도는 본 발명에 따른 내부승압전원 제어방법을 나타내는 개략도.3 is a schematic diagram showing a method for controlling an internal booster power supply according to the present invention.
제4도는 일반적인 스탠바이 승압전압 발생기의 구성블럭도.4 is a block diagram of a typical standby boost voltage generator.
제5도는 본 발명에 따른 내부승압전원 제어방법을 나타내는 구성블럭도.5 is a block diagram showing an internal boost power control method according to the present invention.
제6도는 제5도의 동작 타이밍도.6 is an operation timing diagram of FIG.
본 발명은 반도체 메모리 장치에 관한 것으로, 특히 리프레쉬 싸이클 각각에 따라 적절한 전하를 공급하여 과다한 전하 소모 및 칩의 오동작을 방지하는 내부 승압전원 제어방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method of controlling an internal boosted power supply that prevents excessive charge consumption and chip malfunction by supplying an appropriate charge according to each refresh cycle.
반도체 메모리 장치 내에서 승압전압 발생기의 사용목적은 칩 사이즈(Chip Size)를 줄이기 위해 피형 센스앰프(P-Type Sense Amplifier; 이하 PSA라 칭함)와 엔형 센스앰프(N-Type Sense Amplifier; 이하 NSA라 칭함)를 분리게이트 사이에 배치하는 센스앰프 공유방식을 채용함으로 인하여 활성화 리스토아(Active Restore)시 데이타 1의 손실(엔모오스 분리게이트의 문턱전압 강하)을 막기 위한 승압전원이 필요하게 되었고, 칩이 고집적화되면서 한 싸이클(Cycle)에 구동하여야 하는 워드라인(Word Line)의 로딩(Loading)도 커지게 되어 워드라인 인에이블(Enable)에 시간이 걸리므로 속도 저하가 우려되어, 칩 내에 승압전압 Vpp 발생기는 스탠바이(Stand-by)때 동작하는 메인펌프(Main pump)와 액티브(Active)시 동작하는 액티브 킥커(Active Kicker)로 나뉜다. 통상 다이나믹 램(Dynamic Random Access Memory)에서는 하나의 칩(Chip)내에서 리프레쉬 싸이클(Refresh Cycle)을 옵션(Option)화하여 사용하고 있는데, 이때 한 싸이클에서 동작하는 쎌(Cell)의 개수 차이에 의해 소모되는 전하량이 차이를 보이게 된다. 공급되는 전하량과 소모되는 전하량에 있어서 소모되는 전하량이 공급되는 전하량보다 많을 경우 칩의 오동작을 유발하고, 공급되는 전하량이 소모되는 전하량보다 많을 경우 칩내의 불필요한 전하량을 공급하여 칩의 신뢰성을 떨어뜨리게 된다. 제1도는 종래 기술에 따른 내부승압전원 제어방법을 나타낸 블럭도이다. 제1도를 참조하면, 구성은 승압전압 파워 라인 13과, 상기 승압전압 파워 라인 13에 접속되어 칩의 스탠바이시 승압전압 Vpp을 공급하기 위한 스탠바이 승압전압 발생기 23과, 상기 승압전압 파워 라인 13에 접속되며 칩의 활성화시 소정의 제어신호 PR에 의해 제어되어 승압전압 Vpp를 공급하는 제1,제2,제3, 제N 승압전압 액티브 킥커 15,17,19,21로 구성된다. 따라서, 예를들어 리프레쉬 싸이클 4K는 1K에 비해서 쎌의 개수가 한번에 ¼ 밖에 동작하지 않으므로 그에 다른 소모 전하량도 그만큼 적게 나타난다. 이와같은 경우에 1K에 비해서 4K는 승압전압 Vpp 액티브 킥커의 동작 개수를 작게 하여도 칩은 동작한다. 또한 리프레쉬 싸이클에 관계없이 승압전압 액티브 킥커를 가장 싸이클링(Cycling)이 많이 소모하는 경우에 대해서 배치하여 동작시켜 리프레쉬 싸이클이 큰 경우, 필요이상의 전하량을 공급해 칩 상에서 승압전압 파워 라인(Power Line)에 필요이상의 전압 상승이 발생하여 산화항복(Oxide Breakdown), 접합 항복(Junction Breakdown) 또는 트랜지스터의 특성을 저하시키는 문제를 발생시킨다.The purpose of the boost voltage generator in a semiconductor memory device is to use a P-Type Sense Amplifier (hereinafter referred to as PSA) and an N-Type Sense Amplifier (hereinafter referred to as NSA) in order to reduce the chip size. By adopting a sense amplifier sharing method in which the separation gates are disposed between the separation gates, a boost power supply is required to prevent the loss of data 1 (the threshold voltage drop of the enmo separation gate) during active restore. Due to the high integration, the loading of word lines that must be driven in one cycle also becomes large, and it takes time for word lines to be enabled. The generator is divided into a main pump that operates in stand-by and an active kicker that operates in active mode. In general, the Dynamic Random Access Memory uses a refresh cycle as an option in one chip, and at this time, the difference in the number of cells operating in one cycle is used. The amount of charge consumed is different. If the amount of charge consumed in the amount of charge supplied and the amount of charge consumed is greater than the amount of charge supplied, the chip malfunctions. If the amount of charge supplied is more than the amount of charge consumed, it reduces the reliability of the chip by supplying unnecessary charge in the chip. . 1 is a block diagram showing a method for controlling an internal booster power according to the prior art. Referring to FIG. 1, the configuration includes a boosted voltage power line 13, a standby boosted voltage generator 23 connected to the boosted voltage power line 13 to supply a boosted voltage Vpp at the standby of a chip, and a boosted voltage power line 13. And a first, second, third, and Nth boost voltage active kickers 15, 17, 19, and 21 which are connected and controlled by a predetermined control signal PR to supply a boost voltage Vpp upon activation of the chip. Thus, for example, since the refresh cycle 4K operates only ¼ at a time as compared to 1K, the amount of other consumed charges is also reduced. In this case, the chip operates even if the number of operation of the boost voltage Vpp active kicker is smaller than that of 1K. In addition, regardless of the refresh cycle, the boost voltage active kicker is placed and operated for the most cycle-intensive case, and when the refresh cycle is large, it is necessary to supply more charge than necessary to the boost voltage power line on the chip. The above voltage rise may cause problems such as oxide breakdown, junction breakdown, or deterioration of transistor characteristics.
제2도는 제1도의 동작 타이밍도이다. 제2도를 참조하면, 로우어드레스스트로우브 신호 RASB가 논리로우(Low)로 인에이블되면 제어신호 PR이 논리하이(High)로 되어 동작 싸이클이 시작된다.2 is an operation timing diagram of FIG. Referring to FIG. 2, when the low address strobe signal RASB is enabled at a logic low, the control signal PR is at a logic high to start an operation cycle.
따라서, 본 발명의 목적은 리프레쉬 싸이클에 대해 승압전압 액티브 킥커의 동작 개수를 가변시켜 불필요한 전원공급을 줄여 이에 따른 칩의 오동작 또는 과다한 공급 전하 소모를 제거할 수 있는 리프레쉬 싸이클시 내부전원전압의 제어방법을 제공함에 있다.Accordingly, an object of the present invention is to control the internal power supply voltage during a refresh cycle that can reduce the unnecessary power supply by eliminating the unnecessary power supply by varying the number of operation of the boost voltage active kicker for the refresh cycle, thereby eliminating chip malfunction or excessive supply charge consumption. In providing.
상기한 목적들을 달성하기 위한 본 발명의 기술적 사상에 따르면, 시스템으로부터의 로우어드레스스트로우브 신호 및 승압전압 제어신호에 응답하여 승압전압 발생기에서 승압한 전압을 내부 파워 라인에 공급하며 동시에 리프레쉬 동작을 포함하는 반도체 메모리 장치의 내부승압전원 제어방법에 있어서, 상기 로우어드레스스트로우브 신호가 인에이블된 상태에서 승압전압 액티브 킥커 제어신호와 리프레쉬 싸이클 제어신호로서 제어하여 복수개의 승압전압 액티브 킥커가 동작하는 제1과정과, 상기 로우어드레스스트로우브 신호가 인에이블된 상태에서 상기 승압전압 액티브 킥커 제어신호와 리프레쉬 싸이클 제어신호를 논리조합하여 상기 복수개의 승압전압 액티브 킥커중 소정 개수의 상기 승압전압 액티브 킥커는 동작되지 않게 제어하는 제2과정을 특징으로 한다.According to the technical idea of the present invention for achieving the above object, in response to the low address strobe signal and the boost voltage control signal from the system to supply the voltage boosted by the boost voltage generator to the internal power line and at the same time includes a refresh operation A method of controlling an internal boost power supply of a semiconductor memory device, the method comprising: controlling a boost voltage active kicker control signal and a refresh cycle control signal while the low address strobe signal is enabled to operate a plurality of boost voltage active kickers; And a predetermined number of the boosted voltage active kickers among the plurality of boosted voltage active kickers by performing a logical combination of the boosted voltage active kicker control signal and the refresh cycle control signal while the low address strobe signal is enabled. Control It is characterized by two processes.
이하 본 발명의 바람직한 실시예들의 상세한 설명이 첨부된 도면들을 참조하여 설명된다.DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.
도면들중 동일한 구성요소 및 부분들은 가능한한 어느곳에서든지 동일한 부호들을 나타내고 있음을 유의하여야 한다.It should be noted that like elements and parts in the figures represent the same numerals wherever possible.
제3도는 본 발명에 따른 내부승압전원 제어방법을 나타내는 개략도이다. 제3도를 참조하면, 상기 제1도의 제어방법과 다른 점은 리프레쉬 싸이클시 승압전압 액티브 킥커 제어신호 PAK 및 리프레쉬 싸이클 제어신호 Ref로 승압전압 액티브 킥커가 제어된다는 것이다.3 is a schematic diagram showing a method for controlling an internal booster power supply according to the present invention. Referring to FIG. 3, the difference from the control method of FIG. 1 is that the boost voltage active kicker is controlled by the boost voltage active kicker control signal PAK and the refresh cycle control signal Ref during the refresh cycle.
제4도는 일반적인 스탠바이 승압전압 발생기의 구성블럭도이다. 제4도를 참조하면, 발진신호를 발생하기 위한 발진회로 100과, 상기 발진회로 100에 접속되어 상기 발진신호에 응답하여 펌핑(Pumping)하여 승압전압 Vpp를 출력하기 위한 메인펌프(Main Pump) 200과, 상기 메인펌프 200에 접속되어 승압전압의 레벨을 검출하기 위한 승압전압 감지기 300으로 구성되어 승압전압 Vpp를 발생시키게 된다.4 is a block diagram of a typical standby boost voltage generator. Referring to FIG. 4, an oscillation circuit 100 for generating an oscillation signal and a main pump 200 connected to the oscillation circuit 100 and pumped in response to the oscillation signal to output a boosted voltage Vpp. And a boosted voltage detector 300 connected to the main pump 200 to detect the level of the boosted voltage to generate the boosted voltage Vpp.
제5도는 본 발명에 따른 내부승압전원 제어방법을 나타내는 구성블럭도이다. 제5도를 참조하면, 종래의 제어신호 PR과 제1,제2,제3,제4 승압전압 액티브 킥커 15,17,19,21를 제어하는 승압전압 액티브 킥커 제어신호 PAK 및 리프레쉬 싸이클 제어신호 Ref로서 인버터(Inverter) 31,33 및 낸드게이트(NAND Gate) 35,37 각각을 통하여 동작 싸이클을 제어하는 구성을 가진다. 한편, 통상 칩상에는 승압전압 액티브 킥커 다수개를 배치하여 내부승압전원을 공급하는데 만약, 승압전압 액티브 킥커 4개를 배치하여 1K 리프레쉬인 경우에 그에 상응하는 동작에 따른 전하량을 공급한다고 하면, 4K 리프레쉬일 경우에는 그 만큼 동작하는 회로가 줄어들게 되어 동작에 필요한 전하량은 줄어들게 된다. 따라서 4K 리프레쉬일때는 승압전압 액티브 킥커를 모두 동작시킬 필요가 없고 단지 4K 리프레쉬시 소모되는 전하량만 공급하면 된다. 그러므로, 본 발명은 승압전압 액티브 킥커의 개수를 줄여 과다 공급 전하량을 방지하는 효과를 가지게 된다.5 is a block diagram showing an internal booster power control method according to the present invention. Referring to FIG. 5, the conventional control signal PR and the boosted voltage active kicker control signal PAK and the refresh cycle control signal for controlling the first, second, third, and fourth boosted voltage active kickers 15, 17, 19, and 21 are shown. As a Ref, an operation cycle is controlled through inverters 31, 33 and NAND gates 35, 37, respectively. On the other hand, on the chip, a plurality of booster voltage active kickers are arranged to supply internal boost power.If 4 booster voltage active kickers are disposed and 1K refresh is used to supply the amount of charge according to the corresponding operation, 4K refresh is performed. In one case, the circuit operates as much as that, so the amount of charge required for the operation is reduced. Therefore, in 4K refresh, it is not necessary to operate all boost voltage active kickers, and only supply the amount of charge consumed in 4K refresh. Therefore, the present invention has the effect of reducing the number of boost voltage active kickers to prevent excessive supply charge.
제6도는 제5도의 동작 타이밍도이다. 제6도를 참조하면, 상기 제2도에서는 로우어드레스스트로우브 신호 RASB의 신호를 받아 PR이 인에이블되면서 액티브 킥커가 동작하는데 반하여, 승압전압 액티브 킥커 제어신호 PAK 신호와 리프레쉬 싸이클 제어신호 Ref가 반전논리곱으로 합쳐져서 논리로우가 될 경우 액티브 킥커가 동작한다. 그러므로 리프레쉬 싸이클 제어신호 Ref가 논리하이일 경우 제3,제4 승압전압 액티브 킥커로의 신호인 도면부호 C,D의 출력은 논리하이가 나오므로 상기 승압전압 액티브 킥커가 동작하지 않는다. 여기서는 1K일 경우 액티브 킥커가 4개 동작하는 것을 보여주고(리프레쉬 싸이클 제어신호 Ref가 논리로우상태), 4K일 경우 액티브 킥커가 2개 동작하는 것(리프레쉬 싸이클 제어신호 Ref가 논리하이상태)을 보여준다.6 is an operation timing diagram of FIG. Referring to FIG. 6, in FIG. 2, the active kicker operates while PR is enabled by receiving the low address strobe signal RASB, whereas the boosted voltage active kicker control signal PAK signal and the refresh cycle control signal Ref are inverted. When combined to logical low, the active kicker is activated. Therefore, when the refresh cycle control signal Ref is logic high, the output of the reference numerals C and D, which are signals to the third and fourth boost voltage active kickers, is logic high, and thus the boost voltage active kicker does not operate. In this example, 4 Kicks the active kicker (Refresh Cycle Control Signal Ref is Logic Low), and 4K Kicks the Active Kicker (Refresh Cycle Control Signal Ref is Logic High). .
상기한 바와 같이 본 발명에 따르면, 승압전압 액티브 킥커의 개수를 줄여 과다 공급 전하량을 방지하여 칩의 오동작 방지 및 신뢰성 향상의 효과가 있다.As described above, according to the present invention, the number of boost voltage active kickers is reduced to prevent excessive supply charge, thereby preventing chip malfunction and improving reliability.
상기한 본 발명은 도면을 중심으로 예를들어 한정되었지만, 그 동일한 것은 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러 가지 변화와 변형이 가능함이 본 분야의 숙련된 자에게 있어 명백할 것이다.Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.
Claims (4)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950053533A KR0172404B1 (en) | 1995-12-21 | 1995-12-21 | Refresh boosting source control method of semiconductor memory device |
| TW085114785A TW308694B (en) | 1995-12-21 | 1996-11-29 | Method for controlling the internal booster power source of a semiconductor memory device during every refresh cycle |
| US08/772,172 US5867442A (en) | 1995-12-21 | 1996-12-19 | Variable output voltage booster circuits and methods |
| JP8343113A JPH09282875A (en) | 1995-12-21 | 1996-12-24 | Control method for internal boosting power supply according to refresh of semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950053533A KR0172404B1 (en) | 1995-12-21 | 1995-12-21 | Refresh boosting source control method of semiconductor memory device |
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| Publication Number | Publication Date |
|---|---|
| KR970051074A KR970051074A (en) | 1997-07-29 |
| KR0172404B1 true KR0172404B1 (en) | 1999-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950053533A KR0172404B1 (en) | 1995-12-21 | 1995-12-21 | Refresh boosting source control method of semiconductor memory device |
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| Country | Link |
|---|---|
| US (1) | US5867442A (en) |
| JP (1) | JPH09282875A (en) |
| KR (1) | KR0172404B1 (en) |
| TW (1) | TW308694B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101492717B1 (en) * | 2012-05-21 | 2015-02-11 | 후지쯔 세미컨덕터 가부시키가이샤 | Voltage generation circuit |
| US9123402B2 (en) | 2007-09-14 | 2015-09-01 | Conversant Intellectual Property Management Inc. | Dynamic random access memory and boosted voltage producer therefor |
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| KR100242720B1 (en) * | 1996-12-30 | 2000-02-01 | 윤종용 | Column select control circuit of semiconductor device |
| TW423162B (en) | 1997-02-27 | 2001-02-21 | Toshiba Corp | Power voltage supplying circuit and semiconductor memory including the same |
| KR100378690B1 (en) | 1998-07-21 | 2003-06-12 | 주식회사 하이닉스반도체 | High power generator for semiconductor memory with reduced standby current |
| KR100439026B1 (en) * | 2001-10-23 | 2004-07-03 | 삼성전자주식회사 | High voltage generating circuit and method |
| DE102004004785A1 (en) * | 2004-01-30 | 2005-08-25 | Infineon Technologies Ag | Voltage pump arrangement for semiconductor devices |
| KR100688513B1 (en) * | 2005-01-05 | 2007-03-02 | 삼성전자주식회사 | Boosted voltage generating circuit and method in semiconductor memory device |
| JP5259505B2 (en) | 2009-06-26 | 2013-08-07 | 株式会社東芝 | Semiconductor memory device |
| US10490251B2 (en) | 2017-01-30 | 2019-11-26 | Micron Technology, Inc. | Apparatuses and methods for distributing row hammer refresh events across a memory device |
| US11017833B2 (en) | 2018-05-24 | 2021-05-25 | Micron Technology, Inc. | Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling |
| US10685696B2 (en) | 2018-10-31 | 2020-06-16 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
| WO2020117686A1 (en) | 2018-12-03 | 2020-06-11 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
| US10957377B2 (en) | 2018-12-26 | 2021-03-23 | Micron Technology, Inc. | Apparatuses and methods for distributed targeted refresh operations |
| US11615831B2 (en) | 2019-02-26 | 2023-03-28 | Micron Technology, Inc. | Apparatuses and methods for memory mat refresh sequencing |
| US11227649B2 (en) | 2019-04-04 | 2022-01-18 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of targeted refresh operations |
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| US10978132B2 (en) | 2019-06-05 | 2021-04-13 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of skipped refresh operations |
| US11302374B2 (en) | 2019-08-23 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic refresh allocation |
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| US11309010B2 (en) | 2020-08-14 | 2022-04-19 | Micron Technology, Inc. | Apparatuses, systems, and methods for memory directed access pause |
| US11380382B2 (en) | 2020-08-19 | 2022-07-05 | Micron Technology, Inc. | Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit |
| US11348631B2 (en) | 2020-08-19 | 2022-05-31 | Micron Technology, Inc. | Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed |
| US11557331B2 (en) | 2020-09-23 | 2023-01-17 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh operations |
| US11264079B1 (en) | 2020-12-18 | 2022-03-01 | Micron Technology, Inc. | Apparatuses and methods for row hammer based cache lockdown |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1258242B (en) * | 1991-11-07 | 1996-02-22 | Samsung Electronics Co Ltd | SEMICONDUCTOR MEMORY DEVICE INCLUDING SUPPLY VOLTAGE PUMPING CIRCUIT |
-
1995
- 1995-12-21 KR KR1019950053533A patent/KR0172404B1/en not_active IP Right Cessation
-
1996
- 1996-11-29 TW TW085114785A patent/TW308694B/en not_active IP Right Cessation
- 1996-12-19 US US08/772,172 patent/US5867442A/en not_active Expired - Lifetime
- 1996-12-24 JP JP8343113A patent/JPH09282875A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9123402B2 (en) | 2007-09-14 | 2015-09-01 | Conversant Intellectual Property Management Inc. | Dynamic random access memory and boosted voltage producer therefor |
| KR101492717B1 (en) * | 2012-05-21 | 2015-02-11 | 후지쯔 세미컨덕터 가부시키가이샤 | Voltage generation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US5867442A (en) | 1999-02-02 |
| KR970051074A (en) | 1997-07-29 |
| JPH09282875A (en) | 1997-10-31 |
| TW308694B (en) | 1997-06-21 |
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