KR100228524B1 - Word line driving circuit for semiconductor memory device - Google Patents

Abstract

The present invention relates to a word line driving circuit of a semiconductor memory device having a sub word line driving circuit and a main word line driving circuit for receiving an output of the sub word line driving circuit and for reducing the power consumption of the chip, A word line drive control circuit for providing the external power supply voltage in order to minimize power consumption of the first power supply line and the second power supply line by being logically combined according to an external power supply voltage applied in response to the row address signal, The power supply line is connected to the first power supply line or the second power supply line, and the external power supply voltage is input. Logically combined with the boosted power supply voltage or the external power supply voltage is applied to the SWD circuit connected to the word line of each cell array block. The boosted power supply voltage or the external power supply voltage to drive the storage capacitor of the word line, And a main word line driving circuit for outputting a full data line.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a word line driving circuit for a semiconductor memory device,

The present invention relates to a word line driver circuit of a semiconductor memory device, and more particularly to a word line driver circuit of a semiconductor memory device having a sub word line driver circuit and a main word line driver circuit, .

Efforts to store more information on a small area have been made in various directions, as acceleration of high integration and acceleration of semiconductor memory devices is generally accelerated. Especially, in terms of design, the purpose of high density, low power, and high speed of semiconductor memory devices has been achieved through arrangement and wiring of circuits and circuit implementation of new concept. The area occupied by the peripheral circuits in the memory device was relatively large compared to the cell array in the core region at the beginning of the development of the semiconductor memory device, but the cell array area gradually occupied most of the semiconductor memory device according to the development tendency of the semiconductor device described above . This trend will be even more prominent in the Giga era. In order to improve the reliability of the semiconductor memory device according to the tendency of high integration of the semiconductor memory device, reduction of power consumption of the memory device is an important design element.

On the other hand, when the power supply of 64K DRAM is down from 12V to 5V in terms of power consumption reduction, a loss of cell signal due to noise occurs in the circuit. It is not a problem that the potential in the cell is reduced from 12V to 10V, but a reduction of 3.5V due to the threshold voltage at 5V causes serious problems. In order to solve the reduction of the supply voltage due to the threshold voltage and noise, a word line voltage drive circuit over the supply voltage is being studied. The structure and operation of such a circuit is described in U.S. Patent No. 4,649,523, entitled " SEMICONDUCTOR MEMORY BOOSTED WORD LINE ", issued March 10, 1987, and in U.S. Patent No. 4,896,297, entitled "CIRCUIT FOR GENERATING A BOOSTED SIGNAL FOR A WORD LINE ".

FIG. 1 is a diagram illustrating word line driving circuits disposed around a sub-cell array block of a 1-megahertz DRAM according to the related art. Referring to FIG. 1, a dynamic random access memory, that is, DRAM, has a memory cell array arranged in row and column directions. For example, 256 rows and 256 column arrays provide 65,536 memory cells. The integrated circuit chip or wafer has a plurality of memory cell arrays, each of which can be further divided into sub memory cell arrays M1 to M8. The memory cell itself has an information storage capacitor and an access transistor, and the information storage capacitor stores a voltage of a "high" level or a voltage of a "low" level. Each of the nodes shown in FIG. 1 represents a sub word line driver (SWD) circuit. The SWD circuit receives the voltage of the third power line 116, which is the output line of the row decoder 102,

PXiB and PXiD (where i is "0, 1, 2, 3" and the main word line driving circuits 105 to 113 are composed of a pair) of the main word line driving circuits 105 to 113 are input, (Boosted) signals to the word lines of the sub memory cell arrays M1 to M8 and outputs the data stored in the storage capacitor through the bit lines in a full output manner. That is, the voltage VPP obtained by adding the threshold voltage of the access transistor to the normal power supply voltage VCC is provided as a word line.

The main word line driving circuits 105 to 113 are connected to the first or second power supply lines 114 and 115 of the word line driving control circuits 103 and 104 to output an output signal PXi (where i is 0, 1, 2, Line drive control circuits 103 and 104 are configured as a pair), and provides the PXiD and PXiB signals to the SWD circuit as described above. At this time, PXiD is the boost voltage VPP and the PXiB signal is the external power supply voltage EVC. Each of the word line drive control circuits 103 and 104 receives a block select signal BLSXi having a level of the internal supply voltage IVC and decoded row address signals DRA01, DRA01B, DRA02 and DRA02B 101, And provides the signal PXi to one side of the main word line driving circuit 105 to 113 via the first or second power supply line 114 or 115, respectively.

FIG. 2A and FIG. 2B are diagrams showing details of the configurations of the word line driving control circuits 103 and 104 and the main word line driving circuits 105 to 113 according to the related art.

2A shows an example in which the block select signal BLSXi having the level of the internal power supply voltage IVC and the decoded row address signals DRA01 to DRA02B101 are inputted and the boost voltage VPP (not shown) supplied from the boost circuit PXi (where i is 0, 1, 2, 3) signals to the respective main word line driving circuits 105 to 113 through the first or second power supply lines 114 and 115, respectively. The inverter 201 and the NAND gate 202 receive the block selection signal BLSXi and the decoded row address signals DRA01 to DRAO2B 101 and receive the inverters composed of the transistor 203, the transistor 204 and the transistors 206 and 209, The block selection signal BLSXi having the level of the internal power supply voltage IVC and the decoded row addresses DRA01 to DR02B 101 are logically combined by the configuration of the load transistor 205 and the inverters 207 and 209 to generate the drive signal PXi . The drive signal PXi is input to an inverter composed of the transistor 210 and the transistor 210 in the main word line driving circuits 105 to 113 configured as shown in FIG. 2B. The inverter receives the PXiD signal having the level of the boosted voltage VPP, Type transistor 213 and converted into a PXiB signal having an external power supply voltage EVC and output. The PXiD signal of the VPP and the PXiB signal of the EVC are input to nodes, that is, SWD circuits (denoted by nodes in FIG. 1).

That is, in the conventional technique, the voltage of the drive signal PXi supplied from the word line drive control circuits 103 and 104 to the first or second power supply lines 114 and 115 is the boosted voltage VPP, A larger current consumption occurs than when an external power supply voltage is used. In addition, when the level of the voltage source driving the circuit is high, the current consumption is increased. In this case, the word line driving which has to take a large value of the loading capacitance corresponding to 1/3 of the capacitance of the capacitors of the word lines When the output voltage of the control circuit is adopted as the boosted voltage VPP, the power consumption of the chip increases. That is, the problem of power consumption causes a problem that the competitiveness is weakened in terms of operating current.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a word line driving circuit of a semiconductor memory device capable of minimizing power consumption.

Another object of the present invention is to provide a word line driving circuit of a semiconductor memory device capable of reducing a chip area and minimizing power consumption.

According to an aspect of the present invention, there is provided a word line driving circuit for a semiconductor memory device, comprising: a word line driving circuit for receiving a block selection signal from a decoder and a decoded row address signal, A word line drive control circuit connected to the first power supply line or the second power supply line to supply the external power supply voltage to the first power supply line and the second power supply line, , The boosted power supply voltage or the external power supply voltage logically combined on one side and the other side of the sub word line driver connected to the word line of each cell array block are logically combined in accordance with an applied boosted power supply voltage or an external power supply voltage, A main word line driving circuit for driving the storage capacitor of the line and outputting full data to the bit line; .

FIG. 1 is a diagram illustrating word line driving circuits positioned around a sub-cell array block according to a related art. FIG.

FIG. 2A and FIG. 2B are diagrams showing a word line drive control circuit and a main word line drive circuit according to the prior art, respectively.

FIG. 3 illustrates word line driving circuits positioned around a sub-cell array block according to an embodiment of the present invention. FIG.

4A and 4B are views showing a sub word line driving circuit and a main word line driving circuit according to an embodiment of the present invention, respectively.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention.

3 is a diagram illustrating word line driving circuits positioned around a sub-cell array block according to an embodiment of the present invention. Referring to FIG. 3, a plurality of sub memory cell arrays M1 to M8 including an access transistor and an information storage capacitor connected to the intersections of word lines and bit lines, SWD circuits indicated as nodes, and main The structure of the word line drive circuits 305 to 313 and the pair of word line drive control circuits 303 and 304, the row decoder 302 and the decoded address signals DRA01, DRA01B, DRA02 and DRA02B 301, . Therefore, detailed description of the configuration is omitted here. In short, the present invention adopts the drive signal PXi output from the word line drive control circuits 303 and 304, which determine the voltages of the first or second power supply lines 314 and 315, as the external supply voltage EVC equal to the bit line power source And main word line driving circuits 305 to 313 which receive the output signal PXi as a cascode voltage switching circuit and output the output signals PXiD and PXiB (i = 0, 1, 2, 3 ) Are provided as a boost voltage level VPP and an external power supply voltage level EVC, respectively. Circuit configurations for implementing this are shown in detail in FIGS. 4A and 4B.

FIGS. 4A and 4B are diagrams showing details of a word line driving control circuit and a main word line driving circuit according to an embodiment of the present invention, respectively. Referring to FIG. 4A, a block select signal BLSXi having a level of the internal power supply voltage EVC and decoded row address signals DRA01 to DRAO2B 301 are input. The EVC PXi signal is supplied to the first or second power supply line 314 or 315 according to the applied external power supply voltage EVC. The inverter 401 and the NAND gate 402 receive the block selection signal BLSXi and the decoded row address signals DRA01 to DRA02B 301 as inputs. The EVC PXi signal is provided by the configuration of the load transistor 406, the inverters 405 and 409, and the inverters composed of the transistor 403 and the transistor 409 and the transistors 407 and 408, which are symmetrical to each other.

The EVC PXi signals output from the word line drive control circuits 303 and 304 having the configuration as shown in FIG. 4A are input to one side of the main word line drive circuit of FIG. 4B. Referring to FIG. 4B, the transistor 411 is connected in series to the step-up power supply voltage terminal VPP and the ground power supply voltage terminal and is gated in accordance with the EVC PXi signal to invert a signal PXi inputted at the level of the step- And a transistor 414, and an inverter of a transistor 414 and a transistor 415 which are symmetrical to the inverter. At this time, the inverter 413 receives the inverted signal EVC PXiB of the EVC PXi signal by the inverter 413 to which the external power supply voltage EVC is applied, and has an output node N1 for outputting the inverted signal EVC PXiB.

The gate of the transistor 414 is connected to the drain of the transistor to be coupled 411 and the connection node of the drain of the transistor 412 to which a signal input to the gate of the transistor 414 is inverted to output the inverted boosted voltage VPP PXiD And an inverter 410 for outputting is connected. Therefore, when the drive signal EVC PXi having the level of the external power supply voltage EVC is input to the gate of the transistor 412 and the inverter 413, the inverted boosted voltage VPP PXiD and the inverted drive signal EVC PXiB are respectively outputted from the inverters 410 and 413 Respectively. With this operation, the EVC PXiB and VPP PXiD signals of the output node N1 are respectively input to the above-described SWD circuit. Here, the other side of the SWD circuit drives the data storage capacitor in response to the output signal of the row decoder 302 through the third power supply line 316 shown in FIG. 3 to output the full data to the bit line.

In the embodiment of the present invention, the dynamic random access device is exemplified, but the same method can be applied to similar fields. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the following claims. While the present invention has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit of the invention .

Therefore, according to the present invention as described above, compared with the case where the boost voltage VPP is used as the power source of the conventional sub word line driving circuit, according to the embodiment of the present invention, when used as the external power voltage EVC, The current can be reduced and the chip size can be reduced.

Claims (7)

In a word line driving circuit of a semiconductor memory device, A word line drive control circuit for logically combining the block select signal from the decoder and the external supply voltage applied in response to the decoded row address signal to provide the external supply voltage to the first power supply line and the second power supply line, And a control circuit connected to the first power line or the second power line to input the external power source voltage and logically combine the power source voltage according to an applied boosted power source voltage or an external power source voltage. And a main word line driving circuit for driving the storage capacitor of the word line and outputting the full data to the bit line by providing the boosted power supply voltage or the external power supply voltage logically combined with the driver. in. 2. The word line driving circuit of claim 1, wherein the block selection signal and the decoded row address signal are at an internal power supply voltage level, and the external power supply voltage is used as a voltage source of a bit line. 2. The semiconductor memory device according to claim 1, wherein the other side of the sub word line driver is connected to a third power source line, and an output signal of an internal power source voltage or an external power source voltage level of the row decoder is inputted through the third power source line. Word line driving circuit. 2. The word line driving circuit of claim 1, wherein the main word line driving circuit includes a cascode voltage switching circuit. The method as claimed in claim 1 or 4, wherein the main word line driving circuit is connected in series to a step-up power supply voltage terminal and a ground power supply voltage terminal and is gated according to the external power supply voltage, A first inverter composed of a first type transistor and a first type transistor, A second inverter which is symmetrical with the first inverter and is composed of a second type transistor and a second type transistor, and a gate of the second type transistor is connected to the external power supply voltage inverted by the third inverter to which the external power supply voltage is applied And outputs a boosted voltage which is gated by the boosted power supply voltage applied to the gate of the second transistor and is inverted by the fourth inverter to the gate of the second transistor. in. A plurality of word line drive control circuits responsive to a decoded row address signal of an internal power supply voltage and connected to a first or second power supply line which is an output line of the word line drive control circuit, A plurality of main lines for driving a storage capacitor of a word line connected to the sub word line driver circuit by providing an external power source voltage or a boosted power source voltage to each sub word line driver circuit connected to a line, In a word line driving circuit of a semiconductor memory device including a word line driving circuit, Wherein each of the word line drive control circuits provides an external power supply voltage equal to that of the bit line power source to the first or second power supply line to minimize the power consumption of the chip. . 7. The word line driving circuit of claim 6, wherein the main word line driving circuit includes a cascode voltage switching circuit.