JP2000215676A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which can reduce the circuit area. SOLUTION: This semiconductor memory device is provided with a plurality of memory cells MCs arranged in the row and column directions, a plurality of word lines WL extending in the row direction, a plurality of bit lines BL extending in the. column direction, a plurality of bit line bars/BL extending in the column direction, a plurality of column selection plate drive line CD extending in the column direction and an equalizer/precharge circuit 7 and a sense amplifier 8. A plurality of memory cells MC have a capacitance element Cs and a MOS transistor Qc and the capacitance element forms a ferroelecric material film between a first electrode and a second electrode to store and hold a binary information depending on the polarizing condition of the ferro electric material film. A MOS transistor has a first electrode, a second electrode and a gate electrode, connects the first electrode to the first electrode of capacitance element, connects the gate electrode to the corresponding word line, connects the one second electrode of a plurality of MOS transistors to the corresponding bit line and one second electrode among a plurality of MOS transistors to the corresponding bit line bar.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric memory device that drives only a plate electrode of one memory cell in one access operation.

[0002]

2. Description of the Related Art A semiconductor memory device using a ferroelectric (hereinafter, referred to as a ferroelectric memory device) is a nonvolatile memory that stores data in a polarization direction of a ferroelectric. FIG. 7 shows a conventional example of a nonvolatile semiconductor memory device using such a ferroelectric film.

The ferroelectric memory device shown in FIG. 7 has a capacitor Cs formed by sandwiching a ferroelectric film between two opposing electrodes, one electrode of the capacitor Cs, and a transistor Q.
and a memory cell MC connected to one of the source electrode and the drain electrode c. The plurality of memory cells MC are arranged in a row direction and a column direction.

A plurality of word lines WL _{0 to} WL _{2m + 1} are provided corresponding to a plurality of memory cells MC in a row direction, and are connected to gate electrodes of transistors Qc of memory cells MC in a corresponding row. When the level of the plurality of word lines WL _{0 to} WL _{2m + 1} is the selected level, the memory cell MC connected to the selected level word line is in the selected state.

A plurality of bit lines BL _{0 to} BL _n and a plurality of bit lines / BL ₀ to / BL _n are connected to a plurality of memory cells M
C is provided corresponding to the column of C, and the MO of the corresponding memory cell is
Connected to the other of the source electrode and drain electrode of S transistor Qc.

A plurality of plate lines PL _{0 to} PL _m are provided at a ratio of one in two rows of a plurality of memory cells MC, and the other electrode (hereinafter, plate electrode) of the capacitive element Cs of the two rows of memory cells MC is provided. Is written).

A plurality of MOS transistors T ₀ -T
_{2m + 1} are provided corresponding to a plurality of word lines WL ₀ to WL _{2m + 1,} the plurality of MOS transistors T ₀ through T _{2m + 1} of the gate electrode is connected to a corresponding word line, a plurality of MOS transistors The source electrodes of T _{0 to} T _{2m + 1} are connected to corresponding plate lines, and a plurality of MOS transistors T _{0 to} T 2
_{The 2m + 1} drain electrode is connected to the drive line DL.

The plate drive signal generation circuit 1 supplies a plate drive signal to the drive line DL.

The read operation of the ferroelectric memory device shown in FIG. 7 will be described with reference to FIG.

FIG. 8 is a timing chart of the ferroelectric memory device shown in FIG.

In a standby state before a word line (for example, WL ₀ ) rises to a selected level (high level), bit lines BL _{0 to} BL _n and bit lines / BL ₀ to / BL.
BL _n and drive line DL are at the ground potential level. When the word line WL ₀ goes high, the memory cell MC connected to the word line WL ₀ is in the selected state, and the transistor T ₀ is turned on, so that the drive line DL is connected to the plate line PL ₀ .

[0012] Next, the plate driving signal becomes plate drive voltage Vp1, the voltage Vp1 is supplied to the plate line PL _0. As a result, information stored in these memory cells MC is read onto bit line BL ₀ to BL _n. Bit lines BL _0-
The BL _n and the bit line paired bar / BL ₀ ~ / BL _n,
When a reference cell (not shown) is selectively connected, a reference voltage level is generated. This reference voltage is set to an intermediate potential just after the bit line potential generated by the stored information “1” and “0” of the memory cell MC. This can be realized by adjusting the capacitor size of the reference cell.

By amplifying the difference voltage between the paired bit lines BL _{0 to} BL _n and bit lines / BL ₀ to / BL _n , the storage information of the selected memory cell is read out. Can be put out. Thereafter, the plate driving signal becomes the ground potential, by also to the ground potential the potential of the plate line PL _0, the stored information is written again to the memory cells in the selected state.

In the ferroelectric memory device, positive and negative induced polarization is applied to the ferroelectric film of the capacitance element Cs of the memory cell MC to store information, and the state of the induced polarization is detected to read the stored information. Therefore, it is necessary to supply a predetermined potential Vp1 to the plate line as in the above-described example, and since the capacitance element Cs is formed of a ferroelectric material, the capacitance value is larger than that of a normal DRAM. Become. In addition, Au, P
Noble metals such as t and Ru are used. It is difficult to increase the film thickness of these precious metals due to the problem of workability, and widening the wiring width is disadvantageous from the viewpoint of high density by miniaturization. Therefore, it is difficult to reduce the wiring resistance. For this reason, the time constant of the plate line becomes large, the time for driving the plate line becomes long, and it has been difficult for the conventional ferroelectric memory device to operate at high speed.

Further, since charging and discharging are performed in the plate line, power consumption also increases.

As described above, the conventional ferroelectric memory device has a structure in which the plate line is driven at a predetermined potential for each access, so that the time required to drive the plate line is long and high-speed operation is possible. In addition, there is a problem that power consumption increases due to difficulty in charging and discharging the plate line.

As a method for reducing the time required for driving the plate line and the power consumption, we have disclosed in Japanese Patent Application No. 10-371.
No. 52 shows a method of driving only the plate electrode of one memory cell in one access operation.

The ferroelectric memory device disclosed in Japanese Patent Application No. 10-37152 will be described below with reference to FIGS.

FIG. 9 is a circuit diagram showing a ferroelectric memory device shown in Japanese Patent Application No. 10-37152, and FIG. 10 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG.

The ferroelectric memory device shown in FIG. 9 includes a plurality of memory cells MC arranged in a row direction and a column direction. The memory cell MC includes two ferroelectric films opposed to each other.
A capacitor Cs formed between two electrodes, a transistor Qa connecting one of a source electrode and a drain electrode to one electrode of the capacitor Cs, and a capacitor Qs connecting one of the source electrode and the drain electrode to the capacitor Cs And a transistor Qd connected to the other electrode (hereinafter, referred to as a plate electrode).

A plurality of word lines WL ₀ , WL ₁ ,... Are provided corresponding to a plurality of memory cell rows, and are connected to the gate electrodes of transistors Qa and Qd of the memory cells in the corresponding row.

A plurality of bit lines BL ₀ , BL ₁ ,... And bit lines / BL ₀ , / BL ₁ ,... Are provided corresponding to the columns of the plurality of memory cells MC. Connected to the other of the source electrode and the drain electrode of transistor Qa.

In each column, the other of the source electrode and the drain electrode of transistor Qd of the memory cell is connected to column selection plate drive lines CD ₀ , CD ₁ ,. Here, in the memory cell in the ith row and the jth column, the plate electrode node of the capacitive element Cs is set to PL (i,
j).

The ferroelectric memory device shown in FIG. 9 is further input from the outside (or generated internally).
An address buffer 2 for receiving an address signal, a row decoder 3 and a column decoder 4 for inputting an output signal from the address buffer 2, and an address decode signal output from the row decoder 3 are input to the word lines WL ₀ ,
A word line drive circuit 5 for driving WL ₁ ,... And a column address decode signal output from the column decoder 4 are input, and column select plate drive lines CD ₀ , CD ₁ ,.
And a column selection plate drive circuit 6 for driving the same.

The column selection plate drive line CD
₀ , CD ₁ ... Are formed by polysilicon wiring or ordinary metal wiring (aluminum wiring or the like).

The operation of the ferroelectric memory device shown in FIG. 9 will be described with reference to FIG.

FIG. 10 is a timing chart of the ferroelectric memory device shown in FIG.

In the standby state before the word line rises to the selection level, the bit lines BL ₀ , BL ₁ ,... And the bit lines / BL ₀ , / BL _1, and the column selection plate drive lines CD ₀ , CD _1. ,... Are at the ground potential level. When a predetermined word line (for example, WL _i ) attains a selected level in response to an external address signal, transistor Q of memory cell MC connected to this word line WL _i
a becomes conductive, and one electrode of the capacitive element Cs is at the same ground potential level as the bit line or the bit line bar.

Further, and also conducts transistor Qd to be connected to the word line WL _i, corresponding column selection plate driving lines CD _0, CD _1, ... signals of the plate electrode PL (i,
0), PL (i, 1),...

Further, when a predetermined column selection plate drive signal (for example, CD _j ) is brought to a selection level by an external column address input, only the plate electrode PL (i, j) is at the high level Vp1, and the remaining plate electrodes are at the ground potential. Remains at the level.

As a result, the memory cell M in the i-th row and the j-th column
Only information stored in C is read to the bit line BL _j. That is, when the transistor Qa is on, the bit line / B
Negative direction of the electric field -Emax between L _j and the plate line PL
Is applied, from the “1” data held at the point c in the hysteresis characteristic of FIG. 6, Pmax +
The corresponding charge and Pr can be read on the bit line bar / BL _j, held in a point "0" from the data, Pm
The electric charge corresponding to ax-Pr can be read.

The level of the bit line bar / BL _j forming the bit lines BL _j and pair reference cell (not shown)
Is set to the reference voltage level. The potential difference between the bit lines BL _j and the bit line bar / BL _j forming these pairs by sensing (amplification) can be read out information stored in the memory cells in the selected state to the outside.

It should be noted, not selected for the (j-th non-column) memory cell MC, and does not occur potential difference between the bit lines BL _j and the bit line bar / BL _j, information can sense (amplification) It is not read outside. That is, only the storage information of the single memory cell MC in the i-th row and the j-th column is sensed.

Thereafter, the column selection plate drive line CD _j
Return to the ground potential, the plate line PL
The voltage of (i, j) becomes the ground potential, and the stored information is written again to the selected memory cell. Here, 1
Reading and rewriting are completed by two column selection plate driving signal pulses, but reading is performed by one column selection plate driving signal pulse while the word line is at the selection level, and the second column selection plate driving is performed. Rewriting can be reliably performed by a signal pulse. Here, the rewriting means that the state at the point c changes to the state at the point a in the above-mentioned reading, and the data at the point c is destroyed. This is the operation of applying the voltage and returning the state to the point c again.

In these cases, since the capacitive element Cs is disconnected from the bit line by the transistor Qa for the memory cell MC other than the i-th row that is not selected, it is determined whether the voltage Vp1 is applied to the plate line PL. Regardless of the voltage, there is no change in the voltage between the electrodes of the capacitive element Cs, so that the polarization coast information is not destroyed. Further, connected to the word line WL _i to be selected, the signal of the column selection plate driving lines CD _j is respect to the non-selection level memory cell MC, and the sense operation is not performed, there is no possibility that the polarization information is destroyed .

According to the ferroelectric memory device shown in FIG.
In one access operation, the column selection plate drive circuit operates the plate electrode PL (i, i) of the single memory cell MC.
Only j) needs to be driven, and since the capacitance value and the resistance value are small, the time required to drive the plate electrode is shortened, and high-speed operation and low power consumption can be realized. Further, since only the storage information of the single memory cell MC is sensed, the current consumption in the sensing operation is greatly reduced.

[0037]

However, in the above-mentioned ferroelectric memory device, one memory cell is composed of two transistors and one ferroelectric capacitor, so that one transistor and one ferroelectric There is a problem that the circuit area of the above-described ferroelectric memory device is larger than that of a memory cell including a body capacitance element.

An object of the present invention is to provide a semiconductor memory device having a small circuit area in view of the above problems.

[0039]

A semiconductor memory device according to the present invention comprises a plurality of memory cells arranged in a row direction and a column direction, a plurality of word lines extending in the row direction, and a plurality of bit lines extending in the column direction. A plurality of bit line bars extending in the column direction, a plurality of column selection plate drive lines extending in the column direction, an equalize / precharge circuit, and a sense amplifier. Each has a capacitor and a transistor, and the capacitor is formed with a ferroelectric film interposed between a first electrode and a second electrode opposed to the first electrode. Stores and retains binary information depending on the polarization state,
The transistor has a first electrode, a second electrode, and a gate electrode, the first electrode is connected to a first electrode of the capacitor, the gate electrode is connected to a corresponding word line, A second electrode of one of the transistors is connected to a corresponding bit line; a second electrode of another transistor different from one of the plurality of transistors is connected to a corresponding bit line bar; A sense amplifier amplifies a voltage difference between the corresponding bit line and the corresponding bit line bar, and the equalize / precharge circuit determines a voltage between the corresponding bit line and the corresponding bit line bar. Precharge and equalize, and one of the plurality of column selection plate drive lines is
The first electrode is connected to one of the plurality of capacitance elements, thereby achieving the above object.

The semiconductor memory device further includes a plate drive signal generation circuit, and the plate drive signal generation circuit connects the plurality of column selection plate drive lines with an output signal generated based on a decode signal of a column address signal. The column selection plate drive line to which the output signal is controlled and propagated may be in a selected state, and the column selection plate drive line to which the output signal is not propagated may be in a floating state (non-selected state).

The plate drive signal generation circuit has a main line and a plurality of switch means connected to the plurality of column selection plate drive lines, and the plurality of switch means are provided by a decode signal of the column address signal. At least one may be selectively activated.

Each of the plurality of switch means is N
It may be a transfer gate formed by connecting a channel transistor and a P-channel transistor in parallel.

The column selection plate drive line is selected by a logical product of a column selection signal generated based on a decode signal of a column address signal and an output signal generated by a plate drive signal generation unit. The drive line may be at a high level only when both the column selection signal and the output signal generated by the plate drive signal generation unit are activated, and may be at a low level in other states.

[0044] The sense amplifier may be alternatively operated in accordance with a selected column selection plate drive line.

[0045]

Embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a ferroelectric memory device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG.

The ferroelectric memory device 100 shown in FIG.
A plurality of memory cells M arranged in a row direction and a column direction
C, a plurality of word lines WL _0, WL _1, ..., a plurality of bit lines BL _0, BL _1, ..., a plurality of bit lines bar / BL _0, / B
L ₁ ,..., A plurality of column selection plate drive lines CD ₀ , CD
₁ , ..., column selection plate drive circuit 6, equalize /
It includes a precharge circuit 7, a sense amplifier 8, an address buffer 2, a row decoder 3, a column decoder 4, and a word line drive circuit 5. The memory cell MC includes two electrodes (a first electrode and a second electrode) that face the ferroelectric film.
And one of the source electrode and the drain electrode (first electrode) formed between the capacitor Cs and the capacitor Cs.
Transistor Qc connected to one electrode (first electrode) of
It is composed of

The plurality of word lines WL ₀ , WL ₁ ,... Are connected to the gate electrodes of the transistors Qc of the memory cells MC in the corresponding row direction.

The plurality of bit lines BL ₀ , BL ₁ ,... And the plurality of bit lines / BL ₀ , / BL ₁ ,. (Second electrode).

The column selection plate drive lines CD ₀ , CD ₁ ,
Are connected to the other electrode (second electrode) of the capacitor Cs of the corresponding memory cell MC in the column direction.

The equalize / precharge circuit 7 equalizes the voltage between the bit line BL and the bit line / BL paired with the bit line BL, and precharges to the ground potential. Note that the bit line BL and the bit line / BL that make a pair are adjacent to each other.

The sense amplifier 8 amplifies a voltage between the bit line BL and a bit line / BL paired with the bit line BL.

The address buffer 2 receives an externally input (or internally generated) address signal.

Row decoder 3 and column decoder 4
Receives an output signal from the address buffer.

The word line drive circuit 5 receives the address decode signal output from the row decoder and drives the word lines WL ₀ , WL ₁ ,.

The column selection plate drive circuit 6 receives the column address decode signal output from the column decoder 4, and receives the column selection plate drive lines CD ₀ , CD ₁ ,
Drive ...

The operation of the ferroelectric memory device 100 will be described with reference to FIG.

In the standby state before the word lines rise to the selected level, bit lines BL ₀ , BL ₁ ,... And bit lines / BL ₀ , / BL ₁ ,. Is done. At this time, the column selection plate drive lines CD ₀ , CD ₁ ,... Are also at the ground potential level.

When a predetermined word line (for example, WL _i ) attains a selected level in response to an external address signal, transistor Qc of memory cell MC connected to this word line WL _i is turned on, and one of capacitance elements Cs is turned on. Is applied with the ground potential on the bit line.

When receiving the external column address, the column selection plate drive circuit 6 sets a predetermined column selection plate drive signal to a selection level. For example, when the signal of the column selection plate drive line _CDj reaches the selection level,
Only the other electrode (plate electrode) of the capacitive element Cs in the column is at a high level, and the plate electrodes PL of the capacitive elements Cs other than the j-th column remain at the ground potential. Thereby, the i-th
A voltage is applied only between both electrodes of the capacitive element Cs of the memory cell MC in the row j-th column.

As a result, the memory cell M at the i-th row and the j-th column
Only serial billion information of C is read to the bit line BL _j. That is, a negative electric field −Ema is applied between both electrodes of the capacitive element Cs.
By applying x, in the hysteresis characteristic shown in FIG. 6, from the “1” data held at point c, P
max + can be read charges corresponding to the bit lines BL _j to Pr, from the "0" data held in a point, P
The electric charge corresponding to max-Pr can be read.

[0062] level of the bit line bar / BL _j forming the bit lines BL _j and pair reference cell (not shown)
Is set to the reference voltage level. By differential potential between the bit lines BL _j and the bit line bar / BL _j forming these pairs are sense (amplification) can be read out information stored in the memory cells in the selected state to the outside.

[0063] Incidentally, not selected for the (i-th row and the j other than a column) memory cell MC, and it does not occur potential difference between the bit lines BL _j and the bit line bar / BL _j,
Sense amplifiers so that only sense (amplification) potential difference between the bit lines BL _j and the bit line bar / BL _j of the j-th column is operated. As a result, power consumption can be further reduced.

It is to be noted that, of the capacitance elements Cs belonging to the j-th column and having one electrode of the capacitance element Cs at a high level, the other electrode of the capacitance element Cs belonging to a row other than the i-th row is in an open state, and the parasitic capacitance Since only a small diffusion capacitance exists, no voltage is applied between the electrodes of the capacitance element Cs, and the polarization information remains without being destroyed.

Thereafter, the column selection plate drive line CD _j
Returns to the ground potential, the voltage of one electrode of the capacitive element Cs becomes the ground potential, and the stored information is written again to the selected memory cell.

The rewriting here means that the state at the point c is changed to the state at the point a in the above-mentioned reading, and the data at the point c is destroyed. This is an operation in which the electric field Emax is applied and the state at the point a is returned to the state at the point c again. The destructive reading for the data at the point c is because the polarization value Pr at the point c changes to the polarization value -Pr at the point a.

In these cases, the memory cells MC not selected in the rows other than the i-th row are separated from the capacitor Cs or the bit line by the transistor Qc. For this reason, the voltage between the electrodes of the capacitive element Cs does not change regardless of the voltage change of the bit line BL or the bit line / BL, so that the polarization information is not destroyed. Further, connected to the word line WL _i to be selected, the column selection plate driving lines CD _j is respect to the non-selection level memory cell MC, and the sense operation is not performed, there is no possibility that the polarization information is destroyed.

According to the present embodiment, in one access operation, the column selection plate drive circuit 6 only needs to charge / discharge only the capacitance element Cs of the selected memory cell MC. And the resistance value is small. Therefore, the time required for charging and discharging is reduced, and the ferroelectric memory device of the present embodiment can operate at high speed and with low power consumption.

In this embodiment, since only the information stored in the selected single memory cell MC is sensed,
The number of elements constituting the memory cell MC can be reduced while taking advantage of the fact that the current consumption in the sensing operation can be significantly reduced.

In this embodiment, a plurality of columns can be driven simultaneously by one access. When driving a plurality of columns simultaneously with one access, as described above,
By driving only the sense amplifier connected to the driven column and amplifying only the potential difference between the corresponding bit line and bit line bar, a plurality of selected column data are read out and unselected. Column data (polarization information) is stored without being destroyed.

(Second Embodiment) FIG. 3 is a circuit diagram showing a ferroelectric memory device according to a second embodiment of the present invention. FIG. 4 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG.

The ferroelectric memory device 200 shown in FIG.
A plurality of memory cells M arranged in a row direction and a column direction
C, a plurality of word lines WL _0, WL _1, ..., a plurality of bit lines BL _0, BL _1, ..., a plurality of bit lines bar / BL _0, / B
L ₁ ,..., A plurality of column selection plate drive lines CD ₀ , CD
_1, ..., column selection plate driving circuit 16 includes equalizing / precharging circuit 7, a sense amplifier 8, an address buffer 2, row decoder 3, a column decoder 4, and a word line driving circuit 5.

The structure of the ferroelectric memory device 200 is the same as that of the ferroelectric memory device 100 except for the structure of the column selection plate drive circuit 16.

The column selection plate drive circuit 16 outputs a plate drive signal generation circuit 10 for outputting the main signal MDL to the main line 9 and column address decode signals AD ₀ ,..., AD _j,. It has an AND gate electrode 11 for receiving the main signal MDL.

The operation of the ferroelectric memory device 200 will be described with reference to FIG.

[0076] In the standby state before the word line rises to a high level, the bit lines BL _0, BL _1, ... and the bit line bar / BL _0, / BL _1, and..., The column selection plate driving lines CD ₀ ,..., CD _j ,... Are at the ground potential level. In response to an external row address signal input, a predetermined word line (for example, WL _i ) attains a selected level. Transistor Qc of the memory cells MC connected to the word line WL _i became selected level is rendered conductive, one electrode of the capacitor Cs becomes the same ground potential level to the bit line or bit line bar.

The high level main signal MDL is output from the plate drive signal generation circuit 10 to the main line 9, and the address decode signal A is output in response to the external address signal.
D _0, ..., AD _j, the example address decode signal AD _j of ... is selected by AND gate 11, only the column selection plate driving signal line CD _j becomes high level. Therefore, only the other electrode of the capacitance element Cs in the j-th column is at the high level, and the other electrode of the capacitance element Cs other than the j-th column remains at the ground potential level.

As a result, as in the first embodiment, the i-th
Only information stored in the row and the j th column of the memory cell MC is read onto bit line BL _j. After the read information is sense-amplified, it is read outside. After this reading, the main signal while the address decode signal AD _j is at the selection level M
By returning DL to the ground potential, the storage information is written again to the selected memory cell MC. When the main signal MDL is at the ground potential, the column selection signal line CD
The voltage of _j becomes the ground potential.

(Third Embodiment) FIG. 5 is a circuit diagram showing a ferroelectric memory device according to a third embodiment of the present invention.

The ferroelectric memory device 300 shown in FIG.
A plurality of memory cells M arranged in a row direction and a column direction
C, a plurality of word lines WL _0, WL _1, ..., a plurality of bit lines BL _0, BL _1, ..., a plurality of bit lines bar / BL _0, / B
L ₁ ,..., A plurality of column selection plate drive lines CD ₀ , CD
_1, ..., column selection plate driving circuit 26, equalize / precharge circuit 7, a sense amplifier 8, an address buffer 2, row decoder 3, a column decoder 4, and a word line drive circuit 5.

The configuration of the ferroelectric memory device 300 is the same as that of the ferroelectric memory device 100, except for the configuration of the column selection plate drive circuit 26.

The column selection plate driving circuit 26
Plate drive signal for outputting a drive signal MDL to the main line 9
Generation circuit 10 and a plurality of N-channel MOS transistors
QC ₀And a plurality of P-channel MOS transistors QC₁
And switch means having N channel MOS
Transistor QC₀Of the drain or source electrode
One is the corresponding column selection plate drive line CD_o, ...
・, CD_jAnd an N-channel MOS transistor Q
C₀The other of the drain electrode or source electrode
Connected to line 9. Also, a P-channel MOS transistor
Data QC₁One of the drain or source electrode of
Corresponding column selection plate drive line CD_o, ..., CD_jTo
Connected, P-channel MOS transistor QC₁Dre
The other of the in electrode or the source electrode is connected to the main line 9
Is done.

The gate electrode of N-channel MOS transistor QC ₀ is connected to a corresponding column address decode signal AD.
_0, ..., AD _j, ... I receive the gate electrode of the P-channel MOS transistor QC _1, the corresponding inverted column address decode signal _{AD 0, ..., AD j,} ... receive.

The operation of the ferroelectric memory device 300 is based on the column selection plate drive lines CD ₀ ,.
The operation of the ferroelectric memory device 200 is different only in that the levels of D _j ,.

Column selection plate drive line C in non-selected state
Even if _Do ,..., _CDj ,... Are at the ground potential or in the floating state, the polarization state of the capacitor of the unselected memory cell MC is not destroyed, and the data of the memory cell MC is stored. Has not changed.

It is possible to configure the switch means having a plurality of N-channel MOS transistors QC ₀ and a plurality of P-channel MOS transistors QC ₁ in the column selection plate drive circuit 26 with only N-channel MOS transistors. However, there is a possibility that the threshold voltage Vth of the N-channel MOS transistor, the potential of the column selection plate line CD _j decreases. Therefore, when the level of the main signal MDL output from the plate drive signal generation circuit is low, it is preferable to use the column selection plate drive circuit 26 as shown in FIG.
In the column selection plate driving circuit 26 shown in FIG. 5, it is possible to prevent a reduction in the potential of the column selection plate line CD _i.

Further, the switching means having a plurality of N-channel MOS transistors QC ₀ and a plurality of P-channel MOS transistors QC ₁ in the column selection plate drive circuit 26 can be constituted only by P-channel MOS transistors.

[0088]

The memory cell of the semiconductor memory device according to the present invention comprises one capacitance element and one MOS transistor. Therefore, the circuit area of the semiconductor memory device of the present invention can be made smaller than that of the conventional semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a ferroelectric memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG.

FIG. 3 is a circuit diagram showing a ferroelectric memory device according to a second embodiment of the present invention.

4 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG. 3;

FIG. 5 is a circuit diagram showing a ferroelectric memory device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a hysteresis characteristic of a ferroelectric memory.

FIG. 7 is a circuit diagram showing a conventional ferroelectric memory device.

8 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG. 7;

FIG. 9 is a circuit diagram showing a conventional ferroelectric memory device.

10 is a diagram showing a timing chart of the ferroelectric memory device shown in FIG. 9;

[Explanation of symbols]

 2 Address Buffer 3 Row Decoder 4 Column Decoder 5 Word Line Drive Circuit 6 Column Select Plate Drive Circuit 7 Equalize / Precharge Circuit 8 Sense Amplifier 100 Ferroelectric Memory Device BL Bit Line / BL Bit Line Bar WL Word Line CD Column Select Plate Drive line

Claims (6)

[Claims] A plurality of memory cells arranged in a row direction and a column direction; a plurality of word lines extending in the row direction; a plurality of bit lines extending in the column direction; a plurality of bit line bars extending in the column direction; A semiconductor memory device including a plurality of column selection plate drive lines extending in a column direction, an equalizing / precharge circuit, and a sense amplifier, wherein each of the plurality of memory cells includes a capacitor and a transistor; The capacitor is formed with a ferroelectric film interposed between a first electrode and a second electrode facing the first electrode, and stores and holds binary information according to a polarization state of the ferroelectric film. The transistor has a first electrode, a second electrode, and a gate electrode, the first electrode is connected to a first electrode of the capacitor, and the gate electrode is connected to a corresponding word line, A second electrode of one of the plurality of transistors is connected to a corresponding bit line; a second electrode of one of the plurality of transistors is connected to a corresponding bit line bar; Amplifying a voltage difference between a corresponding bit line and the corresponding bit line bar, wherein the equalizing / precharge circuit precharges and equalizes a voltage between the corresponding bit line and the corresponding bit line bar. A semiconductor memory device in which one of the plurality of column selection plate drive lines is connected to a second electrode of one of the plurality of capacitance elements. 2. The semiconductor memory device further includes a plate drive signal generation circuit, wherein the plate drive signal generation circuit drives the plurality of column selection plate by an output signal generated based on a decode signal of a column address signal. 2. The column selection plate drive line to which the output signal is propagated is in a selected state, and the column selection plate drive line to which the output signal is not propagated is in a floating state (non-selected state).
3. The semiconductor memory device according to claim 1. 3. The plate drive signal generation circuit has a main line and a plurality of switch means connected to the plurality of column selection plate drive lines, and the plurality of switches are provided by a decode signal of the column address signal. 3. The semiconductor memory device according to claim 2, wherein at least one of the means is selectively activated. 4. Each of said plurality of switch means,
4. The semiconductor memory device according to claim 3, wherein the transfer gate is formed by connecting an N-channel transistor and a P-channel transistor in parallel. 5. The column selection plate drive line is selected by a logical product of a column selection signal generated based on a decode signal of a column address signal and an output signal generated by a plate drive signal generation unit. 2. The semiconductor according to claim 1, wherein the selection plate drive line is at a high level only when both the column selection signal and an output signal generated by the plate drive signal generation unit are activated, and at a low level in other states. Storage device. 6. The semiconductor memory device according to claim 1, wherein said sense amplifier is selectively operated in accordance with a selected column selection plate drive line.