JP3715781B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention Imaging device It is about.
[0002]
[Prior art]
In recent years, CCD pixels have been increased in height due to improvements in CCD manufacturing technology. Here, many products adopting a method of reading only a specific area within an effective area have been commercialized. For video movie cameras and digital still cameras, a camera shake prevention mechanism, an electronic zoom mechanism, and a liquid crystal display are being used. Such a method is used to establish a finder display. Further, partial reading is also performed for auto focus, auto iris, and the like, and various driving methods for partial reading are used depending on applications. In the digital still camera, continuous shooting is emphasized in addition to the normal mode of high pixel and high quality, and partial reading is also used for the continuous shooting mode with a small number of pixels.
[0003]
Hereinafter, an example of the partial reading described above in the digital still camera will be described.
[0004]
FIG. 10 is a diagram showing a configuration of a commonly used interline CCD. In the figure, reference numeral 10 is a PD (photodiode) for photoelectric conversion, and 11 is a VCCD (vertical CCD) for transferring signal charges of the PD 10, which normally has a four-phase drive configuration. Reference numeral 12 denotes an HCCD (horizontal CCD) for transferring signal charges for each line transferred from the VCCD 11, and 13 denotes an output amplifier for using the signal charges for each pixel transferred from the HCCD 12 as voltage signals.
[0005]
In this type of sensor, each signal charge accumulated in each PD 10 is normally read out to the adjacent VCCD 11 and the signal charges of the upper and lower two pixels are immediately added, and then the added two lines are regarded as one line. The data are sequentially read out through the HCCD 12. As shown in the figure, the lines added each time the field is read back and forth (field reading). In addition, all pixels may be read out without adding (reading out all pixel frames). In this case, all pixels on the odd lines are read first, and then all pixels on the even lines are read.
[0006]
Next, the output part of the CCD will be described.
[0007]
FIG. 11 is a diagram showing the configuration of the output section of the CCD which is an image sensor. In the figure, reference numeral 101 denotes a transfer gate in the final stage of the second phase of the two-phase drive horizontal CCD, and the signal charge is set to a constant potential in the next stage output gate 102 (normally inside the sensor) by the high and low gates. Are transferred to the floating diffusion 103. The signal charge transferred to the floating diffusion gate is output as a voltage by the output amplifier 106 in accordance with the floating diffusion gate potential. The output amplifier 106 is usually composed of a source follower.
[0008]
A reset gate 104 functions as a wall when signal charges are stored in the floating diffusion 103, and becomes High and Low in order to sweep the signal charges in the floating diffusion 103 into the reset drain 105.
[0009]
12 and 13 are diagrams showing the relationship between the movements of the above-described parts and the output signal. FIG. 12 is a potential profile of each part of FIG. 11, and FIG. 13 is a pulse (ΦH2) applied to the second phase gate of the horizontal transfer CCD. ), Reset gate pulse (ΦR), and output voltage (Vccdout).
[0010]
As can be seen from these figures, before the signal charge of each pixel is read (ts), the output of the floating diffusion gate when there is no signal charge is always read (tr). In the following, the tr period in the figure is called the reset period, the tf period is called the field through period, the output signal level at this time is called the field through level, the ts period is called the image signal period, and the output signal level at this time is called the image signal level. .
[0011]
What should be noted here is related to the readout frequency of the CCD, but usually the upper limit of the readout frequency of the CCD is limited by the performance of the amplifier. Outputs as shown in FIGS. 12 and 13 are amplified after being correlated double sampled (CDS) outside the CCD. For this reason, the period during which the field through level and the image signal level of the output waveform are stably output must be sufficient.
[0012]
In addition, the influence of the shaking at the rise and fall of the horizontal drive pulse and reset pulse must be avoided. Furthermore, there is a restriction on the frequency characteristics of the output amplifier. Due to these restrictions, the readout frequency of the current CCD is around 10 MHz. However, driving at a frequency that can secure transfer efficiency necessary for handling an HCCD image is higher than this, and driving at several times the frequency is possible.
[0013]
Next, an example in which only a central 640 × 480 pixel area is extracted with a 960 × 600 pixel sensor will be described with reference to FIG. With this pixel size sensor, the number of readout lines in one field is 300 lines for both field readout and frame readout (in the field readout, two lines added are one line, and in all pixel readout, only even or odd numbers are thinned out) Line).
[0014]
Normally, in this case, immediately after the PD signal charge is read out to the VCCD (t1) (in the case of field reading, 2 pixels are added immediately, but immediately after that), the VCCD is driven at high speed for 30 lines. The charge is thrown away to the drain via the HCCD (t2). In the case of a video camera, this operation is performed within the vertical blanking period.
[0015]
The frequency of the drive pulse at this time is set to about 300 KHz to 400 KHz because it is necessary to maintain normal transfer efficiency. In addition, the vertical transfer electrode has a large capacity, and can only produce such a driving speed.
[0016]
Further, the drain may be provided horizontally in the HCCD, may be provided in the subsequent stage of the HCCD, and may be substituted by a drain configured in the output amplifier unit. Therefore, in the figure, it is shown that the transfer pulse of the HCCD is driven during the period t2, but there is a method in which this is stopped. Immediately thereafter, high-speed transfer (usually several tens of MHz) of the HCCD for reading the remaining charge remaining in the HCCD is performed (t3).
[0017]
Further, after 30 lines of vertical high-speed transfer and HCCD clearing operation, 240 lines are sequentially read out line by line based on the horizontal synchronization signal (t4). Therefore, in the case of a video camera, if the HCCD is 960 pixels, it is driven at about 16 MHz. The information in one line is read out in accordance with the video signal at the center 640 pixels using the memory as a buffer. After 240 lines are read, the remaining 30 lines are discharged at high speed (t5). The operation at this time is also performed within the V blanking period at a driving speed of 300 KHz to 400 KHz in order to transfer completely like the previous 30 lines.
[0018]
[Problems to be solved by the invention]
However, the partial reading method in the conventional example as described above has the following problems.
[0019]
(1) Although all pixels are discarded in the unnecessary front and rear lines, the signal charges of all the pixels including the pixels on both sides that are not necessary must be read in the line from which the signal is read out. Accordingly, the number of horizontal pixels is determined by the limitation of the horizontal reading speed. At present, the horizontal readout speed is several tens of MHz, and therefore the upper limit is about 1000 pixels. In addition, an external memory is used as a buffer in order to compensate for the loss time of unnecessary charge reading.
[0020]
(2) Although the restriction (1) above relates to a video camera, for example, in a digital still camera or a PC (personal computer) camera, the speed restriction has a degree of freedom compared to a video camera, but a partial image. There is a need for higher speeds in uptake. Therefore, the reading time of the unnecessary pixel portion in the conventional example becomes an obstacle to speeding up the high-speed partial reading even in such an application.
[0021]
(3) Further, the conventional vertical / horizontal blanking constrained to the video rate is a wasteful time in a digital still camera having a use that requires reading an image at high speed. In addition, in a digital still camera that captures a still image, there is a need to shorten the time from when the shutter is pressed until the image is read out, and reading with an increased frame rate is also required as a photometric operation.
[0022]
The present invention was made to address the above problems, Provide an imaging device that enables high-speed partial readout of a high-pixel sensor, shortens readout time, and improves frame rate The purpose is that.
[0024]
[Means for Solving the Problems]
According to the present invention Imaging device Is configured as follows.
[0025]
(1) A plurality of pixels two-dimensionally arranged in the vertical direction and the horizontal direction, each having a photoelectric conversion element, a plurality of vertical shift registers that transfer signals from the plurality of pixels in the vertical direction, and the plurality of vertical A horizontal shift register for transferring a signal from the shift register in a horizontal direction, wherein the horizontal shift register includes a first area to which a signal of an effective pixel is transferred from the plurality of vertical shift registers, and a signal of the effective pixel An imaging device having a second area that is not transferred, During a period in which a horizontal charge transfer clock for outputting a signal transferred from the horizontal shift register to the second region is output, signals from the plurality of pixels of the plurality of vertical shift registers are vertically It overlaps with the period when the vertical charge transfer clock for transferring is output, The first area is sandwiched between the second areas and is within a period during which a signal of a predetermined row is transferred in the horizontal shift register, and there is no signal in the first area. First, the signal of the next row is sent to the horizontal shift register so that the signal of the effective pixel of the predetermined row and the signal of the next row are not mixed within the period in which the signal exists in the second region. I forwarded it.
[0026]
(2) A plurality of pixels two-dimensionally arranged in a vertical direction and a horizontal direction, each having a photoelectric conversion element, a plurality of vertical shift registers that transfer signals from the plurality of pixels in the vertical direction, and the plurality of vertical A horizontal shift register that horizontally transfers a signal from the shift register;
Said plural The vertical shift register Consists of a third region where signals are transferred from effective pixels and a fourth region where signals are transferred from pixels other than effective pixels There is a first area and a second area where the effective pixel signal is not transferred. And the first region is sandwiched between the second regions. An imaging device comprising:
During a period in which a horizontal charge transfer clock for outputting a signal transferred from the horizontal shift register to the fourth area is output, a pulse for discharging signal charges from the plurality of pixels is output. Overlaps with period,
A signal of the next frame is transferred to the vertical shift register within a period in which no signal exists in the first area and a signal exists in the second area.
[0072]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0073]
FIG. 1 is a diagram showing a configuration of an image sensor (CCD) according to the present invention. In the figure, reference numeral 1 denotes a PD (photodiode) which is a photoelectric conversion element, and 2 denotes a VCCD (vertical CCD) which is a plurality of vertical shift registers for transferring the signal charge of the PD1, and usually has a four-phase drive configuration. . And the effective area comprised by these PD1 and VCCD2 is the same as that of the sensor of a prior art example.
[0074]
HCCD (horizontal CCD) 3 is a horizontal shift register for transferring the image signal charges accumulated in the effective area for each line, and 4 is a voltage signal for the signal charge for each pixel transferred from the HCCD 3. These output amplifiers (output means) are not different from the conventional example.
[0075]
This sensor differs from the conventional example in that a buffer storage cell (BS cell) 5 that temporarily stores signal charges for one line from the VCCD 2 before being transferred to the HCCD 3, and the buffer storage cell 5 and the HCCD 3 The transfer gate (TG) 6 is provided.
[0076]
The HCCD 3 is configured at one end of the VCCD 2 and transfers the signal charge of the VCCD 2 as one row or n (positive integer) row of signal charges.
[0077]
2, FIG. 3, FIG. 6, and FIG. 7 are diagrams showing drive timings for explaining the partial readout operation of this sensor. 2 shows the operation in one field, FIG. 3 shows the timing during the high-speed vertical charge discarding operation, FIG. 6 shows the reading timing of the effective line section, and FIG. 7 shows the BS and TG in the effective line reading mode. The timing of each is shown.
[0078]
4, 5, and 8 are cross-sectional configurations from the last part of the corresponding VCCD 2 to the HCCD 3 through the BS cell and TG, and potential diagrams for explaining each operation of each part. 4 and 5 show a potential profile at the time of high-speed vertical charge discarding operation corresponding to FIG. 3, and FIG. 8 shows a potential profile at the time of reading of the effective line portion of FIG.
[0079]
FIG. 9 is a conceptual diagram for explaining a method of reducing unnecessary pixel discarding time at the time of reading the effective line portion. Here, partial reading of this sensor when used in a digital still camera will be described. Here, only the central 640 × 480 pixels are read out by a sensor of 1280 × 960 pixels.
[0080]
In the case of a digital camera, there is no restriction on the video signal format, and only capturing in the shortest time is required. First, signal charges are read from the PD to the VCCD, and the previous 120 lines are discarded as in the prior art (see Tvc in FIG. 2 and FIGS. 3 to 5). The shortest operation time of this operation depends on the maximum transfer rate of the vertical transfer unit as described in the description of the conventional example. The transfer of VCCD and HCCD is the same as in the conventional example.
[0081]
For BS and TG, either method (1) or (2) shown in FIG. 3 is used.
[0082]
In (1), BS is in phase with V1, and TG is in phase with V2 (TG may be in phase with BS).
[0083]
In (2), an appropriate DC bias is applied so that BS and TG have an intermediate potential. At this time, as shown in the figure, an appropriate potential difference is provided between BS and TG.
[0084]
At the end of the 120th line ejection, the signal charge of the 121st line is accumulated under the BS. The signal charge on the 122nd line is sent to the bottom of the V1 and V2 electrodes of the VCCD.
[0085]
Next, a description will be given of reading of necessary lines after completion of 120 lines (Tr in FIG. 2).
[0086]
After the 120-line high-speed V transfer is completed, a transfer pulse of 1280 stages or more is applied to the HCCD to throw away unnecessary charges in the HCCD (remaining charges generated at the time of high-speed discard) (Thc). After the operation is finished (the previous high-speed vertical charge discarding mode is set), the TG gate opens (that is, the TG gate electrode changes from Low to High), and at the same time, the BS electrode is changed from High to Low. Thus, the charge on the 121st line under the BS electrode passes under the TG electrode and is accumulated in the HCCD.
[0087]
When the charge transfer to the HCCD is completed, the TG gate is closed (that is, the TG gate electrode changes from High to Low), and the BS electrode is also returned to High (see Tt in FIG. 6 and FIG. 7). At this time, as shown in FIG. 7, it is desirable that the BS is slightly delayed with respect to TG.
[0088]
After the BS and TG operations are completed, the HCCD performs 320 stages of transfer at a clock frequency higher than that of normal reading (closer to the upper limit of the horizontal transfer efficiency that does not deteriorate the image) (even if it is driven at 30 MHz) The operation is completed in about 10 μS).
[0089]
At this time, since the reset gate is kept open, the transferred charge is immediately discharged to the reset drain. Therefore, the output level from the output amplifier fluctuates in synchronization with the horizontal transfer clock with the reset level as the center. Here, the reset gate is left open for the purpose of clearing high-speed charges and reducing power consumption.
[0090]
During this period, the signal charges on each line under the first and second electrodes of the VCCD are transferred to the lower first and second electrodes, respectively. This time requires several μS to several tens μS because the capacity of the vertical transfer electrode is large and the capacity is high. By this transfer, the signal charges on the 122nd line below the first and second electrodes in the final stage of the VCCD are transferred and stored under the BS electrode (Tc in FIG. 6).
[0091]
Normally, when the vertical transfer electrode is driven in this way, a large noise is added to the CCD output amplifier and the analog signal processing system outside the CCD. For this reason, such transfer is performed within a horizontal blanking period in normal video. In the solid-state imaging device according to the present embodiment, this can be performed simultaneously during an unnecessary charge reading period in which noise is not a problem. By making this possible, the time reading time for partial reading can be shortened. What makes this possible is the buffer storage line composed of the BS electrode and the TG electrode of this embodiment.
[0092]
Next, when the charge of 320 pixels in the previous horizontal stage is discarded, 640 pixels of the effective pixel at the center of the 121st line are read out at a normal reading timing (To in FIG. 6). Then, immediately after the last 640th line of the effective pixels is output, the TG is opened, the charges of all the pixels on the 122nd line are transferred to the lower HCCD, and the gate of the TG is closed again (Tt2 in FIG. 6). . These operations can be driven at a high speed because both the BS and TG electrodes have extremely low capacity, and it is sufficient to have several tens of ns.
[0093]
After the above operation is completed, the well under the BS gate is an empty well. Here, the signal charge for the 320th pixel of the 121st line and the 320th pixel of the previous stage of the 122th line are added to the 320th stage of the HCCD. However, since both are signal charges to be discarded, there is no problem in adding them at this point (see the conceptual diagram in FIG. 9).
[0094]
Here, in the case of the above-described conventional sensor, it takes more time than the transfer from the BS gate to the HCCD, but the transfer is directly performed from the last stage of the VCCD to the HCCD. Similarly, the subsequent-stage unnecessary pixel charges on the previous line to be swept away and the subsequent-stage unnecessary charges on the next line are added.
[0095]
In FIG. 9, A is 121 line unnecessary charge and 122 line unnecessary charge (thick hatched line), B is 122 line effective charge, and C is 122 line unnecessary charge. In the figure, shaded portions indicate unnecessary charges, net portions indicate effective charges, and blank portions indicate empty charges.
[0096]
Immediately after the above addition, 320 stages of charges are discharged at a speed higher than the normal transfer speed, and at the same time, the VCCD is transferred. By this operation, all signal charges on the 123rd line are transferred to the buffer storage memory. (Tc2 in FIG. 6).
[0097]
Although described immediately after the addition, the HCCD may be driven during the addition operation (transfer operation from the BS gate to the HCCD or transfer operation from the final stage of the VCCD to the HCCD). This is because there is no rule for addition because it is an unnecessary charge. In this case, depending on the size of the maximum charge storage capacity of the HCCD, it may be better to move the HCCD driving speed during the addition operation slower than the normal reading speed. This is to take measures against this because the charge may flow into the adjacent cell beyond the saturation capacity due to the addition. As a countermeasure for such a problem, a drain (H 2 drain) may be provided along the HCCD. In this case, however, the barrier between the HCCD and the H drain needs to be set to an appropriate height. Therefore, it is better to use a gate structure so that the height of the barrier can be adjusted. At this time, a voltage is applied to the gate so that the barrier height is appropriate depending on the driving speed of the HCCD. In addition, since the appropriate barrier value is different when reading the effective charge and when reading the added unnecessary charge, the voltage of the barrier gate is also changed during each drive.
[0098]
In the same manner, the central 240 lines (240 lines for one non-added field in all pixel frame reading, and 480 lines added in the front and back in field reading are 240 lines) are sequentially read out.
[0099]
By performing such an operation, the number of clocks for discarding unnecessary charges becomes half the number of clocks when all unnecessary pixels are sequentially discarded, and the time is also halved.
[0100]
When the charge readout of the lines including the effective pixels of the 240 lines is completed, the high-speed vertical charges for the remaining 120 lines are discharged and the readout of one field is completed. Thereafter, all pixel readout or field readout is repeated by the same readout method.
[0101]
As described above, by performing the above-described operation using the area sensor of this embodiment, a partial readout image can be obtained at extremely high speed. Also, video timing readout using a high pixel digital camera is possible.
[0102]
The charge storage capacity of the BS well needs to be larger than the transfer saturation of the VCCD. For example, if the charge storage capacity of the BS well is set to be not less than twice the transfer saturation of VCCD, signal charges can be added in the BS well.
[0103]
In the above operation, means for fixing the potential of TG to an appropriate potential as DC is used. In such a case, an appropriate voltage value is applied to the TG electrode, or an appropriate potential is created by ion implantation.
[0104]
In the present embodiment, the number of HCCD stages and the number of horizontal pixels in the image area are assumed to be the same. However, in reality, the number of HCCD stages is larger for transfer to the read amplifier unit. There is also an optical black region. However, although the description has been made here without clarifying the gist of the present invention, it goes without saying that the actual sensor design and drive timing design should also be considered.
[0105]
(Second embodiment)
Next, a second embodiment of the present invention will be described.
[0106]
The solid-state imaging device uses the configuration shown in FIG. 10, in which 10 is a PD (photodiode) for photoelectric conversion, and 11 is a VCCD for transferring signal charges of the PD 10, and normally has a 4-phase drive configuration. Reference numeral 12 denotes an HCCD (horizontal CCD) that transfers image signal charges accumulated in the effective area for each line. Reference numeral 13 denotes an output amplifier that uses the signal charges for each pixel transferred from the HCCD 12 as voltage signals.
[0107]
It is assumed that the total number of pixels, the effective imaging area, and the invalid imaging area of the solid-state imaging device of the present embodiment are the same as those in the first embodiment. Further, as a method for discharging the signal charge of the pixel, it is assumed that the image pickup device is a solid-state imaging device that can be swept away in the substrate direction.
[0108]
FIG. 15 shows the operation in one field, and shows the first part of the Nth field and the (N-1) th field. FIG. 16 illustrates the operation of over-reading the invalid imaging areas above and below the effective imaging area. The state of the vertical charge transfer element of the solid-state imaging element at the timings t10, t11, and t12 in FIG. Is shown. In the figure, reference numeral 200 denotes an effective imaging area, 201 denotes an upper invalid imaging area, and 202 denotes a lower invalid imaging area. t10 indicates a state immediately after the charge read pulse of the Nth field is applied. As shown in (1) of FIG. 16, the signal charge is read from the pixel to the vertical charge transfer element. From the first line to the 120th line, the charges read from the pixels remain in the (N-1) th field. During the Tvcc period, the same clock as the Tvca period of the first embodiment is used to sweep and transfer the first line to the 120th line at high speed. Next, unnecessary charges remaining in the horizontal charge transfer element are swept out during the Thc period.
[0109]
The Tr period is a period in which the readout operation from the 121st line to the 360th line is shown, and the signal charge in the effective imaging area is read from the output amplifier, and the invalid imaging areas on the right side and the left side of the effective imaging area are overwritten. Yes. Since the overreading method is almost the same as that of the first embodiment, only different portions will be described.
[0110]
FIG. 17 shows the vicinity of the horizontal blanking period between the (n−1) th line and the nth line in the Tr period. The Tn−1 period is a period for reading the signal charge in the effective imaging region of the n−1th line, and the invalid imaging region on the right side of the n−1th line remains in the horizontal charge transfer element even after the end of the Tn−1 period. To remain. However, in the first embodiment, as described with reference to FIG. 9, the charge in the invalid imaging area on the right side remaining in the horizontal charge transfer element overlaps with the signal charge in the effective imaging area on the nth line. All are transferred to the output amplifier side so that it does not become. The Thd period is a period in which signal charges are transferred from the vertical charge transfer element to the horizontal charge transfer element. At this time, the charge in the invalid imaging area on the right side of the (n-1) th line and the invalid imaging area on the left side of the nth line. Are added. The Tv4 period is the vertical charge transfer clock V4 applied to the transfer electrode in contact with the horizontal charge transfer element among the transfer electrodes of the vertical charge transfer element, and the horizontal charge transfer from the vertical charge transfer element only when the vertical charge transfer clock V4 is High. Charge is transferred to the element. The Tml period is a margin period from when the vertical charge transfer clock V4 becomes Low and transfer from the vertical charge transfer element is completed to when charge transfer into the horizontal charge transfer element is completely completed. . The Tnc period is a period in which the added charge in the invalid imaging area on the right side of the (n−1) th line and the charge in the invalid imaging area on the left side of the nth line are overwritten. This leads to a period for reading out signal charges in the effective imaging region of the nth line in the Tn period. By repeating this, overwriting of the invalid imaging region in the horizontal direction is performed.
[0111]
Here, in the conventional video solid-state imaging device, the vertical charge transfer clocks V1, V2, V3 and V4 and the pulse Vsub for discharging the signal charge of the pixel are in a state where the horizontal charge transfer clocks H1 and H2 are at a constant voltage. In general, in this embodiment, a part is added over the Tnc period. The Tsub period is a period in which a pulse Vsub for discharging the signal charge of the pixel is applied, and noise is generated in the signal output from the output amplifier, similarly to the vertical charge transfer clock. The Tnc period is a period that is not used as an image signal because the invalid imaging area in the horizontal direction is over-read, so that even if such an operation is performed, the readout time can be shortened without affecting the image signal. It becomes possible. The Tm2 period is a period from the end of the Tsub period to the start of the Tn period, and is a margin period provided so that the pulse Vsub for discharging the signal charge of the pixel does not affect the image signal.
[0112]
t11 indicates immediately after the end of the reading operation up to the 360th line. As shown in (2) of FIG. 16, the vertical charge transfer element of the solid-state imaging device has only the charge in the invalid imaging area on the upper side. Remaining. Further, it is indicated that all the charges in the upper invalid imaging area are transferred below the effective imaging area.
[0113]
t12 indicates a state immediately after the charge read pulse of the (N + 1) th field is applied, and as shown in (3) of FIG. 16, the signal charge is read from the pixel to the vertical charge transfer element. From the first line to the 120th line, the charges read from the pixels remain in the Nth field, but since the effective imaging area is only the signal charges that are not over-read, there is no problem in imaging. .
[0114]
By repeating such an operation, the effective imaging area can be read at high speed.
[0115]
The following is a supplementary explanation of the present invention.
[0116]
(1) In the present invention, the VCCD is a four-phase drive CCD and the HCCD is a two-phase drive. However, it goes without saying that the present invention can be applied to other types of CCDs. It can also be applied to a frame transfer type CCD or the like.
[0117]
(2) As an application example of the present invention, a sensor in which only a gate is provided between VCCD and HCCD can be considered. In this case, the V3 and V4 gates at the last stage of the VCCD function as BS cells. In FIG. 1, since V4 is the last, this is the case. For example, when the last stage is configured as V2, the V1 and V2 gates serve as BS cells.
[0118]
The same idea can be applied even if the VCCD is three-phase driven. In this case as well, the area under the electrode when forming a well capable of accumulating the transfer charge of the final stage of the VCCD in contact with the gate between the VCCD and the HCCD. Make. However, in this method, it is necessary to move the transfer electrode of the VCCD to ensure charge transfer. For this reason, the charge transfer time to the HCCD is somewhat longer than in the above-described embodiment, but the readout time can be considerably shortened compared to the conventional example.
[0119]
(3) There is an image sensor having a plurality of horizontal registers in order to increase the speed of the high-pixel solid-state image pickup device. The structure and driving method of the present invention can also be adopted for such an image sensor.
[0120]
(4) In the embodiment of the present invention, the ratio between the unnecessary pixel and the effective pixel is set to 1/4 (1/2 × 1/2). However, the ratio is not limited to this ratio. Further, it is not always necessary to center the effective pixel portion.
[0121]
In short, it is important to shorten the time by overlapping unnecessary pixel readout times. However, the effect of shortening the time depends on the location and size of reading.
[0122]
(5) If the reading location is changed or the effective pixel ratio is set to 1/4 (1/2 × 1/2) or more, it may not be possible to drive the VCCD into the unnecessary charge removal time. In this case, means for waiting for the effective pixel reading until the end of the transfer of the VCCD is used. Alternatively, it is possible to correct or blank a noise-added portion later with the VCCD being transferred during the effective pixel readout.
[0123]
(6) For BS and TG electrodes, the effect of the present invention increases as a material having higher conductivity such as an aluminum electrode is used.
[0124]
(7) The present invention can be applied not only to a solid-state imaging device using a charge transfer element but also to a MOS solid-state imaging device using a shift register and an XY address solid-state imaging device.
[0125]
(8) In the present invention, the effective imaging area may be used not only as image information but also as photometric information. In this case, since the effective imaging area is further reduced, the frame rate is further increased.
[0126]
(9) In the present invention, it was used in the Tvcc period between t11 and the readout pulse of the N + 1 field so that all charges in the invalid imaging area on the upper side were transferred below the effective imaging area. A predetermined number of line sweeps may be performed using the same clock as the sweep clock or the vertical charge transfer clock.
[0127]
(10) In the present invention, as a margin for charge overflow due to the superposition of signal charges between t11 and the N + 1 field read pulse, a predetermined number of sweep clocks or vertical charge transfer clocks used in the Tvcc period are used. Line sweeping may be performed.
[0128]
(11) In the horizontal charge transfer element of the present invention, the charge in the invalid imaging area on the right side of the (n-1) th line is to the left of the charge in the effective imaging area of the nth line to be transferred next. A predetermined number of charge sweeps by a horizontal charge transfer clock may be performed between Tn-1 and Thd so as to be transferred.
[0129]
(12) In the horizontal charge transfer device of the present invention, the charge in the invalid imaging area on the right side of the (n-1) th line and the charge in the invalid imaging area on the left side of the nth line to be transferred next. As a margin for the overflow of charges due to the superposition of a plurality of charges, a predetermined number of charges may be swept out by a horizontal charge transfer clock between Tn-1 and Thd.
[0130]
In the first and second embodiments, the invalidation of the present invention corresponds to the horizontal shift register that shifts the invalid charges of the previous row and the next row transferred from the buffer storage element by adding them together and discarding them. are doing. As a result, high-speed reading is possible.
[0132]
【The invention's effect】
According to the present invention, Since high-speed partial reading of a high pixel sensor becomes possible, it is possible to provide an imaging device that realizes a reduction in reading time and an improvement in frame rate.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an image sensor according to the present invention.
FIG. 2 is a drive timing chart of the CCD of the first embodiment.
FIG. 3 is a drive timing chart of the CCD of the first embodiment.
FIG. 4 is a diagram showing a drive potential feel of the CCD of the first embodiment.
FIG. 5 is a diagram showing a drive potential feel of the CCD of the first embodiment.
FIG. 6 is a drive timing chart of the CCD of the first embodiment.
FIG. 7 is a drive timing chart of the CCD of the first embodiment.
FIG. 8 is a diagram showing the drive potential feel of the CCD of the first embodiment.
FIG. 9 is an explanatory diagram showing a case where reading time is shortened.
FIG. 10 is a configuration diagram showing a conventional example.
FIG. 11 is a diagram showing a configuration of an output unit of a CCD
FIG. 12 is an explanatory diagram showing the operation of the output unit of the CCD.
FIG. 13 is a timing chart showing the operation of the CCD.
FIG. 14 is a timing chart for driving a conventional CCD.
FIG. 15 is a drive timing chart of the CCD of the second embodiment.
FIG. 16 is a diagram showing a reduction in readout time.
FIG. 17 is a drive timing chart of the CCD of the second embodiment.
[Explanation of symbols]
1 PD (photoelectric conversion element)
2 VCCD (vertical shift register)
3 HCCD (horizontal shift register)
4 Output amplifier (output means)
5 Buffer storage cells
6 Transfer gate
200 Effective imaging area
201 Invalid imaging area on the upper side
202 Invalid imaging area on the lower side

Claims (2)

A plurality of pixels two-dimensionally arranged in a vertical direction and a horizontal direction, each having a photoelectric conversion element, a plurality of vertical shift registers for transferring signals from the plurality of pixels in the vertical direction, and the plurality of vertical shift registers And a horizontal shift register for transferring the signal in the horizontal direction,
The horizontal shift register is an imaging device having a first area to which an effective pixel signal is transferred from the plurality of vertical shift registers, and a second area to which an effective pixel signal is not transferred.
During a period in which a horizontal charge transfer clock for outputting a signal transferred from the horizontal shift register to the second region is output, signals from the plurality of pixels of the plurality of vertical shift registers are vertically It overlaps with the period when the vertical charge transfer clock for transferring is output,
The first area is sandwiched between the second areas and is within a period during which a signal of a predetermined row is transferred in the horizontal shift register, and there is no signal in the first area. First, the signal of the next row is sent to the horizontal shift register so that the signal of the effective pixel of the predetermined row and the signal of the next row are not mixed within the period in which the signal exists in the second region. An image pickup apparatus for transferring. A plurality of pixels two-dimensionally arranged in a vertical direction and a horizontal direction, each having a photoelectric conversion element, a plurality of vertical shift registers for transferring signals from the plurality of pixels in the vertical direction, and the plurality of vertical shift registers And a horizontal shift register for transferring the signal in the horizontal direction,
The plurality of vertical shift registers include a first area composed of a third area where a signal is transferred from an effective pixel, a fourth area where a signal is transferred from a pixel other than the effective pixel, and a signal of the effective pixel there have a second region that is not transferred, and the first region is an imaging apparatus which is sandwiched between the second region,
During a period in which a horizontal charge transfer clock for outputting a signal transferred from the horizontal shift register to the fourth area is output, a pulse for discharging signal charges from the plurality of pixels is output. Overlaps with period,
An imaging apparatus, wherein a signal of the next frame is transferred to the vertical shift register within a period in which no signal exists in the first area and a signal exists in the second area.

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