JP2009225478A - Method of driving solid-state imaging device, solid-state imaging apparatus, and camera system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose driving timing in the vertical transfer driving mode of a solid-state imaging device which has versatility and improves transfer efficiency in a readout system of three or more fields. <P>SOLUTION: A vertical CCD 13 is driven so as to turn off a backward transfer channel of a charge packet approximately simultaneously with turning on a forward transfer channel of a charge packet in the transfer direction during vertical transfer, so that vertical transfer is performed in such a state that an overlap period of a vertical transfer clock is made long. The transfer efficiency is improved by extending the overlap period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a driving method of a solid-state imaging device (image sensor) that images a subject and outputs an image signal corresponding to the subject image, and a solid-state imaging device and an imaging device module including the solid-state imaging device and a driving device. The present invention relates to a camera system. For example, the present invention relates to a transfer driving technique of a vertical register (vertical CCD) in a charge transfer type solid-state imaging device suitable for use in an electronic still camera or the like.

  In recent years, electronic still cameras (digital still cameras) have been rapidly spreading. Since this electronic still camera requires high-resolution still image shooting, a mechanism for independently outputting the signals of all the pixels without mixing them is adopted. For example, when a CCD image pickup device is used as the image pickup device, all pixels are read out at the same time, and signal charges of the respective pixels are transferred independently without being mixed in a vertical CCD (vertical register), or A so-called frame readout system (see FIGS. 16 to 19) is used in which the mechanical charge is used and the signal charges of the odd and even lines are alternately read out to the vertical CCD for each field and the signal charges of each pixel are transferred independently. ing.

  Further, as an example of a method for increasing the data rate of the output signal of the image sensor during still image shooting, a line thinning readout method (see FIGS. 20 to 23) has been proposed. In this line thinning readout method, empty packets that do not include signal charges existing behind the packet including signal charges Qs are mixed in the horizontal register to eliminate the no-signal period. For example, it is necessary to perform vertical transfer for 2 lines). Here, when the horizontal blanking period for performing vertical transfer is the same in the two operation modes (frame reading and thinning reading) (see FIGS. 18 and 22), the overlap period of the vertical transfer clock is set to “x”. In the case of the line thinning readout method, as shown in FIG. 22, since vertical transfer for two lines is performed, the overlap period of the vertical transfer clock becomes “1 / 2x” and the transfer efficiency is lowered and the frame is reduced. It is necessary to perform vertical transfer driving at a higher speed than in the reading method.

  However, when such high-speed driving is performed, a position far from the input terminal of the vertical transfer clock (for example, the opposite side at the time of one-side input shown in FIG. 24B / the device at the time of both-side input shown in FIG. 24C) In the central part), a decrease in drive voltage or drive pulse propagation delay due to electrode resistance occurs, and the actual drive waveform becomes dull as shown in FIG. In this case, there arises a problem that the transfer efficiency of the vertical CCD deteriorates or the amount of charge handled decreases. In FIG. 24B and FIG. 24C, the driver 42 is omitted.

  Therefore, the present applicant has proposed a technique for solving this problem in, for example, Patent Document 1 (see FIGS. 25 and 26 showing an outline of this technique). According to the technique described in Patent Document 1, as shown in FIG. 25, during vertical transfer in four-phase drive, vertical transfer is performed by a combination of pairs of vertical transfer clocks having opposite phases to each other. Increase the lap period. Thus, even when the line thinning readout method is used, vertical transfer is performed in a state where a long overlap period (the same “x” as in FIG. 18) as in the case of the two-field / frame readout method is taken. Thus, the transfer efficiency of the vertical CCD can be improved.

Japanese Patent Laid-Open No. 10-013742

  By the way, recently, the cell size has been reduced for higher resolution (multiple pixels) or miniaturization, and the frame readout method is also different from the conventional two-field readout method in which the reading is divided into two fields. In addition, a frame reading method based on a three-field reading method (see FIGS. 6 and 7 described later) and a four-field reading method (see FIGS. 10 and 11 described later) has been put into practical use.

  However, it has been found that when the frame reading method of three or more fields is used, the overlap period is reduced and the vertical transfer efficiency is deteriorated not only in the line thinning-out reading operation but also in the frame reading operation. For example, when the horizontal blanking period for performing vertical transfer is the same as that in the two-field read system, the overlap period of the vertical transfer clock is different from that of “x” in the two-field read system (FIG. 18). In the three-field reading system as shown in FIG. 28, “2 / 3x” is obtained. Although not shown, in the four-field readout method, “1 / 4x” is obtained. For this reason, a propagation delay occurs in the vertical transfer clock, and the waveform becomes dull as shown in FIG. 24A at a position far from the input terminal of the clock, so that the transfer efficiency of the vertical register deteriorates and the handling charge amount decreases. Problems occur. The same problem arises with a reading method of 5 fields or more.

  Here, in the case of the readout method with three or more fields, the amount of charge handled by the vertical register is relatively small because the number of on-transfer channels of the vertical register is larger than that in the two-field readout method. The problem is not acceptable for degradation.

  As one method for solving the problem of transfer efficiency degradation, the vertical CCD transfer speed (vertical transfer clock overlap period) is set to a two-field readout system while maintaining the frame rate by increasing the horizontal drive frequency. The same method can be considered.

  However, in order to increase the horizontal drive frequency, the transfer efficiency of the horizontal CCD is degraded. In addition, as the frequency increases, new problems such as an increase in power consumption of the horizontal CCD, an increase in the cost of components used, and a deterioration in S / N occur. Therefore, it is not a preferable method to increase the horizontal driving frequency.

  Further, as a method for solving such a problem, it is conceivable to use the technique described in Patent Document 1. However, although the technique described in Patent Document 1 is an effective technique when applied to the line thinning readout method in the object of the conventional two-field readout method, the three-field readout method or more (for example, 4 or 5 or more) As a technique for solving the above-mentioned problem in the reading system (and more), there is a basic restriction that vertical transfer is performed by a combination of mutually opposite-phase (complementary) vertical transfer clock pairs. The method is not necessarily applicable to driving of any number of fields and phases, and is not a versatile technique for improving the problem of deterioration of vertical transfer efficiency in various readout methods.

  The present invention has been made in view of the above circumstances, and can improve the problem of deterioration of transfer efficiency when performing vertical transfer driving in various field numbers and reading methods, and is more versatile. It is an object of the present invention to provide an imaging element driving method and a camera system such as a solid-state imaging device and an imaging device module.

  The solid-state imaging device driving method according to the present invention is a solid-state imaging device driving method that vertically transfers a signal charge obtained by photoelectric conversion, and is a P (P is a positive integer of 5 or more) phase vertical transfer pulse. Vertical transfer direction for each unit of charge packet for transferring signal charge, formed by a sequence of P-2 transfer channels successively turned on by a vertical transfer drive pulse applied to a vertical transfer electrode based on On, the transfer channel for one packet ahead of the charge packet is turned on, and the transfer channel for one packet at the end of the charge packet is turned off to continuously turn on in the vertical transfer direction. The vertical transfer is performed in a state where the ON period overlaps the P-2 vertical transfer pulses. Preferably, the vertical transfer drive pulse for turning on one transfer channel in front of the charge packet and the vertical transfer drive pulse for turning off one transfer channel at the end of the charge packet are turned on The permissible range of the off switching timing is set such that the fluctuation amount of the charge amount handled in the charge packet is less than the accumulated charge amount of one transfer channel.

  In addition, it is also possible to extract the drive apparatus which implements the drive method of the solid-state image sensor which concerns on the said invention as said invention. This drive device is an array of P-2 transfer channels that are successively turned on by a vertical transfer drive pulse applied to a vertical transfer electrode based on a vertical transfer pulse of P (P is a positive integer of 5 or more) phase. For each unit of formed charge packet for transferring a signal charge, one transfer channel in front of the charge packet in the vertical transfer direction is turned on and one charge packet at the end of the charge packet is turned on. The vertical transfer pulse is generated so that the transfer channel is turned off, and the vertical transfer is performed in a state where the ON period overlaps the P-2 vertical transfer pulses that are continuously turned on in the vertical transfer direction. Also, a vertical transfer drive pulse for turning on one transfer channel ahead of the charge packet and one at the end of the charge packet. The allowable shift range of the ON / OFF switching timing of the vertical transfer drive pulse for turning off the transfer channel is set so that the fluctuation amount of the charge amount handled in the charge packet is less than the accumulated charge amount of one transfer channel. A timing signal generation unit is provided.

  The solid-state imaging device according to the present invention includes a driving device that implements the driving method of the solid-state imaging device according to the present invention, and also includes a solid-state imaging device. In other words, the driving device only needs to have a function of generating the vertical transfer clock having the timing as described above, and may be a so-called timing generator. On the other hand, the solid-state imaging device according to the present invention is provided with a solid-state imaging device in addition to the function of the driving device. In addition to the configuration of the solid-state imaging device according to the present invention, the camera system according to the present invention also includes an imaging lens that forms an optical image of a subject on the imaging surface of the solid-state imaging device, or a signal processing unit. Is.

  In the above configuration according to the present invention, during vertical transfer, the vertical transfer unit is driven so as to turn off the forward transfer channel of the charge packet in the transfer direction at the same time as turning on the rear transfer channel of the charge packet. Vertical transfer is performed in a state where the overlap period of the transfer clock is long.

  Such drive timing can be applied to a four-phase drive method, but in particular, it is not always applicable with the technique described in Patent Document 1 in the four-phase drive method, and more multiphase (for example, 6-phase / 8-phase). It is suitable for application to the driving of a vertical transfer unit of multiple phases (or more phases).

  According to the present invention, vertical transfer driving is performed for each unit of charge packet during vertical transfer at a driving timing of “turning off the backward transfer channel almost simultaneously with turning on the forward transfer channel in the vertical transfer direction”. Thus, vertical transfer can be performed in a state where the overlap period of the vertical transfer clock is long, and the transfer efficiency of the vertical transfer unit can be improved.

  In addition, the application of such drive timing can be easily applied to normal drive timing that does not, and the application range is wide and a versatile drive method could be realized. .

  In addition, when applied to line thinning operation, high-speed read operation can be realized regardless of the method of increasing the horizontal drive frequency, which causes other problems such as deterioration of transfer efficiency of the horizontal register and increase of power consumption of the horizontal register. In addition, a high-speed image pickup signal can be obtained and the transfer efficiency can be improved.

1 is a schematic configuration diagram illustrating an imaging apparatus that is an embodiment of a camera system according to the present invention. It is the schematic of the solid-state imaging device comprised from CCD solid-state image sensor and one Embodiment of a drive control part. It is a plane pattern figure which shows an example of the specific structure of an imaging area. It is a figure which shows the X-X 'arrow cross section of FIG. It is the wiring pattern figure of the transfer electrode in vertical CCD. It is a figure explaining the outline of 3 field read-out system / frame read-out system (this embodiment). It is a timing chart (vertical rate; this embodiment) of a vertical transfer drive pulse of a three-field read system. It is a timing chart (horizontal rate; this embodiment) of a vertical transfer drive pulse of a three-field read system. It is a figure explaining the charge transfer state of 3 field read system / frame read system (this embodiment). It is a figure explaining the outline of 4 field read system / frame read system (this embodiment). It is a timing chart (vertical rate; this embodiment) of a vertical transfer drive pulse of a four-field read system. It is a timing chart (horizontal rate; this embodiment) of a vertical transfer drive pulse of a four-field read system. It is a figure explaining the charge transfer state of 4 field read system / frame read system (this embodiment). It is a figure explaining the amount of charges handled by the vertical CCD in relation to the drive pulse delay. It is a figure explaining the operation | movement of the 2 field read system and the thinning-out read system of 2/8 line. It is a figure explaining the outline of a 2 field read system / frame read system. It is a timing chart (vertical rate) of a vertical transfer drive pulse of a two-field read system. It is a timing chart (horizontal rate; basic of conventional example) of a vertical transfer drive pulse of a two-field read system. It is a figure explaining the charge transfer state of 2 field read system / frame read system (basic of a prior art example). It is a figure explaining the outline of 2 field reading system / thinning-out reading system (2/8 line). 5 is a timing chart (vertical rate) of vertical transfer drive pulses in a two-field read method / decimation read method (2/8 line). It is a timing chart (horizontal rate; basic example of conventional example) of vertical transfer drive pulses in a two-field readout method / decimation readout method (2/8 line). It is a figure explaining the charge transfer state (basic of a prior art example) of 2 field read system / thinning-out read system (2/8 line). It is a figure explaining the delay of a vertical transfer drive pulse. It is a timing chart (horizontal rate; patent document 1) of the vertical transfer drive pulse of 2 field read system / thinning read system (2/8 line). It is a figure explaining the charge transfer state (patent document 1) of 2 field read system / thinning-out read system (2/8 line). It is a timing chart (horizontal rate; conventional example) of a vertical transfer drive pulse of a three-field read system. It is a figure explaining the charge transfer state of 3 field read system / frame read system (conventional example).

<Configuration of digital still camera>
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram illustrating an imaging apparatus which is an embodiment of a camera system according to the present invention. The imaging device (camera system) shown in FIG. 1 is obtained by the imaging device module 3 having the CCD solid-state imaging device 10, the imaging lens 50, and the drive control unit 96 that drives the CCD solid-state imaging device 10, and the imaging device module 3. The digital still camera 1 includes a main body unit 4 that generates a video signal based on a captured image signal and outputs it to a monitor or stores an image in a predetermined storage medium.

  The drive control unit 96 in the imaging device module 3 receives a timing signal generation unit 40 that generates various pulse signals for driving the CCD solid-state imaging device 10 and a pulse signal from the timing signal generation unit 40. A driver (drive unit) 42 that converts the drive pulse to drive the CCD solid-state image sensor 10 and a drive power source 46 that supplies power to the CCD solid-state image sensor 10 and the driver 42 are provided. The solid-state imaging device 2 is configured by the CCD solid-state imaging device 10 and the drive control unit 96 in the imaging device module 3. The solid-state imaging device 2 is provided as a device in which the CCD solid-state imaging device 10 and the drive control unit 96 are arranged on one circuit board or formed on one semiconductor substrate. Is good.

  The processing system of the digital still camera 1 is roughly composed of an optical system 5, a signal processing system 6, a recording system 7, a display system 8, and a control system 9. Needless to say, the imaging device module 3 and the main unit 4 are accommodated in an exterior case (not shown), and an actual product (finished product) is finished.

  The optical system 5 includes a shutter 52, a lens 54 for condensing a light image of a subject, an imaging lens 50 having a diaphragm 56 for adjusting the light amount of the light image, and photoelectrically converting the collected light image into an electric signal. It comprises a CCD solid-state imaging device 10 for conversion. Light L from the subject Z passes through the shutter 52 and the lens 54, is adjusted by the diaphragm 56, and enters the CCD solid-state imaging device 10 with an appropriate brightness. At this time, the lens 54 adjusts the focal position so that an image composed of the light L from the subject Z is formed on the CCD solid-state imaging device 10.

  The signal processing system 6 includes an amplification amplifier that amplifies an analog imaging signal from the CCD solid-state imaging device 10, a CDS (Correlated Double Sampling) circuit that reduces noise by sampling the amplified imaging signal, and the like. A preamplifier unit 62, an analog signal output from the preamplifier unit 62, an A / D (Analog / Digital) converter unit 64 that converts the analog signal into a digital signal, and a predetermined image processing on the digital signal input from the A / D converter unit 64. The image processing unit 66 includes a DSP (Digital Signal Processor) to be applied.

  The recording system 7 encodes the image signal processed by the image processing unit 66 and the memory (recording medium) 72 such as a flash memory for storing the image signal, records the encoded image signal in the memory 72, and reads and decodes the image signal. 66 is provided with a CODEC (Compression / Decompression) 74 supplied to 66.

  The display system 8 is a D / A (Digital / Analog) conversion circuit 82 for converting the image signal processed by the image processing unit 66 into an analog, and a liquid crystal (functioning as a finder) by displaying an image corresponding to the input video signal. A video monitor 84 such as an LCD (Liquid Crystal Display) and the like, and a video encoder 86 that encodes an analog image signal into a video signal of a format suitable for the video monitor 84 in the subsequent stage.

  First, the control system 9 controls a drive (drive device) (not shown) to read a control program stored in a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and from the read control program or a user. A central control unit 92 including a central processing unit (CPU) that controls the entire digital still camera 1 based on the above command is provided.

  The control system 9 also includes an exposure controller 94 that controls the shutter 52 and the diaphragm 56 so that the brightness of the image sent to the image processing unit 66 is kept at an appropriate level, from the CCD solid-state imaging device 10 to the image processing unit 66. A drive control unit 96 having a timing signal generation unit (timing generator; TG) 40 for controlling the operation timing of each functional unit, and an operation unit 98 for a user to input shutter timing and other commands. The central control unit 92 controls the image processing unit 66, the CODEC 74, the memory 72, the exposure controller 94, and the timing signal generation unit 40 connected to the bus 99 of the digital still camera 1.

  The digital still camera 1 includes automatic control devices such as auto focus (AF), auto white balance (AWB), and automatic exposure (AE). These controls are processed using an output signal obtained from the CCD solid-state imaging device 10. For example, the exposure controller 94 has its control value set by the central control unit 92 so that the brightness of the image sent to the image processing unit 66 is kept at an appropriate level, and controls the diaphragm 56 according to the control value. Specifically, the central control unit 92 acquires an appropriate number of luminance value samples from the image held in the image processing unit 66, and the average value falls within a predetermined appropriate luminance range. Thus, the control value of the diaphragm 56 is set.

  The timing signal generation unit 40, which is a characteristic part in the digital still camera 1 of the present embodiment, is controlled by the central control unit 92, and the CCD solid-state imaging device 10, preamplifier unit 62, A / D conversion unit 64, and image processing unit 66. Timing pulses required for the operation are generated and supplied to each unit. The operation unit 98 is operated when the user operates the digital still camera 1.

  In the illustrated example, the preamplifier unit 62 and the A / D conversion unit 64 of the signal processing system 6 are built in the imaging device module 3, but the configuration is not limited to such a configuration, and the preamplifier unit 62 and the A / D conversion unit 64 are included. It is also possible to adopt a configuration in which the main body unit 4 is provided. A configuration in which the D / A conversion unit is provided in the image processing unit 66 can also be adopted.

  Further, although the timing signal generation unit 40 is built in the imaging device module 3, the configuration is not limited to such a configuration, and a configuration in which the timing signal generation unit 40 is provided in the main unit 4 can also be adopted. In addition, the timing signal generation unit 40 and the driver 42 are separate components, but the configuration is not limited to this, and the timing signal generation unit 40 and the driver 42 may be integrated (timing generator with built-in driver). By doing so, a more compact (small) digital still camera 1 can be configured.

  Further, the timing signal generator 40 and the driver 42 may each be configured by a circuit with individual discrete members, but are provided as an IC (Integrated Circuit) formed on a single semiconductor substrate. Is good. By doing so, not only can it be made compact, but the handling of the members becomes easy, and both can be realized at low cost. In addition, the digital still camera 1 can be easily manufactured. Further, the timing signal generator 40 and the driver 42 which are strongly related to the CCD solid-state image sensor 10 to be used are integrated on the same substrate as the CCD solid-state image sensor 10 or integrated in the image pickup device module 3. If they are integrated with each other, the handling and management of the members are simplified. In addition, since these are integrated as a module, the digital still camera 1 (completed product) can be easily manufactured. Note that the imaging device module 3 may be configured only from the optical system 5.

  The digital still camera 1 is specifically applied as a camera that can capture a color image during a still image capturing operation using a frame readout method. As a characteristic part of the digital still camera 1 of the present embodiment, the frame readout method is not limited to the general two-field readout method by combining with the CCD solid-state imaging device 10, and is not limited to the general two-field readout method. It is configured to be able to apply a reading method with various fields such as fields and more. In addition to the still image capturing mode, a moving image capturing mode is also prepared at a frame rate close to 30 frames / second (for example, 10 frames / second or more) using thinning-out reading.

<Outline of CCD solid-state imaging device and peripheral part>
FIG. 2 is a schematic diagram of the solid-state image pickup device 2 configured by the CCD solid-state image pickup device 10 and an embodiment of the drive control unit 96 that drives the CCD solid-state image pickup device 10. In the present embodiment, a case where the interline transfer (IT) type CCD solid-state imaging device 10 is driven in six phases or eight phases will be described as an example.

  In FIG. 2, the drain voltage VDD and the reset drain voltage VRD are applied to the CCD solid-state imaging device 10 from the drive power supply 46, and a predetermined voltage is also supplied to the driver 42.

  The CCD solid-state imaging device 10 constituting the solid-state imaging device 2 includes a sensor unit (photosensitive unit; photocell) 11 including a photodiode as an example of a light receiving element corresponding to a pixel (unit cell) on a semiconductor substrate 21. Are arranged in a two-dimensional matrix in the vertical (column) direction and the horizontal (row) direction. These sensor units 11 convert incident light incident from the light receiving surface into signal charges having a charge amount corresponding to the amount of light, and accumulate the signal charges.

  The CCD solid-state imaging device 10 has a plurality of vertical transfer electrodes 24 (24-1 per unit cell in this example) corresponding to 6-phase or 8-phase drive for each vertical row of the sensor unit 11. To 24-6 or 24-1 to 24-8) are arranged. The vertical CCD (V register unit, vertical transfer unit) 13 is arranged.

  The transfer direction of the vertical CCD 13 is the vertical direction in the figure, the vertical CCD 13 is provided in this direction, and a plurality of vertical transfer electrodes 24 are arranged in a direction (horizontal direction) orthogonal to this direction. Further, a read gate (ROG) 12 is interposed between the vertical CCD 13 and each sensor unit 11. A channel stop CS is provided at the boundary between the unit cells. An imaging area 14 is configured by a plurality of vertical CCDs 13 that are provided for each vertical row of the sensor units 11 and vertically transfer signal charges read from the sensor units 11 by the read gate unit 12.

  The signal charges accumulated in the sensor unit 11 are read out to the vertical CCD 13 by applying a drive pulse corresponding to the readout pulse XSG to the readout gate unit 12. The vertical CCD 13 is driven to transfer by drive pulses φV1 to φV6 (φV8) based on 6-phase (8-phase) vertical transfer clocks V1 to V6 (V8), and the read signal charges are made a part of the horizontal blanking period. Then, the portions corresponding to one scanning line (one line) are sequentially transferred in the vertical direction. This vertical transfer for each line is called a line shift.

  Further, the CCD solid-state imaging device 10 includes a horizontal CCD 15 (H register portion, extending in the horizontal direction in the figure adjacent to each transfer destination side end of the plurality of vertical CCDs 13, that is, adjacent to the vertical CCD 13 in the last row. Horizontal transfer unit) 15 is provided for one line. The horizontal CCD 15 is driven to transfer by drive pulses φH1 and φH2 based on, for example, two-phase horizontal transfer clocks H1 and H2, and the signal charges for one line transferred from the plurality of vertical CCDs 13 are transferred after the horizontal blanking period. The images are sequentially transferred in the horizontal direction during the horizontal scanning period. For this reason, a plurality (two) of horizontal transfer electrodes 29 (29-1, 29-2) corresponding to the two-phase driving are provided.

  At the end of the transfer destination of the horizontal CCD 15, for example, a charge-voltage converter 16 having a floating diffusion amplifier (FDA) configuration is provided. The charge-voltage converter 16 sequentially converts the signal charges transferred horizontally by the horizontal CCD 15 into voltage signals and outputs the voltage signals. This voltage signal is derived as a CCD output (VOUT) corresponding to the amount of incident light from the subject. The interline transfer type CCD solid-state imaging device 10 is configured as described above.

  Further, the solid-state imaging device 2 generates various pulse signals (binary of “L” level and “H” level) for driving the CCD solid-state imaging device 10 as a characteristic part of the solid-state imaging device 2 of the present embodiment. And a driver 42 that supplies various pulses supplied from the timing signal generator 40 to a predetermined level of drive pulses and supplies them to the CCD solid-state imaging device 10. For example, the timing signal generation unit 40 reads out the readout pulse XSG for reading out the signal charge accumulated in the sensor unit 11 of the CCD solid-state imaging device 10 based on the horizontal synchronization signal (HD) and the vertical synchronization signal (VD). Vertical transfer clocks V1 to Vn (n indicates the number of phases at the time of driving; for example, V6 at the time of six-phase driving, V8 at the time of eight-phase driving) for transferring and driving the signal charge in the vertical direction and passing to the horizontal CCD 15 from the vertical CCD 13 Horizontal transfer clocks H1 and H2, a reset pulse RG, and the like for transferring and driving the transferred signal charges in the horizontal direction and passing them to the charge-voltage converter 16 are generated and supplied to the driver 42.

  The driver 42 converts various clock pulses supplied from the timing signal generation unit 40 into voltage signals (drive pulses) of a predetermined level, or converts them into other signals and supplies them to the CCD solid-state imaging device 10. For example, the n-phase vertical transfer clocks V 1 to V 6 (V 8) generated from the timing signal generation unit 40 are converted into drive pulses φV 1 to φV 6 (φV 8) through the driver 42, and corresponding to each other in the CCD solid-state imaging device 10. It is applied to predetermined vertical transfer electrodes (24-1 to 24-6 or 24-1 to 24-8). Similarly, the two-phase horizontal transfer clocks H1 and H2 are converted into drive pulses φH1 and φH2 via the driver 42, and corresponding predetermined horizontal transfer electrodes (29-1 and 29-2) in the CCD solid-state imaging device 10 are used. To be applied.

  Here, the driver 42 superimposes the read pulse XSG on V1, V3, V5 (, V7) of the six-phase or eight-phase vertical transfer clocks V1 to V6 (V8), thereby setting the ternary level. The obtained vertical drive pulses φV1, φV3, φV5 (, φV7) are supplied to the CCD solid-state imaging device 10. That is, the vertical drive pulses φV1, φV3, φV5 (, φV7) are used not only for the original vertical transfer operation but also for reading the signal charges (see FIGS. 7 and 11 described later).

  An outline of a series of operations of the CCD solid-state imaging device 10 having such a configuration is as follows. First, the timing signal generation unit 40 generates various pulse signals such as transfer clocks V1 to V6 (V8) for vertical transfer and a read pulse XSG. These pulse signals are converted into drive pulses of a predetermined voltage level by the driver 42 and then input to predetermined terminals of the CCD solid-state imaging device 10.

  The signal charges accumulated in each of the sensor units 11 are such that the readout pulse XSG emitted from the timing signal generation unit 40 is applied to the transfer channel terminal electrode of the readout gate unit 12, and the potential below the transfer channel terminal electrode is deepened. Thus, the data is read out to the vertical CCD 13 through the readout gate section 12. Then, the vertical CCD 13 is driven on the basis of the six-phase (eight-phase) vertical drive pulses φV1 to φV6 (φV8), and sequentially transferred to the horizontal CCD15.

  The horizontal CCD 15 is sent to one line vertically transferred from each of the plurality of vertical CCDs 13 based on the two-phase horizontal drive pulses φH1 and φH2 emitted from the timing signal generator 40 and converted to a predetermined voltage level by the driver 42. Corresponding signal charges are sequentially horizontally transferred to the charge-voltage converter 16 side.

  The charge-voltage converter 16 accumulates signal charges sequentially injected from the horizontal CCD 15 in a floating diffusion (not shown), converts the accumulated signal charges into a signal voltage, for example, via an output circuit having a source follower configuration (not shown). The image signal (CCD output signal) VOUT is output under the control of the reset pulse RG generated from the timing signal generator 40.

  That is, in the CCD solid-state imaging device 10, the signal charges detected in the imaging area 14 in which the sensor units 11 are arranged two-dimensionally in the vertical and horizontal directions are provided to the vertical CCDs 13 corresponding to the vertical columns of the sensor units 11. Thus, the signal charges are transferred vertically to the horizontal CCD 15, and then the signal charges are transferred in the horizontal direction by the horizontal CCD 15 based on the two-phase horizontal transfer pulses H 1 and H 2. Then, the operation of converting the potential to the potential corresponding to the signal charge from the horizontal CCD 15 by the charge voltage conversion unit 16 and outputting the same is repeated.

<Specific configuration of imaging area>
FIG. 3 is a plan pattern diagram illustrating an example of a specific configuration of the imaging area 14. FIG. 4 is a view showing a cross section taken along the line XX ′. Although only two pixels for the vertical transfer electrodes 24-1 to 24-4 are shown here, the same arrangement is repeated in the vertical direction for the vertical transfer electrodes 24-5 to 24-8.

  First, the vertical CCD 13 includes a transfer channel 23 made of N-type impurities formed on an N-type substrate 21 via a P-type well 22 and a four-phase array arranged repeatedly in the transfer direction above the transfer channel 23. Transfer electrodes 24-1 to 24-4. The wiring form (wiring pattern) of the transfer electrodes 24-1 to 24-4 is basically the same as the conventional one.

  Among these transfer electrodes 24-1 to 24-4, the second-phase transfer electrode 24-2 and the fourth-phase transfer electrode 24-4 are formed by the first layer of polysilicon (indicated by a one-dot chain line in the figure). A two-layer electrode structure is formed, in which the first-phase transfer electrode 24-1 and the third-phase transfer electrode 24-3 are formed of second-layer polysilicon (indicated by a two-dot chain line in the figure). Yes. The material of the transfer electrodes 24-1 to 24-4 is not necessarily limited to polysilicon.

  Further, in the region below the first-phase and third-phase transfer electrodes 24-1 and 24-3, approximately half of the region upstream of the signal charge transfer direction (from left to right in FIG. 3). A P− type impurity layer 25 is formed on the substrate surface side. As a result, a potential gradient that is inclined downward in the signal charge transfer direction is formed in the transfer channel 23 formed in the region below the first-phase and third-phase transfer electrodes 24-1 and 24-3. The As a result, the signal charges transferred below the transfer electrodes 24-1 and 24-3 gradually move below the transfer electrodes 24-2 and 24-4 due to the potential gradient. In this way, the transfer efficiency is improved by combining with the extension of the overlap period of the vertical transfer clock.

  A polysilicon opening 26 is provided on the sensor unit 11 in the first and second polysilicon layers forming the transfer electrodes 24-1 to 24-4. The upper side of the transfer electrodes 24-1 to 24-4 is covered with a light shielding film 27 made of aluminum. In the light-shielding film 27, a sensor opening 28 is formed on the sensor unit 11 inside the polysilicon opening 26. As the material of the light shielding film 27, a material other than aluminum may be used.

<Vertical transfer electrode wiring pattern>
FIG. 5 is a wiring pattern diagram of transfer electrodes in the vertical CCD 13, FIG. 5A shows a field of 6-phase driving (24-1 to 24-6), and FIG. The field (24-1 to 24-8) is shown. In this wiring system, vertical transfer drive pulses φV1 to φV6 (φV8) for the first to sixth phases (eighth phase) are prepared, and a total of six (eight) pulses are transmitted to transmit the vertical transfer clock. Bus lines 31 to 36 (38) are wired.

  A first-phase transfer electrode 24-1 is connected to the bus line 31 for transmitting the vertical transfer drive pulse φV1 every 5 pixels (7 pixels). Similarly, the bus lines 32-36 (38) for transmitting the vertical transfer drive pulses φV2 to φV6 (φV8) have the second to sixth phase (eighth phase) transfer electrodes 24-2 to 24-6. (24-8) are connected every 5 pixels (7 pixels).

  The vertical transfer channel 23 formed by the vertical CCD 13 has a timing having a predetermined pattern on the transfer electrodes 24-1 to 24-6 (24-8) so that signal charges are sequentially transferred in the direction indicated by an arrow in the figure. Drive pulses φV1 to φV6 (φV8) are applied.

  Next, a specific example of a method of driving the CCD solid-state imaging device 10 by the timing signal generation unit 40 that is a characteristic part of the present embodiment will be described. First, the three-field reading method will be described.

<3-field readout method>
6, 7, 8, and 9 are diagrams for explaining the operation of the three-field reading method. Here, FIG. 6 shows an outline thereof, and FIG. 7 is a timing chart of the vertical transfer drive pulses φV1 to φV6 at the vertical rate. 8 and 9 are timing charts and charge transfer states of vertical transfer drive pulses φV1 to φV6 for explaining the operation mode of the frame reading method in the three-field reading method.

  In the schematic diagram of FIG. 6, squares indicated by R, G, and B (each color of the color separation filter) of each field indicate pixels. A vertical line number is shown on the left side of the vertical CCD 13 (the lower horizontal CCD 15 side is first), and a readout pulse for the line is shown in parentheses. The readout target line is suggested by an arrow from the pixel indicated by the rectangle to the vertical CCD 13.

  Here, in the conventional two-field readout method (frame readout method), as shown in FIG. 16, only one pixel out of two pixels is read out in one field, so two pixels (φV1 to φV4 as shown in FIG. 19). ) For a vertical CCD (vertical register) packet.

  On the other hand, in the three-field reading method, as shown in FIG. 6, only one pixel out of three pixels is read out in one field, so that three pixels (V1 to V6) are also shown in FIG. Thus, a vertical CCD packet may be configured. That is, signal charges are read from the sensor unit 11 to the vertical CCD 13 every two pixels in the vertical direction. Therefore, the number of on-transfer channels of the vertical CCD can be 4 channels in the 3 field readout system (frame readout system), compared to 2 channels in the 2 field readout system (frame readout system). It becomes possible to increase the amount of charge handled by the vertical CCD.

  Here, as shown in FIG. 7, in the vertical CCD 13, the first-phase, third-phase, and fifth-phase transfer electrodes 24 also serve as the electrodes of the read gate unit 12. Accordingly, among the six-phase vertical transfer drive pulses φV1 to φV6, the drive pulses φV1, φV3, and φV5 based on the transfer clocks V1, V3, and V5 of the first phase, the third phase, and the fifth phase are low. It is set to take three values: a level (hereinafter referred to as “L” level), an intermediate level (hereinafter referred to as “M” level), and a high level (hereinafter referred to as “H” level). The “H” level drive pulse of the eye becomes the drive pulse of the read gate section 12 corresponding to the read pulse XSG. As described above, the vertical transfer drive pulses φV1, φV3, and φV5 are read pulses for driving the read gate unit 12 when the third “H” level pulse reads the signal charge from the sensor unit 11. .

  Note that the drive pulses φV1 (φV2) and φV3 (φV4) of the first phase (second phase) and the third phase (fourth phase) are substantially different in phase so as to define the repeating unit of the three fields. However, the drive pulse φV5 (φV6) of the final fifth phase (sixth phase) is different from the first to fourth phases in the relationship between the L, M, and H levels. In the above description, the parentheses indicate pairs of the remaining drive pulses φV2, φV4, and φV6, and each is set to take a binary value of “M” level and “L” level.

  In the frame read operation mode, as shown in FIG. 6, the read pulse of vertical transfer drive pulse φV3 is generated in the first field, the read pulse of vertical transfer drive pulse φV1 is generated in the second field, and vertical transfer is performed. A read pulse of drive pulse φV5 is generated in the third field. In the line thinning-out operation mode, a read pulse is generated in the vertical transfer drive pulses φV1, φV3, and φV5 in the first, second, and third fields.

  Next, signal charge readout and vertical transfer operations during a frame readout operation in the three-field readout method will be described with reference to FIGS. In FIG. 9, the direction from the right side to the left side is the charge transfer direction.

  As shown in FIG. 8, the characteristic part of the driving method of the present embodiment is that, for each unit of charge packet in vertical transfer, almost simultaneously with turning on the transfer channel ahead of the charge packet in the vertical transfer direction, The transfer channel at the rear end of the charge packet is turned off. For example, one transfer channel located at the rear end of the charge packet immediately before the transfer, almost simultaneously with turning on one of the transfer channels immediately preceding (positioned immediately before) the charge packet immediately before the current transfer, That is, the transfer channel located at the end is turned off. This will be specifically described below.

  When reading the signal charges from each sensor unit 11, in the first field, the vertical transfer drive pulse φV3 shown in FIG. 7 is applied to the third-phase transfer electrode 24-3. As a result, a readout pulse is applied to the readout gate unit 12 of the first phase, so that signal charges are read out from the sensor unit 11 to the vertical CCD 13 every two pixels in the vertical direction.

  The read signal charges are vertically transferred line by line in the horizontal blanking period by the transfer operation of the vertical CCD 13. At a time point t0 immediately before the transition to the line shift period, as shown in FIG. 8, drive pulses φV1, φV2, and φV3 based on the vertical transfer clocks of the first phase, the second phase, the third phase, and the fourth phase. , ΦV4 are both at the “M” level. Therefore, as shown in FIG. 9, the potentials under the transfer electrodes 24-1, 24-2, 24-3, and 24-4 of the first phase, the second phase, the third phase, and the fourth phase are Deeper, one unit of charge packet (= transfer packet) is formed, and each signal charge Qs is accumulated in this packet.

  When the line shift operation is started and the fifth-phase vertical transfer drive pulse φV5 transitions from the “L” level to the “M” level (time point t1), the potential below the fifth-phase transfer electrode 24-5 is Deepen. As a result, the signal charge Qs of the packet below the first-phase, second-phase, third-phase, and fourth-phase transfer electrodes 24-1, 24-2, 24-3, 24-4 is changed to the fifth phase. It becomes possible to move under the transfer electrode 24-5.

  Here, as a drive control method peculiar to the present embodiment, at the time of transition from the period t0 to the period t1, the drive pulse φV5 that forms the forward transfer channel in the transfer direction is changed from “L” to “M” (timing signal). The output of the generator 40 is changed from “L” to “H” (the same applies hereinafter) (at the same time the potential of the vertical register becomes deep and becomes an accumulation state), and at the same time, a drive pulse that forms a transfer channel behind in the transfer direction φV1 is changed from “M” to “L” (the output of the timing signal generation unit 40 is “H” → “L”; the same applies hereinafter) (the potential of the vertical register becomes shallower and the transfer state to the next transfer channel is changed) ).

  As a result, the signal charge Qs of the packet formed under the transfer electrodes 24-1, 24-2, 24-3, and 24-4 at the time point t0 becomes the transfer electrode 24-2, 24-3,. It is transferred to a packet formed under 24-4 and 24-5.

  Subsequently, when the sixth-phase vertical transfer drive pulse φV6 transitions from the “L” level to the “M” level (time point t2), the potential below the sixth-phase transfer electrode 24-6 becomes deeper. As a result, the signal charges Qs of the packets under the transfer electrodes 24-2, 24-3, 24-4, and 24-5 of the second phase, the third phase, the fourth phase, and the fifth phase are changed to the sixth phase. It becomes possible to move to below the transfer electrode 24-6.

  Here, as a drive control method peculiar to the present embodiment, the drive pulse φV6 that forms the forward transfer channel in the transfer direction is changed from “L” to “M” at the transition from the period t1 to the period t2. At substantially the same time, the drive pulse φV2 forming the rear transfer channel in the transfer direction is changed from “M” to “L”.

  As a result, the signal charge Qs of the packet formed under the transfer electrodes 24-2, 24-3, 24-4, and 24-5 at the time t1 becomes the transfer electrodes 24-3, 24-4, and 24-5 at the time t2. It is transferred to a packet formed under 24-5 and 24-6.

  The same operation is repeated thereafter. That is, when the vertical transfer drive pulse φV1 of the first phase, which is the forward transfer channel in the transfer direction, transitions from the “L” level to the “M” level (time point t3), almost simultaneously with the change, By changing the drive pulse φV3 forming the transfer channel from “M” to “L”, it was formed below the transfer electrodes 24-3, 24-4, 24-5, 24-6 at the time t2. The signal charge Qs of the packet is transferred to the packet formed under the transfer electrodes 24-4, 24-5, 24-6, 24-1 at time t3.

  When the vertical transfer drive pulse φV2 of the second phase, which is the forward transfer channel in the transfer direction, transitions from the “L” level to the “M” level (time point t4), almost simultaneously with the change, By changing the drive pulse φV4 forming the transfer channel from “M” to “L”, it was formed below the transfer electrodes 24-4, 24-5, 24-6, 24-1 at time t3. The signal charge Qs of the packet is transferred to the packet formed under the transfer electrodes 24-5, 24-6, 24-1, 24-2 at time t4.

  When the third-phase vertical transfer drive pulse φV3, which is the forward transfer channel in the transfer direction, transits from the “L” level to the “M” level (time point t5), almost simultaneously with the change, By changing the drive pulse φV5 forming the transfer channel from “M” to “L”, it was formed below the transfer electrodes 24-5, 24-6, 24-1, 24-2 at time t4. The signal charge Qs of the packet is transferred to the packet formed below the transfer electrodes 24-6, 24-1, 24-2, and 24-3 at time t5.

  When the fourth-phase vertical transfer drive pulse φV4, which is the forward transfer channel in the transfer direction, transitions from the “L” level to the “M” level (time point t6), almost simultaneously with the change, By changing the drive pulse φV6 forming the transfer channel from “M” to “L”, it was formed below the transfer electrodes 24-6, 24-1, 24-2, 24-3 at time t5. The signal charge Qs of the packet is transferred to the packet formed below the transfer electrodes 24-1, 24-2, 24-3, and 24-4 at time t6.

  Through a series of vertical transfer operations in the above-described line shift period, signals read from each of the sensor units 11 and accumulated in packets below the first-phase to sixth-phase transfer electrodes 24-1 to 24-6. The electric charge Qs is shifted by one line and is sequentially stored in the packets below the transfer electrodes 24-1 to 24-6 of the next first to sixth phases.

  At this time, the signal charge for one line at the lowermost end of the imaging area 14 is transferred to the horizontal CCD 15. The signal charges for one line transferred to the horizontal CCD 15 are sequentially transferred in the horizontal direction by the transfer drive of the horizontal CCD 15 in the horizontal scanning period after the horizontal blanking period.

  In the above description of the operation, the case of the first field has been described. However, in the case of the second (third) field, the transfer electrode 24-1 (24-5) of the first phase (fifth phase) is used. By applying the vertical transfer drive pulse φV1 (φV5) shown in FIG. 7, a read pulse is given to the read gate section 12 of the first phase (fifth phase), and every other pixel in the vertical direction, Signal charges are read out to the vertical CCD 13 from a sensor unit 11 different from that in the first field. Subsequent vertical transfer operations are performed in the same manner as in the first field.

  As described above, when the forward transfer channel in the transfer direction is turned on at the same time as the forward transfer channel is turned on for each charge packet unit in the vertical transfer, the vertical transfer period is t0 in FIG. Can be reduced to t0 to t6 as shown in FIG. Also, the overlap period of the vertical transfer clock can be increased (doubled) from the previous “2 / 3x” shown in FIG. 27 to “4 / 3x” shown in FIG. As a result, there is a margin for the propagation delay of the vertical transfer clock.

  Therefore, by adopting the transfer timing as in the present embodiment, a propagation delay (in this case, physically considered on the same time axis) occurs in the vertical transfer clock even in the three-field read method of the six-phase driving of V1 to V6. However, it can be prevented that it becomes a problem, and the problem of a decrease in transfer efficiency is avoided even in the center of the device that is far from the input terminal of the drive pulse in the imaging area 14 or on the opposite side of the input end. can do. That is, when viewed in one unit of vertical transfer cycle (that is, in terms of a relative time axis), a vertical transfer pulse having a predetermined waveform is transferred from the timing signal generator 40 to the CCD solid-state imaging device 10 via the driver 42. When applied to the electrode, the waveform of the drive pulse that drives the transfer electrode does not become dull as shown in FIG. 24 even at the center of the imaging area 14 or on the side opposite to the input end, and the transfer efficiency of the vertical CCD 13 is improved. It means that it will be improved.

  For example, at the conventional drive timing, the overlap period of each clock is short and becomes “2 / 3x”. Here, since the vertical transfer drive pulses φV1 to φV6 are transmitted from one side or both sides of the imaging area 14 to the transfer electrodes 24-1 to 24-6 of the vertical CCD 13, the wiring resistance is formed in the central portion of the imaging area 14. As a result, the amplitude of the vertical transfer drive pulses φV1 to φV6 decreases, or the waveform of the vertical transfer drive pulses φV1 to φV6 becomes dull as shown in FIG. Decrease or transfer efficiency deteriorates.

  On the other hand, as in this embodiment, when the forward transfer channel in the transfer direction is turned on and the backward transfer channel is turned off for each charge packet unit, the overlap period of both clocks is the previous drive timing. It becomes "4 / 3x" which is twice ("2 / 3x"). As described in Patent Document 1 and the like, a longer overlap period of the vertical transfer clock is advantageous for signal charge transfer, and the drive timing of the present embodiment is more than the case of the previous drive timing. Transfer efficiency can be improved.

  Regarding the amount of charge handled by the vertical register, as described above, the number of on-transfer channels of the vertical register is large, and in the operation of the three-field reading method / frame reading method, transfer 1 with six vertical transfer electrodes as one unit. The charge packet size at the time of vertical transfer per cycle is advantageous because it can secure only four vertical transfer electrodes among the six vertical transfer electrodes. Accordingly, even with the vertical transfer timing of the present embodiment in the operation of the three-field readout method / frame readout method, the amount of charge handled by the vertical register can be secured even if the cell size is reduced. This is advantageous for downsizing.

  Note that, as described above, the driving method at the time of vertical transfer of “turning off the rear transfer channel almost simultaneously with turning on the front transfer channel in the vertical transfer direction” is applied to the frame reading method as described above. It will be easily understood that the present invention can be applied to the line thinning operation.

  That is, in the case of the three-field readout method, the vertical transfer drive pulses φV1, φV3, and φV5 are read when the third “H” level pulse reads the signal charge from the sensor unit 11 as described above. This is a read pulse for driving the gate unit 12. In the frame reading method, the fields where the reading pulses are set in the vertical transfer drive pulses φV1, φV3, and φV5 are sequentially switched, whereas in the line thinning method, the two-field reading method is the same as in FIG. The first, second, and third fields are divided into two systems, and a read pulse is generated in the vertical transfer drive pulses φV1, φV3, and φV5 in the first, second, and third fields of one system, A read pulse is prevented from standing in the first, second, and third fields of the other system.

  Further, in the line thinning method, empty packets that do not include signal charges existing behind the packet including the signal charge Qs are mixed in the horizontal register and the no-signal period is removed. However, the basic vertical transfer itself may be the same as that in the frame reading method described above. Here, an example in which the drive timing peculiar to the present embodiment is applied to the line thinning operation is omitted from the illustration.

  If the driving method of the above embodiment is applied to the line thinning operation, the line thinning operation, that is, the number of lines of the imaging signal to be output can be reduced only by changing the timing of the driving system of the solid-state imaging device in the same manner as before. By performing an operation for obtaining a higher-speed imaging signal, it is possible to realize an operation mode for obtaining a higher-speed imaging signal, for example, an output signal corresponding to the NTSC system, without increasing the data rate. Since such a high-speed reading operation can be realized without using a method of increasing the horizontal drive frequency, other problems such as deterioration in transfer efficiency of the horizontal register and increase in power consumption of the horizontal register are not caused. In addition, by applying the same vertical drive timing as in the above-described embodiment in the frame readout method at that time, it is possible to obtain a high-speed imaging signal and improve transfer efficiency. This enables smooth video display by obtaining high-speed imaging signals when displaying captured images on a normal television monitor, or when performing automatic control such as automatic focus control, automatic iris control, or automatic white balance control. In addition, accurate automatic control can be realized.

  As described above, the driving method at the time of vertical transfer such as “turning the rear transfer channel off at almost the same time as turning on the front transfer channel in the vertical transfer direction” as in the above embodiment is not limited to the frame readout method, and line thinning is performed. It can be applied to the operation as well, and has a versatile drive system.

<4-field readout method>
Next, a four-field reading method under the drive control by the timing signal generator 40 will be described.

  10, FIG. 11, FIG. 12, and FIG. 13 are diagrams for explaining the operation of the four-field reading method. Here, FIG. 10 shows the outline, and FIG. 11 is a timing chart of the vertical transfer drive pulses φV1 to φV8 at the vertical rate. FIGS. 12 and 13 are timing charts and charge transfer states of vertical transfer drive pulses φV1 to φV8 for explaining an operation mode of the frame reading method in the four-field reading method. Each figure is shown in the same manner as in the three-field reading method.

  As can be seen from the comparison with the case of the three-field readout method, only one of the four pixels is read out in one field, so that a vertical CCD packet may be configured for four pixels (V1 to V8). . That is, signal charges are read from the sensor unit 11 to the vertical CCD 13 every three pixels in the vertical direction. Therefore, the number of on-transfer channels of the vertical CCD can be 6 transfer channels in the 4-field readout system (frame readout system), and the amount of charge handled by the vertical CCD is further increased than in the 3-field readout system (frame readout system). Can be increased.

  Here, as shown in FIG. 11, in the vertical CCD 13, the first-phase, third-phase, fifth-phase, and seventh-phase transfer electrodes 24 also serve as the electrodes of the read gate unit 12. Therefore, among the 8-phase vertical transfer drive pulses φV1 to φV8, the drive pulses φV1 based on the transfer clocks V1, V3, V5, and V7 of the first phase, the third phase, the fifth phase, and the seventh phase. , ΦV3, φV5, and φV7 take three values: a low level (hereinafter referred to as “L” level), an intermediate level (hereinafter referred to as “M” level), and a high level (hereinafter referred to as “H” level). The third “H” level drive pulse that has been set becomes the drive pulse of the read gate section 12 corresponding to the read pulse XSG.

  Note that the drive pulses φV1, φV3, and φV5 of the first, third, and fifth phases are substantially different in phase to define the repetition unit of the four fields, but the last seven-phase drive pulse In φV7, the relationship between each level of L, M, and H is different from that of the first phase, the third phase, and the fifth phase. The remaining drive pulses φV2, φV4, φV6, and φV8 to be paired are set to take two values of “M” level and “L” level.

  As described above, the vertical transfer drive pulses φV1, φV3, φV5, and φV7 are read pulses that drive the read gate unit 12 when the third-level “H” level pulse reads the signal charge from the sensor unit 11. It becomes. As shown in FIG. 10, in the frame read operation mode, the read pulse of vertical transfer drive pulse φV5 is generated in the first field, the read pulse of vertical transfer drive pulse φV3 is generated in the second field, and vertical transfer is performed. A read pulse of drive pulse φV1 is generated in the third field, and a read pulse of vertical transfer drive pulse φV7 is generated in the fourth field. In the line thinning-out operation mode, a read pulse is generated in the vertical transfer drive pulses φV1, φV3, φV5, and φV7 in each of the first to fourth fields.

  Next, signal charge readout and vertical transfer operations during a frame readout operation in the four-field readout method will be described with reference to FIGS. In FIG. 13, the direction from the right side to the left side is the charge transfer direction.

  Also in the 4-field readout method, as shown in FIG. 12, the backward transfer channel is turned off almost simultaneously with the forward transfer channel in the transfer direction being turned on for each unit of the charge packet in the vertical transfer. There is a characteristic part in the driving method of the present embodiment. This will be specifically described below.

  When reading the signal charges from each sensor unit 11, in the first field, the vertical transfer drive pulse φV5 shown in FIG. 11 is applied to the transfer electrode 24-5 of the fifth phase. As a result, a readout pulse is applied to the readout gate section 12 of the fifth phase, so that signal charges are read from the sensor section 11 to the vertical CCD 13 every three pixels in the vertical direction.

  The read signal charges are vertically transferred line by line in the horizontal blanking period by the transfer operation of the vertical CCD 13. At a time point t0 immediately before the shift to the line shift period, as shown in FIG. 12, the drive pulses φV1 to φV6 based on the vertical transfer pulses of the first phase to the sixth phase are all at the “M” level. For this reason, as shown in FIG. 13, the potential under each of the transfer electrodes 24-1 to 24-6 of the first phase to the sixth phase is deepened to form one unit of charge packet (= transfer packet). Each signal charge Qs is accumulated in this packet.

  When the line shift operation is started and the seventh-phase vertical transfer drive pulse φV7 changes from the “L” level to the “M” level (time point t1), the potential below the seventh-phase transfer electrode 24-7 is Deepen. As a result, the signal charge Qs of the packet below the first-phase to sixth-phase transfer electrodes 24-1 to 24-6 can move to below the seventh-phase transfer electrode 24-7.

  Here, as a drive control method peculiar to the present embodiment, at the time of transition from the period t0 to the period t1, the drive pulse φV7 that forms the forward transfer channel in the transfer direction is changed from “L” to “M” (timing signal). The output of the generator 40 is changed from “L” to “H” (the same applies hereinafter) (at the same time the potential of the vertical register becomes deep and becomes an accumulation state), and at the same time, a drive pulse that forms a transfer channel behind in the transfer direction φV1 is changed from “M” to “L” (the output of the timing signal generation unit 40 is “H” → “L”; the same applies hereinafter) (the potential of the vertical register becomes shallower and the transfer state to the next transfer channel is changed) ).

  Thereby, the signal charge Qs of the packet formed under the transfer electrodes 24-1 to 24-6 at time t0 is transferred to the packet formed under the transfer electrodes 24-2 to 24-7 at time t1. Is done. As described above, the charge packet size during the transfer operation substantially matches the initial packet size.

  Hereinafter, as in the case of the three-field reading method, the same operation as at t0 → t1 is repeated. As a result, the signal charge accumulated in the transfer channel formed below the transfer electrodes 24-2 to 24-7 at the time point t1 is transferred to the bottom of the transfer electrodes 24-3 to 24-8 from t1 to t2. → At t3, below transfer electrodes 24-4 to 24-1, at t3 → t4, below transfer electrodes 24-5 to 24-2, and at t4 → t5, below transfer electrodes 24-6 to 24-3, From t5 to t6, below transfer electrodes 24-7 to 24-4, from t6 to t7, below transfer electrodes 24-8 to 24-5, and from t7 to t8, below transfer electrodes 24-1 to 24-6. Then, it is transferred sequentially.

  Through a series of vertical transfer operations in the above line shift period, signals read from each of the sensor units 11 and accumulated in packets below the first to eighth phase transfer electrodes 24-1 to 24-8. The electric charge Qs is shifted by one line and is sequentially stored in packets below the transfer electrodes 24-1 to 24-8 of the next first to eighth phases. The signal charge for one line at the lowermost end of the imaging area 14 is transferred to the horizontal CCD 15. The signal charges for one line transferred to the horizontal CCD 15 are sequentially transferred in the horizontal direction by the transfer drive of the horizontal CCD 15 in the horizontal scanning period after the horizontal blanking period.

  In the above description of the operation, the case of the first field has been described. However, in the case of the second (third, fourth) field, the transfer electrode 24-3 of the third phase (first phase, seventh phase) is used. By applying the vertical transfer drive pulse φV3 (φV1, φV7) shown in FIG. 11 to (24-1, 24-7), the read gate section 12 of the third phase (first phase, seventh phase) is applied. Is read out, and signal charges are read out from the sensor unit 11 different from that in the first field to the vertical CCD 13 every other pixel in the vertical direction. Subsequent vertical transfer operations are performed in the same manner as in the first field.

  As described above, even in the case of the 4-field readout method, if the forward transfer channel in the transfer direction is turned on almost simultaneously with the turn-on of the forward transfer channel for each charge packet unit in the vertical transfer, The vertical transfer period is t0 to t8 as shown in FIG. 12, and the overlap period of the vertical transfer clock can be x (= 4 / 4x) as shown in FIG. Here, although not shown in the figure, at the transfer timing of the conventional 8-phase drive, the period from t0 to t16 is necessary, and the overlap period of the vertical transfer clock is “1 / 4x”. Therefore, by adopting the transfer timing as in this embodiment, it is possible to make the overlap period of the vertical transfer clock longer than that in the conventional case, and a margin is provided for the propagation delay of the vertical transfer clock.

  Therefore, for each charge packet unit in the vertical transfer, the transfer timing is such that the forward transfer channel in the transfer direction is turned on almost at the same time as the backward transfer channel is turned off. Even in the readout method, a propagation delay hardly occurs in the vertical transfer clock, and the waveform of the drive pulse for driving the transfer electrode does not become dull as shown in FIG. Efficiency is improved.

  As in the case of the three-field reading method, the vertical transfer driving timing as described above is not limited to being applied to the frame reading method, but can also be applied to the line thinning operation.

  When comparing the 4-field readout system and the 3-field readout system, as described above, the number of on-transfer channels of the vertical CCD is 6 transfer channels in the 4-field readout system (frame readout system). The amount of charge handled by the vertical CCD can be further increased than in the case of the three-field readout method (frame readout method), and there is an advantage in reducing the cell size. In this case, the 4-field readout method is more advantageous.

  By the way, in the description of each frame reading operation in the above-described three-field reading method or four-field reading method, “almost simultaneous” when it is described that turning on the forward transfer channel in the transfer direction turns “almost simultaneous” and turning off the rear transfer channel. "Is not necessarily strictly" simultaneous "for the same purpose as described above, and may be a case where, for example, a slight delay between clocks has occurred. Means. In short, it is sufficient if there is enough room to improve the transfer efficiency of the vertical CCD 13 due to the propagation delay of the vertical transfer clock. The significance of this will be briefly described below together with the amount of charge handled by the vertical CCD.

<Relationship between drive pulse delay and handling charge amount>
FIG. 14 is a diagram for explaining the amount of charge handled by the vertical CCD in relation to the drive pulse delay. Here, the case of the three-field reading method and the frame reading operation will be described, but the same applies to the case of the four-field reading method and the frame reading operation, and further, the thinning-out reading operation.

  As shown in FIG. 9, the signal charge Qs is accumulated in the packet formed under the transfer electrodes 24-1, 24-2, 24-3, 24-4 at time t0. This state is shown in FIG.

  Thereafter, as the transfer timing of the present embodiment, when the forward transfer channel in the transfer direction is turned on, the backward transfer channel is turned off “substantially simultaneously”, so the potentials on both sides of the packet storing the signal charge Qs move simultaneously. It will be. For example, in the charge transfer process from t0 to t1, a charge well is formed under the transfer electrode 24-5 and the charge well under the transfer electrode 24-1 disappears. If the difference does not occur, as shown in FIG. 14B, the charge well starts to be formed under the transfer electrode 24-5, and at the same time, the charge well under the transfer electrode 24-1 existing before that A shallow state temporarily occurs. At this time, the amount of charge to be handled (charge accumulation amount) does not change theoretically, but tends to decrease somewhat when a timing shift occurs.

  For example, the drive pulse φV1 changes from “L” level to “M” level (the potential of the vertical register becomes deep and becomes an accumulation state) rather than the drive pulse φV5 changes from “L” level to “M” level. If the change to the “L” level (the potential of the vertical register becomes shallower and the transfer state to the next transfer channel becomes slightly faster), as shown in FIG. After the charge well under the transfer electrode 24-1 becomes considerably shallow, a state temporarily occurs where a charge well starts to be formed under the transfer electrode 24-5. At this time, the amount of charge handled decreases slightly.

  Further, when the drive pulse φV1 changes from “H” level to “L” level much faster than the drive pulse φV5 changes from “L” level to “M” level, FIG. As shown in (D), after the charge well under the transfer electrode 24-1 that existed before completely disappears, the charge well starts to be formed under the transfer electrode 24-5. Arise. At this time, the transfer channel under the transfer electrode 24-1 cannot contribute to charge accumulation, and temporarily accumulates charge in only three transfer channels (charge wells). This reduces the amount of charge handled.

  However, although not shown in the figure, in the line thinning operation, there is an empty packet B behind the packet A including the signal charge Qs, so even if the signal charge Qs overflows in the packet A, the empty packet B behind If it does not overflow, the charges of the packets A and B are finally mixed in the horizontal CCD 15, so there is no problem, and therefore the amount of charge handled by the vertical CCD 13 does not decrease.

  Such a shift in the drive pulse switching timing does not exist in the transfer clocks V1 to V6 (V8) output from the timing signal generation unit 40, even if the drive pulse is properly applied to the input point of the transfer electrode. As shown in FIG. 24, passing through the transfer electrode causes a propagation delay, and the delay amount between the electrodes is not necessarily uniform. It is inevitable. Further, depending on the circuit configuration of the timing signal generation unit 40, there may be a shift in the transfer clocks V1 to V6 (V8) themselves output from the timing signal generation unit 40.

  However, even if there is a deviation due to the propagation delay as shown in FIG. 24 or there is a deviation in the output from the timing signal generator 40, the difference in delay is within a certain range. As can be seen from the above explanation, there is virtually no problem.

  As described above, the three-field or four-field read method (frame read method / decimation method) is used for the vertical transfer driving method of “turning off the rear transfer channel almost simultaneously with turning on the forward transfer channel in the vertical transfer direction”. Although a specific example of application to any reading method is illustrated, such a driving method is not limited to a three-field or four-field reading method, and more than that, for example, 10-phase driving (φV1 to φV10) It can also be applied to the five-field readout method of FIG. It can be easily understood from the above description of the three-field or four-field reading method that the overlap period of the vertical transfer clock can be increased thereby improving the transfer efficiency of the vertical register. In this case as well, the present invention can be applied not only to the frame reading method but also to the thinning reading method.

  Further, the driving method at the time of the vertical transfer of “turning off the rear transfer channel almost simultaneously with turning on the forward transfer channel in the vertical transfer direction” is not limited to the frame reading method or the thinning reading method of 3 fields or more. The present invention can also be applied to a field frame reading method and a thinning reading method. In this case, the thinning readout operation is similar to the technique described in Patent Document 1 at first glance. However, its significance and the effects are different. Hereinafter, this point will be described.

<Difference between each technology of this embodiment and Patent Document 1 in 2-field readout method>
FIG. 15 is a diagram for explaining the operation of the 2-field readout method and the 2/8 line thinning-out readout method. Here, FIG. 15 (A) is the same as FIG. 22 and shows the drive timing according to the conventional example (basic form). FIG. 15B shows the drive timing according to the present embodiment, and FIG. 15C shows the drive timing to which the complementary drive according to Patent Document 1 is applied. FIG. 15D is an enlarged view at the time of switching the transfer clock output from the timing signal generation unit 40 for explaining the difference between each technique of the present embodiment and Patent Document 1.

  As shown in FIG. 15A, in the conventional basic driving timing, 16 cycles (t1 to t16) are required to transfer two lines. When the overlap period of the vertical transfer clock for transferring one line during the frame reading operation shown in FIG. 18 is “x”, two lines are used in the conventional basic driving timing shown in FIG. Therefore, the vertical transfer clock overlap period is “1 / 2x”.

  On the other hand, the drive timing of this embodiment is “turning off the rear transfer channel almost simultaneously with turning on the front transfer channel in the vertical transfer direction”, as shown in FIG. In order to perform transfer for two lines, eight cycles (t1 to t8) are sufficient, and high-speed transfer is possible. In addition, by performing vertical transfer in this way, it is possible to lengthen the overlap period of the vertical transfer clock and set the same “x” as the conventional basic drive timing.

  By the way, the drive timing and the overlap period of the vertical transfer clock in this embodiment are substantially the same as those in Patent Document 1 shown in FIG. That is, as long as the drive pulse timings are compared, at first glance they are similar. However, the essence of each technical meaning is completely different.

  That is, as shown in FIG. 15 (D2), in the method of Patent Document 1 in which vertical transfer is performed by a combination of vertical transfer clock pairs having mutually opposite phases (complementary) at the time of line thinning, the timing signal generator 40 outputs the signal. In principle, there is no deviation between the falling edge and the rising edge (at each time point from t1 to t8 in the figure) of the transfer clocks V1 to V6 (V8). This is because it means "reciprocal to each other (complementary)". If there is a deviation, it should be considered at most as a “gate delay difference” of logic gates (for example, AND gates and OR gates) constituting the circuit.

  On the other hand, in the method of this embodiment, as shown in FIG. 15 (D1), “turning on the forward transfer channel in the vertical transfer direction and turning off the backward transfer channel“ almost at the same time ”. Even if there is a certain amount of deviation between falling and rising between corresponding pulses, as will be understood from the explanation of FIG. 14, it does not matter. The state where there is no accidental shift is merely that the waveform is the same as the “opposite phase” state. The concept of the application range with respect to the “deviation” at the falling edge and the rising edge between the corresponding pulses is completely different.

  As described above, when the driving method of the present embodiment and the driving method of Patent Document 1 are compared with respect to the two-field reading method and the line thinning-out reading method, the driving timing and the overlap period of the vertical transfer clock are seemingly at a glance. Are similar, but their technical implications are different. In addition, in order to realize the driving method of Patent Document 1, there is a circuit design restriction that the transfer clocks that form a pair must be “in phase with each other (complementary)”. In the driving method, there is no such restriction, and it is sufficient to have a circuit configuration in which the falling and rising between corresponding pulses are made “almost simultaneously”, and there is an advantage that the degree of freedom in circuit design is large. is there. In consideration of the delay difference between the electrodes, the transfer pulse output from the timing signal generator 40 is positively shifted so that the overall transfer efficiency can be balanced.

  In the above embodiment, the case where the number of driving phases is an even number is shown. However, as can be seen from the above description, when the conventional driving method is an odd number (for example, three phases, five phases, or more). However, it is understood that the driving method of “turning off the rear transfer channel almost simultaneously with turning on the front transfer channel in the vertical transfer direction” can be applied, and the same effect as described above can be obtained. Is Rukoto.

  In the above-described embodiment, the case where the present invention is applied to an interline transfer type CCD solid-state image pickup device has been described. However, the present invention is not limited to this, and a CCD solid-state image pickup device other than the interline transfer type. Further, the present invention can be similarly applied to a solid-state imaging device using other than a CCD.

  DESCRIPTION OF SYMBOLS 1 ... Digital still camera, 2 ... Solid-state imaging device, 3 ... Imaging device module, 10 ... CCD solid-state image sensor, 11 ... Sensor part, 13 ... Vertical CCD, 14 ... Imaging area, 15 ... Horizontal CCD, 16 ... Charge voltage conversion , 40 ... Timing signal generator, 42 ... Driver, 46 ... Drive power supply, 50 ... Imaging lens, 96 ... Drive controller, 24_1 to 24_8 ... Vertical transfer electrode

Claims (8)

A method for driving a solid-state imaging device that vertically transfers signal charges obtained by photoelectric conversion,
Formed of an array of P-2 transfer channels successively turned on by a vertical transfer drive pulse applied to a vertical transfer electrode based on a vertical transfer pulse of P (P is a positive integer of 5 or more) phase, For each unit of charge packet for transferring signal charge, one transfer channel in front of the charge packet is turned on in the vertical transfer direction, and one charge packet at the end of the charge packet is transferred. A method for driving a solid-state imaging device, in which vertical transfer is performed with P-2 vertical transfer pulses continuously turned on in the vertical transfer direction being overlapped in the ON period by driving the channel to be turned off. The method for driving a solid-state imaging device according to claim 1, wherein line thinning operation is performed. The method for driving a solid-state imaging device according to claim 1, wherein the vertical transfer is performed by vertical transfer driving with an even number of phases of six or more phases. The method for driving a solid-state imaging device according to claim 1, wherein the vertical transfer is performed by a frame reading operation with three or more fields. The method for driving a solid-state imaging device according to claim 2, wherein the vertical transfer is performed by a line thinning-out reading operation with three or more fields. Performing vertical transfer with P-2 vertical transfer pulses continuously turned on in the vertical transfer direction, with the ON period overlapping, and
ON / OFF of a vertical transfer drive pulse for turning on one transfer channel ahead of the charge packet and a vertical transfer drive pulse for turning off one transfer channel at the end of the charge packet 6. The allowable range of deviation in switching timing of the charge packet is set such that the fluctuation amount of the handling charge amount of the charge packet is less than the accumulated charge amount of one transfer channel. A driving method of the solid-state imaging device described. A vertical transfer unit that vertically transfers signal charges obtained by photoelectric conversion based on a vertical transfer drive pulse applied to a vertical transfer electrode that vertically transfers signal charges, and a signal charge transferred from the vertical transfer unit is applied to a horizontal transfer electrode. A solid-state imaging device comprising a horizontal transfer unit that performs horizontal transfer based on a horizontal transfer drive pulse, and an output unit that outputs an imaging signal corresponding to the signal charge that has been horizontally transferred;
In the vertical transfer driving by the P (P is a positive integer of 5 or more) phase, it is formed by an array of P-2 transfer channels that are continuously turned on by the vertical transfer drive pulse applied to the vertical transfer electrode. For each unit of the charge packet for transferring the signal charge, one transfer channel in front of the charge packet is turned on in the vertical transfer direction, and one charge packet at the end of the charge packet is turned on. A timing signal for performing vertical transfer with P-2 vertical transfer pulses continuously turned on in the vertical transfer direction being overlapped with the ON period by generating vertical transfer pulses so that the transfer channel is turned off A generator,
A solid-state imaging device comprising: a drive unit that inputs a vertical transfer drive pulse based on the vertical transfer pulse generated by the timing signal generation unit to the vertical transfer electrode of the solid-state image sensor. An imaging lens that captures an optical image of the subject;
An imaging area composed of a plurality of sensor units on which optical images of the subject captured by the imaging lens are formed, and a signal charge obtained by photoelectric conversion in the sensor unit as a vertical transfer drive pulse applied to a vertical transfer electrode A vertical transfer unit that vertically transfers the signal charge, a horizontal transfer unit that horizontally transfers the signal charge transferred from the vertical transfer unit based on a horizontal transfer drive pulse applied to a horizontal transfer electrode, and the horizontally transferred signal charge A solid-state imaging device having an output unit that outputs an imaging signal corresponding to
In the vertical transfer driving by the P (P is a positive integer of 5 or more) phase, it is formed by an array of P-2 transfer channels that are continuously turned on by the vertical transfer drive pulse applied to the vertical transfer electrode. For each unit of the charge packet for transferring the signal charge, one transfer channel in front of the charge packet is turned on in the vertical transfer direction, and one charge packet at the end of the charge packet is turned on. A timing signal for performing vertical transfer with P-2 vertical transfer pulses continuously turned on in the vertical transfer direction being overlapped with the ON period by generating vertical transfer pulses so that the transfer channel is turned off A generator,
And a driving unit that inputs a vertical transfer drive pulse based on the vertical transfer pulse generated by the timing signal generation unit to the vertical transfer electrode of the solid-state imaging device.

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