JPH11275464A - Method for driving charge transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for driving a charge transfer device by which a difference from a pulse delay time caused by dispersion or the like in a gate capacitance is hardly affected regardless of short time charge transfer. SOLUTION: Four-phase transfer pulses are applied sequentially to transfer electrodes G1-G4. In the case of transferring charges stored in a depletion layer opposed to the two adjacent transmission electrodes G1, G2 to a depletion layer opposed to the two adjacent transmission electrodes G3, G4, this processing includes a state that charges are stored in a depletion layer opposed to the three adjacent transfer electrodes G1, G2, G3 including the two adjacent transmission electrodes G1, G2 before the transfer of the charges and the two adjacent transmission electrodes G2, G3 after the transfer of the charges, and a period Δt when the charges are stored in the depletion layer opposed to the three adjacent transfer electrodes G1, G2, G3 is selected to be 1-10% of the period when the charges are stored in the depletion layer opposed to the two adjacent transfer electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a charge transfer device used as a solid-state image sensor (image sensor) in, for example, an integrated video camera.

[0002]

2. Description of the Related Art FIG. 1 shows a cross-sectional structure of an embedded charge transfer device (hereinafter abbreviated as BCCD) widely used in an integrated video camera or the like. In FIG. 1, 1 is a P-type substrate, 2 is an n − buried layer as a buried charge transfer portion, and 3 is an n + diffusion layer. IS is an input source electrode for setting a charge injection potential, and IG is an input gate electrode for controlling a charge injection amount. G1 to G4 are 4
A transfer electrode that performs charge transfer by a phase clock,
OG is an output gate electrode. OS is a signal output electrode for converting the signal charge Q into a voltage V and outputting the voltage V, and is connected to the n + diffusion layer 3. OD is an output drain electrode,
RG is a reset gate electrode.

[0003] A DC voltage of about 2 volts is applied to the output gate electrode OG. The output drain electrode OD and the input source electrode IS have a voltage (for example, 1) at which the channel is depleted.
0 volts). FIG. 2 shows an example of the distribution of the channel depletion potential (hereinafter referred to as potential distribution) when 10 volts are applied to G1 and G2 of the four gate electrodes G1 to G4 and 0 volt is applied to G3 and G4. Shown in

In the first conventional driving method, a driving pulse as shown in FIG. 3 is applied to each of the electrodes G1 to G4, IG, and RG. In FIG. 3, for example, the H (high) level is 5V and the L (low) level is 0V. φG1 to φG4 indicate signals applied to the transfer electrodes G1 to G4, φIG indicates a signal applied to the input electrode IG, and φRG indicates a signal applied to the reset gate electrode RG.

FIGS. 4 to 6 show time t = t1 to t18 in FIG.
Shows the potential distribution at. First, time t
= T1, the pulses φG1, φG2 and φIG are H
The level and other pulses are at the L level, and charges are injected. At time t = t2, since φIG is at the L level, charges are accumulated under the gate electrodes G1 and G2. At time t = t3, in addition to the pulses φG1 and φG2, φG3 is also at the H level, and the electric charges are stored in the three gates G.
1, G2 and G3 (this period is called a diffusion period for convenience).

At time t = t4, the pulse φG1 changes to L level, and the electric charge under the transfer electrode (gate electrode) G1 is reduced by the fringe electric field to the two transfer electrodes G1.
It is transferred under the electrodes 2 and G3 (this period is called a transfer period for convenience). At time t = t5, in addition to the pulses φG2 and φG3, the pulse φG4 is also at the H level, and the charges are spread over the three gates φG2, φG3, and φG4. That is, the diffusion period has again started.

Thereafter, similarly, by repeating the diffusion period and the transfer period, charges are transferred rightward in FIGS. 4 to 6, and finally charges are output from the OS terminal. Next, in the second conventional driving method, the driving pulses φG1 to φG4, φIG, and φRG shown in FIG.
1 to G4, IG, and RG. The charge transfer device to which this driving method is applied is a BCCD having a structure as shown in FIG. 1 as in the first driving method. Hereinafter, the second conventional driving method will be described with reference to FIGS.

First, at time t = t1, a pulse φG
1, φG2 and φIG are at H level, other pulses are at L level
Level and charge is injected. At time t = t2, φ
Since the IG is at the L level, the charge is
1 and stored under G2. At t = t3, the pulses φG1 and φG3 change simultaneously. That is, at the same time as the pulse φG1 falls from the H level to the L level, the pulse φG3 rises from the L level to the H level. FIG. 8 shows a detailed timing at which the time axis is extended at this time.

As can be seen from FIG. 8, the pulse φG1 is H
Timing of falling from level to L level and pulse φ
G3 rises from the L level to the H level at the same time. When the pulse φG1 falls to 50% of the H level, the pulse φG3 rises to 50% of the H level.

At t = t4, the pulses φG2 and φG3 are H
The level and other pulses are at the L level, and the electric charge under the transfer electrode G1 is transferred under the two transfer electrodes G2 and G3 by the fringe electric field (transfer period).

At t = t5, the pulses φG2 and φG4 change simultaneously. That is, at the same time as the pulse φG2 falls from the H level to the L level, the pulse φG4 rises from the L level to the H level. The detailed timing at this time is the same as the change in the pulses φG1 and φG3 shown in FIG.

At t = t6, the pulses φG3 and φG4 are H
The level and other pulses are at the L level, and the electric charge under the electrode of the transfer electrode G2 is transferred under the electrodes of the two transfer electrodes G3 and G4 by the fringe electric field.

Thereafter, similarly, charges are transferred rightward in FIGS. 4 to 6, and finally charges are output from the OS terminal. In this driving method, the diffusion period in the first driving method, that is, the electric charge is applied to the three gate electrodes G1 and G2.
And the period of diffusion over G3 (t =
t3, t5, t7,..., t17) do not substantially exist. Two gate electrodes G1 and G2, or G2 and G
The charge transfer period in which charges exist under the third electrode is repeated, and the two gate electrodes move rightward in FIGS.

[0014]

The first driving method of the prior art described above is characterized in that the charge transfer is performed reliably by alternately repeating the charge diffusion period and the charge transfer period, but the transfer time is long. Disadvantageous. That is, the charge diffusion period is almost equal to the charge transfer period, and the time required for transfer per stage of the four-electrode CCD is, for example, eight unit times of t = t1 to t8.

On the other hand, in the second conventional driving method, since the charge diffusion period does not substantially exist as described above and the charge transfer is performed only in the charge transfer period, about half of the first driving method is performed. Charge can be transferred in time. However, for example, the falling of the pulse φG1 and the pulse φG3
Rise at almost the same time, its timing control must be critical. If the fall of pulse φG1 is earlier than the rise of pulse φG3 and a period occurs in which only φG2 of four gate pulse pulses φG1 to φG4 is at the H level, the transfer charge overflows from under the electrode. . Alternatively, it is necessary to reduce the maximum transfer charge amount in order to prevent such overflow. Since the gate capacitance is different for each electrode, there may be a case where a difference occurs in the actual internal timing of the element even when the timing of the pulse applied to the gate is exactly the same.

The present invention has been made in view of the above circumstances, and has as its object to enable the charge transfer in a short time and to reduce the difference in pulse delay time caused by variations in gate capacitance. It is an object of the present invention to provide a method for driving a charge transfer device which is less affected by the influence.

[0017]

According to the driving method of the charge transfer device of the present invention, the electric charge held over the depletion layer facing two or more several n adjacent transfer electrodes is reduced to 1 or n.
When moving to the depletion layer facing n adjacent transfer electrodes shifted by several m less than n + m adjacent transfer electrodes including n transfer electrodes before charge transfer and n transfer electrodes after charge transfer The state in which the charge is held over the depletion layer opposed to the transfer electrode is interposed, and the period for holding the charge over the depletion layer opposed to the (n + m) adjacent transfer electrodes is extended over the depletion layer opposed to the n adjacent transfer electrodes. It is characterized in that the period is set shorter than the period for retaining charges.

As a specific configuration, four-phase transfer pulses are sequentially applied to the transfer electrodes, and the charges held over the depletion layer facing the two adjacent transfer electrodes are shifted by two between the two adjacent transfer electrodes. When transferring to the depletion layer opposite to the transfer, two transfer electrodes before the charge transfer and two transfer electrodes after the charge transfer
A state in which charge is held across a depletion layer facing three adjacent transfer electrodes including three transfer electrodes is interposed, and a period in which charge is held across a depletion layer facing three adjacent transfer electrodes is set between two adjacent transfer electrodes. Is set to be shorter than the period for retaining charges over the depletion layer opposite to.

The period for holding the charge over the depletion layer facing n + m (for example, three) adjacent transfer electrodes is represented by n
It is preferable that the period is set within a range of 1 to 10% of a period for retaining charges over a depletion layer facing two (for example, two) adjacent transfer electrodes.

According to the above configuration, since a short diffusion period is provided between the transfer period and the next transfer period, the first conventional transfer period in which transfer periods and diffusion periods of the same length alternately occur. A driving method that enables charge transfer in a short time as compared with the driving method described above and is less susceptible to a difference in pulse delay time due to a variation in gate capacitance and the like, which is a problem of the conventional second driving method. Can be provided.

[0021]

Preferred embodiments of the present invention will be described below with reference to the drawings. In this embodiment, in the second driving method described in the conventional example, for example, instead of changing the pulses φG1 and φG3 simultaneously, the pulse φG1
Is characterized in that a delay time is provided in advance between the timing at which the signal φ falls from the H level to the L level and the timing at which the pulse φG3 rises from the L level to the H level.

Unlike the conventional timing shown in FIG.
In the present embodiment, the timing as shown in FIG. 9 is set. In other words, after the delay time Δt from the rise of the pulse φG3 to 50% of the H level, the pulse φG1 becomes 5% of the H level.
It falls to 0%.

The driving method of this embodiment will be described with reference to FIGS. 4 to 7 in the same manner as the description of the second driving method of the conventional example. At time t = t1, the pulses φG1, φG2, and φIG are at the H level, the other pulses are at the L level, and charges are injected. At time t = t2, since φIG is at the L level, the charges are not applied to the gate electrodes G1 and G2.
It is stored under. At t = t3, the pulses φG1 and φG3 change almost simultaneously. FIG. 9 shows a detailed timing at which the time axis is extended at this time.

As can be seen from FIG. 9, the pulse φG3 is H
The pulse φG1 falls to 50% of the H level after a delay time Δt after rising to 50% of the level. Delay time Δ
t is determined in consideration of a difference in timing that may occur inside an actual device due to a variation in gate capacitance or the like.

Usually, it is preferable to set the transfer time within the range of 1 to 10% of the transfer period in which the electric charge is held under the two gate electrodes G1 and G2 (or G2 and G3). 1%
Above, the falling timing of the pulse φG1 will not be earlier than the rising timing of the pulse φG3 due to the timing difference generated inside the element due to the variation of the gate capacitance or the like. If it is 10% or less, the increase in the transfer time due to the provision of the delay time Δt is small, and the charges can be transferred at substantially the same speed as in the second transfer method of the conventional example. In this embodiment, the delay time Δt corresponds to a period (diffusion period) in which charges are held over a depletion layer facing three adjacent transfer electrodes.

Next, at t = t4, the pulse φG2
And φG3 are at the H level and the other pulses are at the L level, and the electric charge under the transfer electrode G1 is transferred under the two transfer electrodes G2 and G3 by the fringe electric field (transfer period). ).

At t = t5, the pulses φG2 and φG4 change almost simultaneously. That is, after the pulse φG4 has risen to 50% of the H level, the pulse φG4
2 falls to 50% of the H level. The delay time Δt is
Delay time Δt between pulses φG1 and φG3 shown in FIG.
This is determined in consideration of a difference in timing that may occur inside an actual device due to a variation in gate capacitance or the like.

At t = t6, the pulses φG3 and φG4 are H
The level and other pulses are at the L level, and the electric charge under the electrode of the transfer electrode G2 is transferred under the electrodes of the two transfer electrodes G3 and G4 by the fringe electric field. Thereafter, similarly, charges are transferred rightward in FIGS. 4 to 6, and finally charges are output from the OS terminal.

The driving method of the charge transfer device of the present invention is not limited to the four-pole driven BCCD, but can be applied to a charge transfer device having another structure. The image sensor to which the driving method of the present invention is applied may be a two-dimensional sensor or a one-dimensional sensor.

[0030]

As described above, according to the present invention,
By providing a short diffusion period between the transfer period and the next transfer period, the charge in a shorter time than in the first driving method of the related art in which the transfer period and the diffusion period having the same length alternately occur. It is possible to provide a driving method that enables transfer and is less susceptible to a difference in pulse delay time caused by a variation in gate capacitance, which is a problem of the second driving method in the related art.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an electrode configuration of a transfer unit of a charge transfer device.

FIG. 2 is a diagram showing a potential distribution of a charge transfer device;

FIG. 3 is a diagram showing each driving pulse in a first conventional driving method.

FIG. 4 is a potential distribution diagram for explaining a charge transfer operation of the charge transfer device.

FIG. 5 is a potential distribution diagram for explaining a charge transfer operation of the charge transfer device.

FIG. 6 is a potential distribution diagram for explaining a charge transfer operation of the charge transfer device.

FIG. 7 is a diagram showing each driving pulse in a second conventional driving method.

FIG. 8 is a partially enlarged view of the driving pulse of FIG. 7;

FIG. 9 is a partially enlarged view of a driving pulse in the driving method of the present invention.

[Explanation of symbols]

 Reference Signs List 1 P-type substrate 2 n- buried layer 3 n + diffusion layer G1 to G4 transfer electrode IS input source electrode IG input gate electrode OG output gate electrode OS signal output electrode OD output drain electrode RG reset gate electrode

Claims (3)

[Claims] 1. A method of driving a charge transfer device in which charge transfer is performed by applying a predetermined pulse to transfer electrodes sequentially arranged in a charge transfer direction, wherein two or more number n of adjacent transfers are provided. When transferring the electric charge held over the depletion layer facing the electrode to the depletion layer opposing n adjacent transfer electrodes shifted by 1 or less than n by several m, the n transfer electrodes before the charge transfer And a state in which the charge is held across the depletion layer facing the n + m adjacent transfer electrodes including the n transfer electrodes after the charge transfer, and the charge is transferred across the depletion layer facing the n + m adjacent transfer electrodes. A method for driving a charge transfer device, wherein a retention period is set shorter than a period for retaining charges over a depletion layer facing the n adjacent transfer electrodes. 2. A four-phase transfer pulse is sequentially applied to the transfer electrode, and charges held over a depletion layer facing two adjacent transfer electrodes are opposed to two adjacent transfer electrodes shifted by one. When transferring to the depletion layer, the state where the charge is held across the depletion layer facing three adjacent transfer electrodes including two transfer electrodes before the charge transfer and two transfer electrodes after the charge transfer is interposed, 2. The electric charge according to claim 1, wherein a period for retaining electric charge over a depletion layer opposed to two adjacent transfer electrodes is set shorter than a period for retaining electric charge over a depletion layer opposed to the two adjacent transfer electrodes. A method for driving the transfer device. 3. A period for retaining charges over a depletion layer facing the (n + m) adjacent transfer electrodes is 1 to 10% of a period for retaining charges over a depletion layer facing the n adjacent transfer electrodes. 3. The method for driving a charge transfer device according to claim 1, wherein the charge transfer device is set within a range.