JPS61198677A - Charge transfer device - Google Patents

Abstract

PURPOSE:To enable uniform fat zero to be introduced into a two-phase CCD charge transfer device by implanting a charge QA' into the bits of each register by the so-called CCD transfer, and then pushing up the potential to cause excess charges to be emitted into the substrate, thereby making the remaining bias charges to fat zero. CONSTITUTION:A plurality of transfer electrodes 3 are arranged and formed along charge transfer direction (a) on one surface of a P-type silicon substrate 1 through a gate insulation film 2 composed of SiO2 or the like, whereby a CCD transfer portion also acting as a photo detector portion is constructed. The respective transfer electrodes 3 are alternately connected in common and applied with clock voltages phi1 and phi2, respectively. In order to introduce fat zero, within the vertical blanking period, a first gate voltage G1 and a second gate voltage G2 are simultaneously applied to a first input gate electrode 7 and a second input gate electrode 8, respectively, and a charge of a quantity somewhat greater than the quantity of the bias charge of fat zero is sequentially introduced from the diffusion layer of the input portion applied with an input voltage VIN to below the next electrode to receive light.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-phase CCD charge transfer device suitable for use in solid-state imaging devices.

In a frame transfer type surface channel type COD solid-state imaging device, it is possible to operate the device with high transfer efficiency by introducing a bias charge called a fat zero in order to reduce the influence of interface states. However, it is difficult to uniformly insert the phantom zeros into each bit of the image portion, and if the fant zeros are not uniformly inserted, linear fixed pattern noise appears. For this reason, a charge transfer device has been proposed, for example, as shown in FIG. 1, in which a diffusion layer is provided at the input and bias charges are electrically introduced therefrom. FIG. 1A shows an example of an image section of a frame transfer type solid-state image pickup device using a three-layer CCD. A plurality of transfer electrodes (3) are arranged in charge transfer direction a via a gate insulating film (2).
A transfer section that also serves as a light receiving area is constructed by being arranged along the lines, and every third transfer electrode (3) is commonly connected to each other to receive a three-phase transfer port 7 voltage φ1. φ2 and φ3 are applied, and an N-shaped diffusion layer (
4) is provided, and an input gate section is provided in which an input gate electrode (5) is formed between the input section and the transfer section with a gate insulating film (2) interposed therebetween. To introduce a bias charge called a fant zero, first turn on all the transfer electrodes (3) as shown in FIG.
More charge QA than necessary is injected from a given diffusion layer (4) under all the transfer electrodes (3).

Next, as shown in FIG. 1C, the transfer electrode (
3) (in this case, the electrode of φ2) is turned on to push up its potential well (6), and at the same time, the other electrodes of φ1. Push up the bottom of the transfer electrode (3) of φ3 to the accumulation potential. At this time, the transfer electrode of φ2 (3
), a charge QB corresponding to the difference between the on-level potential and the threshold potential vth is accumulated, and the excess charge is released into the substrate (1).
3) Make the lower potential deeper and start light reception hv. At this point, the bias charge QB accumulated under the transfer electrode (3) of φ2 becomes fat zero.

If such a measure is taken, the amount of fat zero is determined by the potential of the electrode of each bit in FIG. Even if there are variations, a uniform fat zero is introduced, and linear fixed pattern noise is not introduced. However, this method uses three-phase drive,
It can be used as a four-phase drive CCD charge transfer device, but two-phase drive CC where a step potential is formed with the same voltage
A DCC charge transfer device cannot be applied, because if the above operation is performed when bias charges are input, the maximum amount of charge that can be handled must be introduced into the register section once. That is, as shown in the potential distribution in Figure 2, in order to turn on the transfer electrodes (3) of φ1 and φ2 and inject the bias charge Q^, each bit of the register must be loaded with a charge greater than the maximum amount of charge that can be handled. It must be accumulated once.

Even in this way, it is possible to apply equal fat zeros to each bit by performing the operations shown in Figure 1 C and D.
In the frame transfer method, this extra charge leaks into the IiFM section, causing problems such as large noise.

In view of the above-mentioned points, the present invention provides a charge transfer device capable of introducing a uniform fat zero bias charge to each bit of each register, particularly in a two-phase CCD.

The present invention will be explained below with reference to the embodiment shown in FIG.

FIG. 3A shows an image part of a surface channel type solid-state imaging device using a frame transfer method using a two-phase CCD. A plurality of transfer electrodes (3) are arranged along the charge transfer direction a through a gate insulating film (2) made of 5i (h, etc.) on the − plane of the CCD which also serves as a light receiving part.
A transfer section is configured. Every other transfer electrode (31) is connected in common, and two-phase clock voltages φ1 and φ2 are applied to each transfer electrode. Note that below the transfer electrodes to which φ1 and φ2 are applied, there is a stepped potential along the transfer direction. For example, the gate insulating film (2) of the storage part and the transfer part is formed so that the storage part and the transfer part are formed.
It is possible to adopt a configuration in which the film thicknesses of the storage section and the transfer section are made different, or the impurity concentrations on the substrate surface in the storage section and the transfer section are made different from each other. On the other hand, the base (1) has a second
An input section is provided with a conductivity type, that is, an N-type diffusion layer (4), and a first manual gate electrode (7) and a second manual gate electrode are provided between the input section and the transfer section via a gate insulating film (2). (
8) is provided.

In order to introduce a fat zero in such a configuration, first, for example, a frame shift period Tpg (clock voltage φ1 is applied to each transfer electrode (3) in the vertical blanking period shown in FIG.
and φ2 are applied to transfer signal charges from the image section to the storage section), at the same time, the first input gate electrode (7) and the second manual gate electrode (8) are connected to the first input gate electrode (7) and the second manual gate electrode (8) at the timing shown in FIG. By applying the voltage G1 and the second gate voltage G2 and driving each transfer electrode (3) by φ1 and φ2, a fat zero bias is generated from the diffusion layer (4) of the input section to which the input voltage VINO is applied. A charge amount slightly larger than the charge amount is sequentially introduced under the next electrode to receive light.

To describe this operation in more detail, at time t1 in FIG. 5, as shown in FIG. 3B, charge q=a little more than the required bias charge amount is injected from the diffusion layer (4) into the area below the first manual gate. At time t2, charge QA' is accumulated under the first and second manual gates as shown in FIG. 3C. At this time, the amount of charge Qx to be injected is arbitrarily controlled by the relative potential between the input diffusion layer (4) and the second manual gate section. Next, at time t3, the first input gate section is turned off, and the charge Q is transferred to the lower part of the second manual gate (Fig. 3D), and then, through time t4 and t5, it is transferred to the next electrode to receive light, for example, φ1. Charge QA is transferred under electrode (3) (Fig. 3 E and F)
. Thereafter, this charge QX is sequentially transferred by clock voltages φ1 and φ2, and at the same time, the same amount of charge QX is sequentially injected from the input diffusion layer (4) under the transfer electrode (3) of φ1 where each light is to be received. (Figure 3G).

In this state, the amount of charge Q in each register varies due to variations in the surface potential of the input gate portion.

In this way, each bit of the image part has a predetermined charge Q
After injecting X, that is, the frame shift period TF in FIG.
In the period Ta after s, as shown in FIG. 3H, the transfer electrode of φ (
3) to push up the potential well (9) under this electrode, and at the same time push up the other φ2 transfer electrode (
3) A voltage is applied to bring the area under the electrode into an accumulation state, and the area under the electrode is pushed up to the accumulation potential.

At this time, an amount of charge QB corresponding to the difference between the on-level potential and the threshold voltage vth is accumulated under the transfer electrode (3) of φ1, and the excess charge is discharged into the base (1). 5
Entering the light receiving period TiN in the figure, the hotential well under the transfer electrode (3) of φ1 is further deepened and light receiving hν is started.

At this point, the bias charge QB accumulated under the transfer electrode (3) of φ1 becomes fat zero, and a signal charge Qsig corresponding to the amount of received light is accumulated in each potential well (FIG. 3I).

As described above, according to the present invention, the bias charges Q,
A larger amount of charge QX is injected into the bit of each register by so-called CCD transfer, and then the potential is pushed up to release the excess charge other than the required amount of bias charge QB into the substrate, and the remaining bias charge QB is fattened.・By using it as a zero, it is possible to introduce uniform fat zeros to the bits of each register in the two-phase CCD charge transfer device as well as in the three-phase and four-phase CCD @ charge transfer devices. This method does not cause any inconvenience such as noise, and is therefore suitable for application to, for example, a frame transfer type two-phase CCD solid-state image pickup device.

Furthermore, on the upper side, the charge QX is injected during the frame shift period TF5.
1, but it can also be performed after the frame shift period as long as it is within the vertical blanking period.

[Brief explanation of the drawing]

1A to 1D are potential change diagrams when fat zero is introduced, showing an example of a conventional three-phase CCD charge transfer device, FIG. 2 is a potential diagram of a two-phase CCD charge transfer device used to explain the present invention, and FIG. FIG. A-1 is a potential change diagram when fat zero is introduced, showing an example of a two-phase CCD charge transfer device according to the present invention, FIG. 4 is a diagram showing an operation period used to explain the present invention, and FIG. FIG. 3 is a drive pulse waveform diagram of FIG. (1) is the semiconductor substrate, (2) is the gate insulating film, (3) is the transfer electrode, (4) is the input diffusion layer, (5), (7), (
8) is an input gate electrode. Figure 1 Figure 2 Figure 5 Winter map

Claims (1)

[Claims] In a two-phase CCD charge transfer device having an input section and a transfer section, an electrode on the transfer section is driven with a charge amount slightly larger than a predetermined bias charge amount determined by a potential applied to the input section. introduced under the first phase electrode in the electrode,
A predetermined potential is applied to the first phase electrode, and a potential is applied to the electrodes other than the first phase so that the bottom of the electrode becomes in an accumulation state, and the predetermined bias charge amount is applied from below the first phase electrode. A charge transfer device characterized in that a predetermined bias charge is introduced under the first phase electrode by discharging charges other than that into the substrate.