JP2870046B2 - Charge-coupled device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a charge-coupled device, and more particularly, to a charge-coupled device using a floating diffusion method as a charge detection means.

[Prior Art] FIGS. 3 (a) and 3 (b) show a plan view of a conventional charge transfer device (hereinafter referred to as a CCD) of this type and a cross-sectional view taken along the line XY of the device. This is an example in which a CCD is used for a horizontal CCD of an interline transfer type solid-state imaging device.
CD is used.

As shown in FIGS. 3A and 3B, a channel region 1 of a horizontal CCD is provided on a semiconductor substrate 11, and a channel region 2 of a vertical CCD is provided at an appropriate position in the channel region 1. Is connected. A floating diffusion layer 8 and a reset drain 10 are provided after the channel region 1. On the channel region 1, a storage gate electrode 3, a barrier gate electrode 4, a final storage gate electrode 5, and a final barrier gate electrode 6 are provided via a gate insulating film.
An output gate 7 is provided on a final portion of the channel region 1 via a gate insulating film. In addition, a reset gate 9 is provided on the substrate between the floating diffusion layer 8 and the reset drain 10. The storage gate electrodes 3, 5 are connected to the right barrier gate electrodes 4, 6, respectively, and operate as one transfer electrode. In this specification, the storage electrode gate means a transfer electrode capable of temporarily storing signal charges under the electrode, or a charge storage portion of the transfer electrode.

Therefore, when designing such a CCD, it is necessary to ensure that a sufficiently large accelerating electric field is formed under each storage gate electrode and that there is no difference in the amount of charge stored under each gate electrode. Is taken into account. On the other hand, the area of the floating diffusion layer is made as small as possible in order to increase the output voltage and the signal-to-charge ratio.
Due to the small area of the floating diffusion layer, the width of the channel region is gradually reduced in front of the channel region. Then, in that case, as described above, consideration is made so as not to cause a difference in the amount of storable charge under each storage gate electrode, so that the area of each storage gate electrode on the channel region is substantially the same. Is made. As a result, the gate length L ₁ of the last stage storage gate electrode 5 is set longer than the other storage gate electrode 3, for example, that of the final stage when the gate length L ₂ of the storage gate electrode 3 is 5μm is 9 μm
Is made.

[Problems to be Solved by the Invention] In recent years, in particular, it has been required to lower the driving voltage of a solid-state imaging device. For example, a low-voltage power supply of, for example, about 5 V has been used. The charge accelerating electric field tends to decrease. In particular, in the final gate, a DC potential at an intermediate level of the pulse amplitude of the CCD is often applied to the output gate, so that the electric field in that portion is much weaker than the electric field in other CCD gates.

In addition, in the above-described conventional CCD, since the gate length of the last-stage storage gate electrode is made longer, the potential difference between the output gate and the lower portion becomes smaller, so that the electric charge is transferred to the next stage within a predetermined time. It is becoming difficult to transfer data, which causes a decrease in transfer efficiency. As a result, for example, in a solid-state imaging device, there is a problem in that the degree of color modulation is reduced and sensitivity is insufficient at low illuminance.

FIG. 4 is a diagram showing the dependence of the degree of color modulation on the gate length L of the last-stage storage gate electrode when the output voltage is 500 mV in a two-dimensional solid-state imaging device having 510 horizontal pixels, and FIG. FIG. ₁₄ is a diagram showing output dependency on a gate length L at the time of low illuminance of 5 _Lux using the same image sensor. These are data when the drive voltage is 5 V and the normal channel width is 30 μm. As is clear from FIGS. 4 and 5, the gate length L of the final storage gate electrode is 9 μm.
When the ratio exceeds 1, that is, when the area ratio of the storage gate electrode exceeds 1, the degree of color modulation and the output decrease due to a decrease in transfer efficiency.

[Means for Solving the Problems] The CCD of the present invention has a plurality of storage gate electrodes on a charge transfer region (channel region) and uses a floating diffusion method for an output mechanism. The width gradually decreases toward the floating diffusion layer near the terminal end, and the area of the last storage gate electrode on the charge transfer region is 0.6 to less than the area of the other storage gate electrode on the charge transfer region. It has been made 0.9 times.

[Operation] In FIGS. 4 and 5, the color modulation degree and the output do not decrease because the gate length of the final storage gate electrode is 8.75.
The area on the channel region is 0.9 μm or less of that of the other storage gate electrodes. That is, a driving voltage of 5 V and a general storage gate electrode length of 5
In the case of μm, good transfer efficiency can be obtained when the area ratio of the final storage gate electrode to the other gate electrode is 1 or less, more preferably 0.9 or less.

By the way, as described above, each storage gate electrode has such a gate length that a large accelerating electric field can be obtained even at a low voltage. Therefore, when the drive voltage is reduced, it is necessary to further shorten the gate length. Since the effect of lowering the driving voltage acts equally on the general storage gate electrode and the final gate electrode, when the gate length of the general storage gate electrode is reduced, the final gate The gate length of the electrode may be shortened in proportion to it. According to the simulation results of the present inventors, even when the drive power supply voltage and the gate length of the storage gate electrode are changed, the area ratio between the final-stage storage gate electrode and the other storage gate electrode is 0.9 times or less. Sometimes it was found that good transfer efficiency could be ensured.

Note that the lower limit of the area ratio is desirably 0.6 or more from the viewpoint of preventing a decrease in the charge storage capacity of the final-stage gate electrode.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing an embodiment of the present invention. 3, the same reference numerals are given to the portions corresponding to those of the conventional example shown in FIG. 3, and the duplicate description is omitted. In this embodiment, the gate length L of the last-stage storage gate electrode 5 is shown. ₁ is set to 7 μm. Here, since the gate length L ₂ of the other storage gate electrode 3 is at 5 [mu] m, in this case the gate length ratio has a 1.4 (gate area ratio is 0.7).

FIG. 2 is a plan view showing another embodiment of the present invention.
In this embodiment, the gate length of the last-stage storage gate electrode 5 is 7 μm, but the channel region is not narrowed at a constant rate as in the previous embodiment, but is narrowed in two stages. Has been Therefore, the gate length ratio is 1.4
Although this is not different from the previous embodiment, the gate area ratio has increased to 0.75. According to this embodiment, since the amount of charge that can be stored can be increased without increasing the gate length, higher transfer efficiency can be realized.

In the above embodiment, the transfer electrode is divided into the storage gate electrode and the barrier gate electrode. However, a transfer electrode in which these are integrated may be used. In this case, as pointed out earlier, in this specification, a portion of the transfer electrode where signal charges are temporarily stored is referred to as a storage gate electrode.

In addition, the present invention can be applied to a CCD driven by a clock having three or more phases. In this case, when no barrier is provided under each transfer electrode, each transfer electrode
When a barrier is provided, a portion of each transfer electrode where the barrier is not provided becomes a storage gate electrode.

[Effects of the Invention] As described above, in the present invention, the area of the final-stage storage gate electrode is made smaller than that of the other storage gate electrodes, instead of making the amount of stored charge under each storage gate electrode uniform as in the conventional example. According to the present invention, high transfer efficiency can be realized in the final stage even in a CCD driven at a low voltage. Therefore, when the CCD according to the present invention is used for a solid-state imaging device, insufficient sensitivity can be prevented and a high degree of color modulation can be obtained.

[Brief description of the drawings]

1 and 2 are plan views each showing an embodiment of the present invention, FIG. 3 (a) is a plan view showing a conventional example, and FIG. 3 (b) is a sectional view taken along line XY of FIG. 4 and 5 are characteristic curve diagrams for explaining the characteristics of the conventional example and the present invention. 1, 2, ... channel region, 3 ... storage gate electrode, 4 ...
... barrier gate electrode, 5 ... final stage storage gate electrode, 6 ...
... last stage barrier gate electrode, 7 ... output gate, 8 ... floating diffusion layer, 9 ... reset gate, 10 ... reset drain, 11 ... semiconductor substrate.

Claims (1)

(57) [Claims] A charge transfer region formed in a surface region of the semiconductor substrate; a floating diffusion layer formed in a surface region of the semiconductor substrate subsequent to the charge transfer region and reset to a constant potential at regular intervals; It has a plurality of storage gate electrodes disposed on the charge transfer region via an insulating film, and an output gate maintained at a constant potential disposed on the last portion of the charge transfer region via an insulating film. In the charge-coupled device, the width of the charge transfer region gradually decreases toward the floating diffusion layer near the terminal end, and the last one of the storage gate electrodes has an area on the charge transfer region. Is 0.6 to 0.9 times the area of the other storage gate electrode on the charge transfer region.