JP3788027B2 - Driving method of charge transfer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method of a charge transfer device used as a solid-state imaging device (image sensor) in an integrated video camera, for example.
[0002]
[Prior art]
FIG. 1 is a sectional view of a buried channel charge coupled device (BCCD) used in a conventional driving method, and FIG. 9 shows the potential distribution thereof. In FIG. 1, 1 is a P-type substrate, 2 is an n ⁻ buried layer as a buried charge transfer section, 3 is an n ⁺ diffusion layer as a charge detection section, IS is an input source electrode for setting a charge injection potential, IG Is an input gate electrode for controlling the charge injection amount, G1 to G4 are transfer electrodes for controlling charge transfer by a four-phase clock, OG is an output gate electrode for applying a predetermined DC voltage, and OS converts a signal charge Q into a voltage V OD is an output drain electrode that applies a predetermined DC voltage as a reference potential setting unit, and RG is a reset switch unit that is connected to the n ⁺ diffusion layer 3 to which a reset signal charge is connected to the signal output electrode OS. reset gate electrode to a voltage set by connecting to a DC voltage set the n ⁺ diffusion layer 3 at the output drain electrode OD immediately before being transferred, 4 electric signal output electrode OS Amplifier unit for impedance conversion, VO represents an output terminal of the amplifier unit 4, respectively.
[0003]
A DC power supply of 2 volts is applied to the output gate electrode OG. A DC power supply having a voltage (for example, 10 volts) or more that depletes the channel is applied to the output drain electrode OD and the input source electrode IS. The channel depletion potential when 0 volt is applied to the gate electrodes G1 to G4 is indicated by a thick solid line in the potential distribution of FIG. Actually, the voltages applied to G1 to G4, IG and RG are the pulse waveforms shown in FIG. 10, and the H level is 10V and the L level is 0V. In FIG. 10, pulses φG1, φG2, φG3 and φG4 are signals applied to the transfer electrodes G1, G2, G3 and G4, φIG is a signal applied to the input gate electrode IG, and φRG is applied to the reset gate electrode RG. Each signal is shown.
[0004]
The operation of the BCCD configured as described above will be described with reference to the drive timing chart of FIG. 10 and the potential distributions at that time shown in FIGS. First, at time t = t1, the pulses φG1, φG2, and φIG are at the H level, the other pulses are at the L level, and charges are injected. Next, at t = t2, the pulse φIG becomes L level. Next, at t = t3, the pulses φG1, φG2, and φG3 are at the H level and the other pulses are at the L level, and the charges are diffused for three gates (this period is called a diffusion period). Next, at t = t4, the pulses φG2 and φG3 are at the H level and the other pulses are at the L level, and the electric charge under the transfer electrode G1 is transferred to the two gates of the transfer electrodes G2 and G3 by the fringe electric field (this period) Is called the transfer period). Next, at t = t5, the pulses φG2, φG3, and φG4 are at the H level and the other pulses are at the L level, and the charge enters the diffusion period again, and is diffused over the three gates of the electrodes φG2, φG3, and φG4. Thereafter, the charges are transferred by repeating the diffusion period and the transfer period from t = t6 to t14, the output is selected from the signal output electrode OS, and then output from the output terminal VO via the amplifier 4. Next, at t = t15, the reset gate electrode RG becomes H level and the charge is reset.
[0005]
[Problems to be solved by the invention]
However, with the increase in the number of pixels of the image sensor, it is desired to widen the output amplifier. However, in the conventional method for driving a charge transfer device, the frequency characteristics of the output amplifier cannot be predicted from the rising or falling edge of the signal. There is a problem that accurate measurement is not possible.
[0006]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a driving method of a charge transfer device capable of measuring the frequency characteristics of an amplifier.
[0007]
[Means for Solving the Problems]
The charge transfer device driving method of the present invention includes a charge transfer unit, a charge detection unit that detects charges transferred from the charge transfer unit, an amplifier unit that converts impedance of the potential of the charge detection unit, and a charge detection unit A charge transfer device driving method comprising a reference potential setting unit for setting a potential of a charge transfer device and a reset switch unit for connecting the charge detection unit and the reference potential setting unit for each cycle. An AC signal is input.
[0008]
In the charge transfer device driving method according to the present invention, it is preferable that the AC signal is constituted by a rectangular wave.
[0009]
According to this configuration, the frequency characteristics of the amplifier of the charge transfer device can be accurately measured.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred first embodiment of the present invention will be described with reference to the drawings.
[0011]
The charge transfer device driving method of the present invention will be described with reference to FIGS. In this operation, a DC power supply of 2 volts is applied to the output gate electrode OG. A DC power supply having a voltage (for example, 10 volts) or more that depletes the channel is applied to the output drain electrode OD and the input source electrode IS. The channel depletion potential when 0 volt is applied to the gate electrodes G1 to G4 is indicated by a thick solid line in the potential distribution of FIG. Actually, the voltage applied to the output drain electrode OD is the DC voltage, pulse waveform, and output waveform shown in FIG. The pulse φOD has an H level of 15V and an L level of 10V. Otherwise, the pulse φOD has an H level of 10V and an L level of 0V. In FIG. 3, pulses φG1, φG2, φG3 and φG4 are signals applied to the transfer electrodes G1, G2, G3 and G4, φIG is a signal applied to the input gate electrode IG, and φRG is applied to the reset gate electrode RG. , ΦOS indicates a signal output waveform, and φVO indicates a signal waveform that has passed through the amplifier 4.
[0012]
First, at time t = t1, the pulse φOD becomes H level and 15V is applied to RG, so that the H level (15V) of the pulse φOD is connected to the signal output electrode OS. Thereafter, the signal whose impedance is converted by the amplifier 4 is output from the output terminal VO. Next, at t = t2, the pulse φOD becomes L level, and 15V is applied to RG, so that the L level (10V) of the pulse φOD is connected to the signal output electrode OS. Thereafter, the signal whose impedance is converted by the amplifier 4 is output from the output terminal VO. Since the waveform output from the output terminal VO at this time is a result of multiplying the pulse φOD by α, the gain of the amplifier 4 can be easily evaluated only by measuring the amplitude.
[0013]
Hereinafter, a second preferred embodiment of the present invention will be described with reference to the drawings.
The method for driving the charge transfer device of the present invention will be described with reference to FIGS. The difference from the first embodiment is that a clamp part and a sample hold part are added after the output terminal VO. In this operation, a DC power supply of 2 volts is applied to the output gate electrode OG. The output diode electrode OD and the input source electrode IS are applied with a DC power supply having a voltage (for example, 10 volts) or more at which the channel is depleted. The channel depletion potential when 0 volt is applied to the gate electrodes G1 to G4 is also shown by a thick solid line in the potential distribution of FIG. Actually, the voltage applied to the output drain electrode OD is the DC voltage, the pulse waveform, and the output waveform shown in FIG. The pulse φOD has an H level of 15V and an L level of 10V. Otherwise, the pulse φOD has an H level of 10V and an L level of 0V. In FIG. 5, φG1, φG2, φG3, and φG4 are signals applied to the transfer electrodes G1, G2, G3, and G4, φIG is a signal applied to the input gate electrode IG, and φRG is applied to the reset gate electrode RG. The signal, φOS indicates a signal output waveform, φVO is a signal waveform that has passed through the amplifier 4, φSC is a pulse applied to the switch SC of the clamp unit, and the switch SC is turned on when it is at H level. A pulse φSS is a pulse applied to the switch SS of the sample hold unit, and indicates that the switch SS is turned on when it is at the H level.
[0014]
First, at time t = t1, the pulse φOD becomes H level and 15V is applied to RG, so that the H level (15V) of the pulse φOD is connected to the signal output electrode OS. Thereafter, the signal whose impedance is converted by the amplifier 4 is output from the output terminal VO. Next, the pulse φSC becomes H level, the switch SC is turned ON, and the clamp voltage EC is charged in the clamp capacitor CC. Next, at t = t2, the pulse φSC becomes L level, the switch SC is turned OFF, the pulse φSS becomes H level, the switch SS is turned ON, and the signal is held in the sample hold capacitor CS, and at the same time, the sample hold. A signal at this timing is output from the output SHO. Next, at t = t3, the pulse φSS becomes the H level for the second time, the switch SS is turned on, a signal is held in the sample hold capacitor CS, and at the same time, a signal at this timing is output from the sample hold output SHO. Next, at t = t4, the pulse φSS becomes the third H level, the switch SS is turned on, the signal is held in the sample hold capacitor CS, and at the same time, the signal at this timing is output from the sample hold output SHO. At this time, since the input signal pulse φOD is output at the L level (10 V), the waveform output from the output terminal VO is moving toward the L level. It takes time. Next, at t = t5, the pulse φSS becomes the H level for the fourth time, the switch SS is turned on, the signal is held in the sample hold capacitor CS, and at the same time, a signal at this timing is output from the sample hold output SHO. Similarly, repeat until t = t8. The waveform output from the sample-and-hold output SHO at this time can be observed, the falling characteristics of the pulse can be evaluated, and the frequency characteristics can be evaluated. In addition, it goes without saying that the rising characteristics can be similarly evaluated.
[0015]
Hereinafter, a third preferred embodiment of the present invention will be described with reference to the drawings. The method for driving the charge transfer device of the present invention will be described with reference to FIGS. This method is effective when the output drain electrode OD is connected to the power supply terminal of the entire charge transfer device and a pulse cannot be input to the output drain electrode OD.
[0016]
In this operation, a DC power supply of 2 volts is applied to the output gate electrode OG. A DC power supply having a voltage (for example, 10 volts) or more that depletes the channel is applied to the output drain electrode OD and the input source electrode IS. The channel depletion potential when 10 volts is applied to the gate electrodes G1 to G4 is indicated by a thick solid line in the potential distribution of FIG. Actually, the voltage applied to each terminal is the DC voltage, pulse waveform, and output waveform shown in FIG. The pulse φIS has an H level of 15V and an L level of 10V. Otherwise, the pulse φIS has an H level of 10V and an L level of 0V. In FIG. 7, pulses φG1, φG2, φG3, and φG4 are signals applied to the transfer electrodes G1, G2, G3, and G4, a pulse φIG is applied to the input gate electrode IG, and a pulse φRG is applied to the reset gate electrode RG. An applied signal, pulse φOS, indicates a signal output waveform, and pulse φVO indicates a signal waveform that has passed through the amplifier 4.
[0017]
First, at time t = t1, the pulse φIS becomes H level, and 10V is applied to IG, so that the H level (15V) of the pulse φIS is connected to the signal output electrode OS. Thereafter, the signal whose impedance is converted by the amplifier 4 is output from the output terminal VO. Next, at t = t2, the pulse φIS becomes L level and 10 V is applied to the input gate electrode IG, so that the L level (10 V) of the pulse φIS is connected to the signal output electrode OS. Thereafter, the signal whose impedance is converted by the amplifier 4 is output from the output terminal VO. Since the waveform output from the output terminal VO at this time is a result of multiplying the pulse φIS by α, the gain of the amplifier 4 can be easily evaluated only by measuring the amplitude. The difference from the first embodiment is that an input pulse is applied from the input source electrode IS.
[0018]
Hereinafter, a fourth preferred embodiment of the present invention will be described with reference to the drawings. A method for driving the charge transfer device of the present invention will be described with reference to FIGS. The difference from the second embodiment is that an input pulse is applied from the input source electrode IS. This method is effective when the output drain electrode OD is connected to the power supply terminal of the entire charge transfer device and a pulse cannot be input to the output drain electrode OD.
[0019]
In this operation, a DC power supply of 2 volts is applied to the output gate electrode OG. A DC power supply having a voltage (for example, 10 volts) or more that depletes the channel is applied to the output drain electrode OD and the input source electrode IS. The channel depletion potential when 10 volts is applied to the gate electrodes G1 to G4 is indicated by a thick solid line in the potential distribution of FIG. Actually, the voltage applied to each terminal is the DC voltage, pulse waveform and output waveform shown in FIG. The pulse φIS has an H level of 15V and an L level of 10V. Otherwise, the pulse φIS has an H level of 10V and an L level of 0V. In FIG. 8, pulses φG1, φG2, φG3 and φG4 are signals applied to the transfer electrodes G1, G2, G3 and G4, a pulse φIG is a signal applied to the input gate electrode IG, and a pulse φRG is applied to the reset gate electrode RG. The applied signal, pulse φOS, indicates a signal output waveform, the pulse φVO is a signal waveform that has passed through the amplifier 4, and the pulse φSC is a pulse that is applied to the switch SC of the clamp unit. A pulse φSS is a pulse applied to the switch SS of the sample hold unit, and indicates that the switch SS is turned on when it is at the H level.
[0020]
First, at time t = t1, the pulse φIS becomes H level, and 15 V is applied to the input gate electrode IG, so that the H level (15 V) of the pulse φIS is connected to the signal output electrode OS. Thereafter, the signal whose impedance is converted by the amplifier 4 is output from the output terminal VO. Next, the pulse φSC becomes H level, the switch SC is turned ON, and the clamp voltage EC is charged in the clamp capacitor CC. Next, at t = t2, the pulse φSC becomes L level, and the switch SC is turned OFF. Further, the pulse φSS becomes H level, the switch SS is turned ON, and a signal is held in the sample hold capacitor CS. At the same time, a signal at this timing is output from the sample hold output SHO. Next, at t = t3, the pulse φSS becomes the H level for the second time, the switch SS is turned on, a signal is held in the sample hold capacitor CS, and at the same time, a signal at this timing is output from the sample hold output SHO. Next, at t = t4, the pulse φSS becomes the third H level, the switch SS is turned on, the signal is held in the sample hold capacitor CS, and at the same time, the signal at this timing is output from the sample hold output SHO. At this time, since the input signal pulse φIS is output at the L level (10 V), the waveform output from the output terminal VO is moving toward the L level. It takes time. Next, at t = t5, the pulse φSS becomes the H level for the fourth time, the switch SS is turned on, the signal is held in the sample hold capacitor CS, and at the same time, a signal at this timing is output from the sample hold output SHO. Similarly, repeat until t = t8. The waveform output from the SHO terminal at this time can be observed, the falling characteristics of the pulse can be evaluated, and the frequency characteristics can be evaluated. In addition, it goes without saying that the rising characteristics can be similarly evaluated.
[0021]
The image sensor to which the driving method of the charge transfer device of the present invention is applied may be a two-dimensional one or a one-dimensional one.
[0022]
【The invention's effect】
As described above, according to the method for driving a charge transfer device of the present invention, basic characteristics such as amplifier gain and frequency characteristics can be evaluated in a short time.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an electrode configuration of a transfer unit of a charge transfer device in a conventional driving method and driving methods of first and third embodiments of the present invention. FIG. 3 is a diagram showing the potential distribution of the charge transfer device in the driving method of the second embodiment. FIG. 3 is a diagram showing driving pulses in the driving method of the first embodiment of the invention. Sectional drawing which shows the electrode structure of the transfer part of the charge transfer apparatus in the driving method of 2 and 4th Embodiment. FIG. 5 is a figure which shows each drive pulse in the driving method of the 2nd Embodiment of this invention. 6 is a diagram showing the potential distribution of the charge transfer device in the driving method according to the third and fourth embodiments of the present invention. FIG. 7 is a diagram showing each driving pulse in the driving method according to the third embodiment of the present invention. FIG. 8 shows the drive of the fourth embodiment of the present invention. FIG. 9 is a diagram showing the potential distribution of the charge transfer device in the conventional driving method. FIG. 10 is a diagram showing each drive pulse in the conventional driving method. FIG. 12 is a potential distribution diagram for explaining the charge transfer operation of the charge transfer device. FIG. 13 is a potential distribution diagram for explaining the charge transfer operation of the charge transfer device. Explanation of]
1 P-type substrate 2 n ⁻ buried layer 3 n ⁺ diffusion layer 4 amplifiers G1 to G4 transfer electrode IS input source electrode IG input gate electrode OG output gate electrode OS signal output electrode OD output drain electrode RG reset gate electrode VO output terminal

Claims (5)

  A charge transfer unit, a charge detection unit that detects charges transferred from the charge transfer unit, an amplifier unit that converts impedance of the potential of the charge detection unit, and a reference potential setting that sets a potential of the charge detection unit And a reset switch unit that connects the charge detection unit and the reference potential setting unit every cycle, wherein an AC signal is input to the reference potential setting unit A method for driving a charge transfer device. The charge transfer device further includes a clamp unit that clamps a signal output from the amplifier unit at a predetermined timing, and a sample hold unit that samples and holds the signal output from the clamp unit a plurality of times at a predetermined timing. The method of driving a charge transfer device according to claim 1. A charge transfer unit; a charge detection unit that detects charges transferred from the charge transfer unit; an amplifier unit that converts impedance of the potential of the charge detection unit; and a reference potential setting that sets a potential of the charge detection unit And a reset switch for connecting the charge detection unit and the reference potential setting unit for each cycle, the input unit for setting the potential of the input unit of the charge transfer unit located on the opposite side of the reference potential setting unit A method for driving a charge transfer device comprising: a charge transfer device, wherein an AC signal is input to the input portion in a state where a constant voltage is applied to the charge transfer portion . A charge transfer unit; a charge detection unit that detects charges transferred from the charge transfer unit; an amplifier unit that converts impedance of the potential of the charge detection unit; and a reference potential setting that sets a potential of the charge detection unit And a reset switch for connecting the charge detection unit and the reference potential setting unit for each cycle, the input unit for setting the potential of the input unit of the charge transfer unit located on the opposite side of the reference potential setting unit Unit, a clamp unit that clamps the signal output from the amplifier unit at a predetermined timing, and a sample hold unit that samples and holds the signal output from the clamp unit a plurality of times at a predetermined timing The method of driving a charge transfer device according to claim 1, wherein an AC signal is input to the input unit in a state where a constant voltage is applied to the charge transfer unit.   5. The method for driving a charge transfer device according to claim 1, wherein the AC signal is constituted by a rectangular wave.

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