JPH055434B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an output circuit of a charge transfer device, and specifically relates to reducing noise in an output section of a charge transfer device.

BACKGROUND ART In a charge transfer device applied to an imaging device using a charge-coupled device (hereinafter referred to as CCD), a charge transfer device is used to finally accumulate transferred signal charges and read out a voltage corresponding to the signal charges. A diffusion capacitance is formed on the substrate that constitutes the CCD. In order to accurately detect the signal charge, this diffusion capacitor is periodically reset to a predetermined potential just before the signal charge is transferred to the diffusion capacitor. The potential in the diffusion capacitance of the CCD, in other words, the output voltage level of the CCD changes.

In order to eliminate the influence of thermal noise generated during such a reset operation, a correlated double sampling circuit is generally used in the output circuit of the charge transfer device. As is well known, the correlated double sampling circuit is
For example, by holding the signal output obtained from the diffused capacitance of a charge transfer device in a capacitor that has just been clamped to a predetermined potential level, and later sampling and holding this voltage, the zero level can be subtracted from the signal output. It is possible to obtain signal components that are Therefore, the final signal output does not include noise components due to zero level fluctuations.

This sampling circuit typically samples the signal voltage using a sampling pulse. However, since this sampling pulse has steep rises and falls, spike noise is superimposed on the sampled signal voltage corresponding to the rises and falls of the sampling pulse.

Conventionally, therefore, a low-pass filter was connected to the output of the correlated double sampling circuit, thereby removing spike noise in the signal voltage.

However, in general, filter circuits are difficult to integrate into integrated circuits, so they are not compatible with integrated circuit CCDs, and if the above-mentioned low-pass filter is used in the output section of a charge transfer device, the charge transfer device will become larger. There is a problem.

Furthermore, when a low-pass filter is used to remove spikes, it blocks high-frequency components of the signal components, so when a charge transfer device is used in an image pickup device, for example, there is a problem that the resolution of the image decreases. Ta.

Purpose The present invention solves the drawbacks of the prior art,
It is an object of the present invention to provide an output circuit for a charge transfer device that can remove spikes generated during sampling operations from signal components without using a low-pass filter.

DISCLOSURE OF THE INVENTION According to the present invention, a charge transfer device including a charge transfer path, storage means for receiving and accumulating signal charges transferred from the charge transfer path, and reset means for resetting the storage means to a predetermined potential. , an output circuit of a charge transfer device that takes out an output according to a signal charge includes a clamping means that temporarily clamps the output of the storage means to a predetermined voltage, and a first circuit that samples and holds the output of the storage means after clamping. a second sample and hold means for sampling and holding a predetermined electrically fixed signal in synchronization with the first sample and hold means; and calculation means for outputting a signal according to the difference.

According to the present invention, signal charges are transferred from a charge transfer device having a charge transfer path, an accumulation means for receiving and accumulating signal charges transferred from the charge transfer path, and a reset means for resetting the accumulation means to a predetermined potential. The output circuit of the charge transfer device that takes out an output according to the output includes a means for temporarily clamping the output of the storage means to a predetermined potential, and a means for receiving the output of the clamping means and outputting signals in the positive and negative phases of this output. circuit means for sampling and holding the positive-phase output signal of the circuit means after the clamping; The second sample and hold means samples and holds the output signal of the second sample and hold means, and the calculation means outputs a signal corresponding to the difference between the outputs of the first and second sample and hold means.

DESCRIPTION OF EMBODIMENTS Next, embodiments of an output circuit of a charge transfer device according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, a P-type silicon substrate 12
An array of gate electrodes 11 is formed on the main surface of the substrate, thereby configuring, for example, a two-phase drive CCD transfer path. Near its termination, an N-type diffusion region 14 is formed, which is connected to an amplifier 20 by a connecting line 15.

The diffusion region 14 has a capacitance C _D and also has a reset gate 18 formed on the surface of the substrate 12.
and N formed near the surface of the substrate 12.
Reset transistor by type diffusion region 16
It constitutes TR. Area 16 is a predetermined reference voltage
It is connected to a power supply 22 having V _R .

When horizontal transfer pulses φH1 and φH2 are applied to each gate electrode 11 at the timing shown in FIG. The electrodes Q are sequentially transferred and finally accumulated in the diffusion capacitance C _D by the diffusion layer 14. This charge Q is taken out via the buffer amplifier 20 as the CCD signal power V _OS .

Immediately before the signal charge is transferred to the diffusion amount C _D ,
For example, at time _t1 , the reset pulse φRS is applied to the gate 18.
(Figure 3c). As a result, the diffusion capacitance 14 is connected to the other N-type diffusion layer 16 by the channel formed by the gate 18, through which the reset voltage V _R is applied by the reset power supply 22.
will be reset to the level of The output voltage V _OS of the CCD at this time varies from time t ₁ to t ₂ as shown in Fig. 3d.
The waveform has a superimposed thermal noise NT caused by the gate 18 acting as a resistor when it is in the ON state.

Therefore, the output voltage V _OS between time t ₂ and _{t 4} is
The reset pulse φRS whose level fluctuates due to the influence of thermal noise varies depending on the value at the falling time _t2 , and the level between time _t5 and _t6 after the transfer of the signal charge to the diffusion capacitor 14 is completed accordingly. output voltage
The level of V _OS will also fluctuate. In order to eliminate the influence of thermal noise caused by such a reset operation, a technique called a correlated double sampling method is known.

The present invention eliminates the spike noise inherent in this correlated double sampling method without using a conventionally used low-pass filter, and an embodiment thereof is shown in FIG. In the same figure,
An output 30 of the buffer amplifier 20 (FIG. 2) is connected to a clamp circuit 32 via a clamp capacitor C _c . The clamp circuit 32 is a circuit that, after resetting the diffusion capacitance 14, temporarily clamps the capacitor C _c to a predetermined level in response to the clamp pulse φCP.

The output 33 of the clamp circuit 32 is connected to a first sample and hold circuit 34 and the output 35 of the latter
is grounded via the hold capacitor C _H1 on the one hand, and connected to the non-inverting input (+) of the differential amplifier 54 on the other hand. The sample and hold circuit 34 is a circuit that samples the voltage of the input 33 in response to the sampling pulse φSP and holds it in the capacitor C _H1 .

The inverting input (-) 55 of the differential amplifier 54 has a second
sampling circuit 50 is connected, which is the first
It has substantially the same configuration as the sampling circuit 34 of , and is supplied with the same sampling pulse φSP.
However, a predetermined voltage VK is fixedly supplied to the input 51 by a power supply 52. The inverting input 55 is also connected to ground via a capacitor C _H2 which is substantially the same as capacitor C _H1 . The differential amplifier 54 is an arithmetic circuit that outputs a voltage corresponding to the difference between the two inputs 35 and 55 to the output 56.

By the way, the signal output _VOS of the CCD is inputted from the terminal 30, and the clamping capacitor _Cc is set to a predetermined level by the clamp pulse φCP outputted at the timing shown in FIG. 3e, that is, immediately after the diffusion capacitance _CD is reset. The CCD signal voltage V _OS (zero level) at reset is clamped to a constant voltage.

Thereafter, the horizontal transfer pulses φH1 and φH2 start transferring the signal charges from the horizontal transfer path to the diffusion capacitor C _D. When the transfer operation is completed, for example within the period from time t ₅ to time t ₆ in FIG. 3, the sampling pulse φSP is input to the sample hold circuit 34, and the sampling operation of the signal voltage V _OS is performed. For example, the signal voltage at this time
When V _OS shows a change as shown in Figure 4 a, the signal voltage V _OS is sampled by the sampling pulse φSP output at the timing shown in Figure 4 b, and each sampling pulse _is It is held at the falling edge of (FIG. 4c). At this time, when the signal voltage V _OS is sampled as shown in FIG. 4c, spikes 100 and 102 are superimposed on the output voltage V _H1 of the sample and hold circuit 34 at the rising and falling points of the sampling pulse. In the conventional circuit, this spike was removed by a low-pass filter that removes the low-frequency components of the output signal of the sample-and-hold circuit 34.

In this embodiment, such a low-pass filter is not used, and the sample-hold circuit 34 and capacitor are used.
a second sample-and-hold circuit 50 and a capacitor C _H2 each having substantially the same circuit characteristics as C _H1 ;
, the two sample and hold circuits 34 and 50 generate substantially similar spike noises, and the differential amplifier 54 cancels out the spike noises of both.

More specifically, the first sample and hold circuit 3
At the same timing as the sampling in step 4, the sample and hold circuit 50 samples the voltage V K from the fixed power supply 52, and the voltage V _K from the fixed power supply 52 is sampled by the sample hold circuit ₅₀ .
is maintained. This sample held waveform
V _H2 is shown in Figure 4d. This voltage V _H2 has a voltage V _H1
Since spikes 104 and 106 that are in phase with the voltages V _H1 and V _H2 are applied to the differential amplifier 54
By subtracting each other from each other, a signal V _OUT from which spikes have been substantially removed is obtained at its output terminal 56 .

Next, another embodiment of the present invention is shown in FIG. This embodiment differs in structure from the embodiment shown in FIG. Both differential outputs of the dynamic amplifier 60 are used as input signals to the sampling circuits 34 and 50, respectively. amplifier 60
is a circuit that outputs a signal having the same phase as the input 33 to the non-inverting output 62 and outputting a signal having the opposite phase to the inverting output 64.

In the above configuration, similar to the embodiment shown in FIG.
After the signal voltage V _OS is clamped to a constant voltage by the clamp circuit 32, the differential amplifier 60 generates two differential outputs, that is, two signals of positive phase and negative phase. These two signals are sampled by sample and hold circuits 34 and 50 driven by the same sampling pulse φSP, respectively, and held in capacitors C _H1 and C _H2 . At this time, the voltage V _H2a held in the capacitor C _H2 is
Shown in Figure f. Note that a voltage waveform similar to that of the embodiment shown in FIG. 1, that is, a voltage V H1 shown in FIG. 4c, for example, appears on the capacitor _{C H1} . As can be seen from these, spikes are superimposed on both voltages V _H1 and V _H2a in the same phase, and since the signal components have a phase difference of 180°, the output terminal of the differential amplifier 54 has spikes 100, 102, 108, 110 removed
A voltage corresponding to 2V _H1 (V _H2 = -V _H1 ) is obtained.

As described above, according to this embodiment, not only spikes are removed, but also a larger signal voltage can be obtained. Note that each circuit element in the above two embodiments can be integrated on a CCD substrate.

Effects According to the present invention, spike noise generated during sampling in correlated double sampling can be removed without using a low-pass filter.

Therefore, the output circuit of the charge transfer device can be miniaturized, and when the present invention is used in an imaging device, there is no need to block signal components in a specific frequency band, so there is no deterioration in image resolution due to this. do not have.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the output circuit of a charge transfer device according to the present invention, FIG. 2 is a circuit diagram showing the configuration of a charge transfer device to which the output circuit according to the present invention is applied, and FIG. FIG. 2 is a waveform diagram showing the operation of each part of the charge transfer device, FIG. 4 is a waveform diagram showing the operation of the output circuit shown in FIGS. 1 and 5, and FIG. 5 is a waveform diagram showing the operation of the output circuit shown in FIGS. FIG. 2 is a circuit diagram showing an example. Explanation of symbols of main parts, 32...clamp circuit, 34, 50...sample hold circuit, 5
4,60...Differential amplifier.

Claims (1)

[Claims] 1. A charge transfer path for sequentially transferring accumulated charges to an output side, and a charge transfer path formed at the output end of the charge transfer path to sequentially detect and read signal charges transferred from the charge transfer path. A charge transfer device having a detection means, an output means for outputting the signal charge read from the detection means, and a reset means for periodically resetting the detection means to a predetermined potential outputs an output according to the signal charge. The output circuit of the charge transfer device to be taken out includes: clamping means for temporarily clamping the output of the outputting means to a predetermined voltage; and a first clamping means for sampling and holding the output of the outputting means after the clamping. a second sample and hold means for sampling and holding a signal fixed at a predetermined potential in synchronization with the first sample and hold means; 1. An output circuit for a charge transfer device, comprising: arithmetic means for outputting a signal according to a difference. 2. A charge transfer path that sequentially transfers the accumulated charges to the output side, a detection means formed at the output end of the charge transfer path and sequentially detects and reads out the signal charges transferred from the charge transfer path, and A charge transfer device for extracting an output corresponding to a signal charge from a charge transfer device having an output means for outputting a signal charge read out by a detection means, and a reset means for periodically resetting the detection means to a predetermined potential. The output circuit includes: a clamping means for temporarily clamping the output of the outputting means to a predetermined voltage; and a circuit receiving the output of the clamping means and outputting signals of positive phase and negative phase of the output. means, first sample and hold means for sampling and holding the positive phase output signal of the circuit means after the clamping, and an opposite phase output of the circuit means in synchronization with the first sample and hold means. An output of a charge transfer device characterized by having a second sample and hold means for sampling and holding a signal, and an arithmetic means for outputting a signal according to the difference between the outputs of the first and second sample and hold means. circuit.