JP4536234B2 - Charge coupled device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for driving a charge coupled device, and more particularly to a charge coupled device that outputs a charge transferred by a transfer gate electrode from an ohmic junction electrode and reduces the feedthrough of a clock signal with respect to an output signal. It is about.
[0002]
[Prior art]
In recent years, charge coupled devices (hereinafter referred to as CCDs) have been used in many fields including image sensors and delay lines. In particular, how to detect the amount of charge transferred with high accuracy is a major issue. FIG. 3 shows a conventional CCD and its driving method. FIG. 3 is a schematic diagram of a typical two-phase CCD. Here, description will be given with particular emphasis on the behavior of the output section. However, the CCD used here is n-type (carrier is an electron), and all are discussed in terms of voltage. Therefore, the polarity is opposite to that of the channel potential normally discussed in the CCD.
[0003]
In FIG. 3, 1-4 are Schottky junction transfer gate electrodes, 5 is a Schottky junction output gate electrode, 6 is a first ohmic junction electrode, 7 is a Schottky junction first gate electrode, and 8 is a Schottky junction second. A gate electrode 9 is a second ohmic junction electrode. The lower surfaces of the electrodes 1 to 4 are semiconductor regions constituting the CCD. The lower surfaces of the electrodes 6 to 9 constitute a dual gate FET for charge reset using the electrode 6 as a source, the electrodes 7 and 8 as a dual gate, and the electrode 9 as a drain. 31 and 32 are two-phase clock signal sources (transfer clock signal sources) based on clock signals φ4 and φ5 that are 180 degrees out of phase, 33 and 14 are bias sources, and 15 is a reset signal source for a reset signal φ3 (in phase with the clock signal φ4). , 16 is a power source, 17 is a high input impedance amplifier, and 18 is an output terminal.
[0004]
FIG. 4 is a diagram for explaining the operation of the charge coupled device of FIG. 3. FIG. 4A shows the potential when the clock signal φ4 is “H”, the clock signal φ5 is “L”, and the reset signal φ3 is “H”. ) Indicates the potential when the clock signal φ4 is “L”, the clock signal φ5 is “H”, and the reset signal φ3 is “L”. Further, (c) is a waveform diagram of the clock signal φ5, (d) is a waveform diagram of the clock signal φ4, and (e) is a waveform diagram of the reset signal φ3.
[0005]
Charges injected into the semiconductor region by a photodiode (not shown) or a charge input mechanism are caused by potential fluctuations caused by the two-phase clock signals φ4 and φ5 from the clock signal sources 31 and 32 applied to the transfer gate electrodes 1 to 4. 3 are transferred from the left side to the right side in FIG.
[0006]
When the potential of the final transfer gate electrode 4 is “H”, the output gate electrode 5 blocks the charge as shown in FIG. 4A, and when it is “L”, the output gate electrode 5 shows as shown in FIG. 4B. Then, the electric power is biased by the power source 33 so that the electric charge passes over the output gate electrode 5 and flows into the first ohmic junction electrode 6 which is floating. Further, the output gate electrode 5 prevents the electric charge charged around the first ohmic junction electrode 6 from flowing backward in the direction of the transfer gate electrodes 1 to 4. Furthermore, this output gate electrode 5 reduces the so-called leakage (feedthrough) of the clock signal φ4 from the clock signal source 31 applied to the final transfer gate electrode 4 to the first ohmic junction electrode 6 through the parasitic capacitance. Also serves as a guard electrode.
[0007]
The dual gate FET composed of the electrodes 6 to 9 can accept the next transferred charge packet by discharging the charge stored in the first ohmic junction electrode 6 and its surrounding capacitance to the power supply 16. Functions as a reset FET. The second ohmic junction electrode 9 as the drain discharges electric charge to the power supply 16. When the reset signal φ3 from the reset signal source 15 is applied to the second gate electrode 8, and the potential of the reset signal φ3 is “H”, as shown in FIG. 4A, the first ohmic junction electrode A reset operation is performed to discharge the electric charge in 6 to the power supply 16. Note that a DC bias shallower than the pinch-off voltage is applied to the first gate electrode 7 by the bias source 14, and the reset signal φ3 applied to the second gate electrode 8 is applied to the first gate electrode 8 in the same manner as the output gate electrode 5 described above. It also serves as a guard electrode that reduces feedthrough toward the ohmic junction electrode 6.
[0008]
In the operation sequence, when the charge of the CCD reaches just below the final transfer gate electrode 4, the potential of the gate electrode 8 is set to "H", and the charge charged in the first ohmic junction electrode 6 and the surrounding capacitance is charged. Is discharged as shown in FIG. Next, as shown in FIG. 4B, the potential of the second gate electrode 8 is set to “L” to shut off the dual gate FET, and at the same time, the potential of the final transfer gate electrode 4 is set to “L”. Into the first ohmic junction electrode 6. The flowed-in charge charges the first ohmic junction electrode 6 and its surrounding capacitance, and the charge signal is converted into a voltage and output from the output terminal 18 to the outside by the high input impedance amplifier 17.
[0009]
[Problems to be solved by the invention]
By the way, although the first ohmic junction electrode 6 which is a floating electrode is guarded by the output gate electrode 5 and the first gate electrode 7, the final transfer gate electrode 4 and the first ohmic junction electrode 6 are still used. And the coupling capacitance remains between the second gate electrode 8 and the first ohmic junction electrode 6. On the other hand, in order to increase the signal level output from the CCD, it is necessary to keep the capacitance around the first ohmic junction electrode 6 small, and a large feedthrough occurs even with a small coupling capacitance. Further, in this case, since the polarity of the clock signal φ4 of the clock signal source 31 applied to the final transfer gate electrode 4 and the reset signal φ3 of the reset signal source 15 are the same, the reset is released and the final transfer gate electrode 4 At the timing when the electric charge is sent to the first ohmic junction electrode 6 (timing (b) in FIG. 4), a large negative feedthrough (feedthrough due to both φ4 and φ3) occurs. For this reason, the amplifier 17 and the subsequent circuit need to have a larger input range in order to accurately extract the charge signal, and there is a problem that the design becomes difficult.
[0010]
The present invention has been made in view of the above points, and an object of the present invention is to provide a charge coupled device in which feedthrough to an output is greatly reduced.
[0011]
[Means for Solving the Problems]
First inventions For this purpose, a plurality of transfer gate electrodes of the transfer clock signal is applied, a first ohmic contact electrode for taking out the charges transferred by the transfer gate electrodes, a DC voltage is applied A second ohmic junction electrode, and a gate electrode provided between the first ohmic junction electrode and the second ohmic junction electrode to which a reset signal is applied, the first ohmic junction electrode, In the charge coupled device in which the second ohmic junction electrode and the gate electrode form a charge reset FET, a transfer clock signal for driving a final transfer gate electrode of the plurality of transfer gate electrodes, and the gate electrode are driven The reset signal to be set is set so as to be in opposite phases to each other.
[0012]
The second invention is the first invention, the output gate electrode gave a DC voltage between said final transfer gate electrode and the first ohmic contact electrode is provided, one in front of the last transfer gate electrode when the charge stored directly below the transfer gate electrode is transferred through the right under the final transfer gate electrode and said output gate electrode, so that it can reach the first ohmic contact electrode, said output gate The DC voltage applied to the electrode was set.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention is shown in FIG. In FIG. 1, 1 to 4 are Schottky junction transfer gate electrodes, 5 is a Schottky junction output gate electrode, 6 is a first ohmic junction electrode, 7 is a Schottky junction first gate electrode, and 8 is a Schottky junction second. A gate electrode 9 is a second ohmic junction electrode. The lower surfaces of the electrodes 1 to 4 are semiconductor regions constituting the CCD. The lower surfaces of the electrodes 6 to 9 constitute a reset dual gate FET having the electrode 6 as a source, the electrodes 7 and 8 as dual gates, and the electrode 9 as a drain. Reference numeral 14 denotes a bias source, 15 denotes a reset signal source of the reset signal φ3, 16 denotes a power source, 17 denotes a high input impedance amplifier, and 18 denotes an output terminal. The above is the same as the configuration of FIG.
[0014]
This embodiment differs from FIG. 3 in that a two-phase clock signal source that generates clock signals φ1 and φ2 that are 180 degrees different in phase is used as the transfer clock signal sources 11 and 12 of the CCD transfer gate electrodes 1 to 4. This is because the clock signal φ1 is in phase opposite to the reset signal φ3 of the reset signal source 15. Furthermore, the bias level by the bias source 13 applied to the output gate electrode 5 is made shallower, so that the charges immediately below the final transfer gate electrode 4 can pass through the output gate electrode 5 at any time, so that the first ohmic junction electrode 6 is formed. It was to be able to reach.
[0015]
FIG. 2 is a diagram for explaining the operation of the charge coupled device of FIG. 1. FIG. 2A shows the potential when the clock signal φ1 is “L”, φ2 is “H”, and φ3 is “H”, and FIG. The potential when the clock signal φ1 is “H”, φ2 is “L”, and φ3 is “L” is shown. (C) is a waveform diagram of the clock signal φ2, (d) is a waveform diagram of the clock signal φ1, and (e) is a waveform diagram of the reset signal φ3.
[0016]
In the present embodiment, when the transfer charge of the CCD reaches immediately below the transfer gate electrode 3 immediately before the final transfer gate electrode 4 , the potential of the second gate electrode 8 is set to “H”, and the first The charge charged in the ohmic junction electrode 6 and its surrounding capacitance is discharged as shown in FIG. Next, as shown in FIG. 2B, the potential of the gate electrode 8 is set to “L” to shut off the dual gate FET, and at the same time, the potential of the transfer gate electrode 3 is set to “L”, and the final transfer gate electrode 4 Is set to “H”, and charges are directly flowed from the transfer gate electrode 3 to the first ohmic junction electrode 6. The flowed-in charge charges the first ohmic junction electrode 6 and its surrounding capacitance, and the charge signal is converted into a voltage and output from the output terminal 18 to the outside by the high input impedance amplifier 17.
[0017]
As described above, in this embodiment, when the transfer gate electrode 3 immediately before the final transfer gate electrode 4 transits from “H” to “L”, the charge immediately below the transfer gate electrode 3 is As shown in FIG. 2 (b), it passes through the transfer gate electrode 4 and the output gate electrode 5 and flows into the first ohmic junction electrode 6. At this time, since the clock signal φ1 of the final transfer gate electrode 4 that determines the feedthrough to the first ohmic junction electrode 6 and the reset signal φ3 of the reset signal source 15 have opposite polarities, these clock signals are Canceled by the first ohmic junction electrode 6, feedthrough to the output side can be kept small.
[0018]
In designing a general CCD, the reset signal is shared with the clock signal, and in this embodiment, the reset signal φ3 can be shared with the clock signal φ2. From this, it can be expected that the clock signal φ1 and the reset signal φ3 have the same amplitude, and the coupling capacitance between the final transfer gate electrode 4 and the first ohmic junction electrode 6 that determines the feedthrough amount, the gate If the coupling capacity between the electrode 8 and the first ohmic junction electrode 6 is designed to be equal, the feedthrough is completely canceled and becomes zero.
[0019]
FIG. 5 shows the output waveform of the CCD obtained in the experiment. (b) is an output waveform obtained by a conventional driving method, and (a) is an output waveform obtained by a driving method according to the present invention. In either case, a sinusoidal CCD input signal was given. In (a), it can be seen that the charge signal component obtained by delaying the CCD input signal appears as an envelope immediately below the reset level, and the feedthrough component of the clock signal is very small. On the other hand, in (b), the feed-through component is large, and it can be seen that the input circuit needs to be enlarged in order to capture the charge signal component in the subsequent circuit of the output terminal 18.
[0020]
In the above description, the electrodes 1 to 5, 7, and 8 are not limited to Schottky junction electrodes, but may be metal electrodes with an insulating film interposed on the upper surface of the semiconductor, and may have a MOS structure.
[0021]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a method for driving a charge coupled device with less feedthrough to the output side. As a result, the input range of the output amplifier and the subsequent circuit can be reduced, which contributes to improvement of system performance and cost reduction.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a driving method of a charge coupled device of the present invention.
2A and 2B are potential state diagrams, and FIGS. 2C and 2D are waveform diagrams of clocks φ2, φ1, and φ3. FIG.
FIG. 3 is an explanatory diagram of a conventional method of driving a charge coupled device.
4A and 4B are potential state diagrams, and FIGS. 4C and 4D are waveform diagrams of clocks φ5, φ4, and φ3.
5A is an input / output waveform diagram when the method of FIG. 1 is used, and FIG. 5B is an input / output waveform diagram when the method of FIG. 3 is used.
[Explanation of symbols]
1, 2, 3, 4: transfer gate electrode, 5: output gate electrode, 6: first ohmic junction electrode, 7: first gate electrode, 8: second gate electrode, 9: second ohmic junction electrode, 11, 12: Clock signal source, 13, 14: Bias power source, 15: Reset signal source, 16: Power source

Claims (2)

A plurality of transfer gate electrodes of the transfer clock signal is applied, a first ohmic contact electrode for taking out the charges transferred by the transfer gate electrodes, a second ohmic contact electrode to which a DC voltage is applied, the A gate electrode provided between the first ohmic junction electrode and the second ohmic junction electrode to which a reset signal is applied, the first ohmic junction electrode, the second ohmic junction electrode, and the gate; In the charge coupled device in which the electrode constitutes a charge reset FET,
A charge-coupled device, wherein a transfer clock signal for driving a final transfer gate electrode of the plurality of transfer gate electrodes and a reset signal for driving the gate electrode are set in opposite phases. The charge coupled device of claim 1, wherein
Providing an output gate electrode that applies a DC voltage between the final transfer gate electrode and the first ohmic junction electrode;
When the electric charge stored immediately below the transfer gate electrode immediately before the final transfer gate electrode is transferred, the charge passes immediately below the final transfer gate electrode and the output gate electrode , and the first ohmic junction. A charge-coupled device, wherein a DC voltage applied to the output gate electrode is set so as to reach the electrode.

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