JPH10321836A - Method for driving solid-state charge transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a broad dynamic range and a high S/N by performing resetting operations on a charge-voltage converting section by making the potential value of the converting section when the section is depleted under a reset gate when a reset pulse is given lower than the voltage value or a reset drain region. SOLUTION: Resetting operations are performed so that the floating diffusion region 7 of the so-called reset transistor composed of a floating diffusion region 7, a reset gate section 11, and a reset drain region 10 may be reset through the operation of the saturated region of the reset transistor. The resetting of the region 7 is performed by setting the potential value when the region 7 is depleted under the reset gate section 11 when the high-level of a reset pulse ϕRG is given to the reset gate section 11. Therefore, the operating range of the diffusion region 7 can be widened, namely, high S/N signals can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a solid-state charge transfer device, and more particularly to a method for resetting signal charges in a charge-voltage converter.

[0002]

2. Description of the Related Art FIG. 9 shows a configuration of a final stage portion and an output section of a horizontal transfer register of a conventional CCD solid-state imaging device. In FIG. 1, reference numeral 1 denotes a horizontal transfer register having a CCD structure. The horizontal transfer register 1 includes a plurality of transfer sections 3 having transfer electrodes, that is, storage electrodes 2S and transfer electrodes 2T, and two-phase driving pulses φH ₁ and φH.
₂ is formed so as to transfer signal charges in the horizontal direction. 4 is a horizontal transfer channel.

The transfer unit 3 at the last stage of the horizontal transfer register 1 is connected to, for example, a floating diffusion region 7 serving as a charge-voltage conversion unit via a horizontal output gate unit 6 to which a gate voltage V _HOG is applied. The signal charge is transferred to the floating diffusion region 7, is subjected to charge-voltage conversion, and is output through the output amplifier 8. In this output unit 9,
In order to release the signal charges transferred to the floating diffusion region 7 to the reset drain region 10 to which the reset drain voltage V _RD is applied, the two regions 7 and 10
A reset gate portion 11 to which a gate voltage, that is, a reset pulse _φRG is applied is formed. Reference numeral 12 denotes an output gate electrode constituting the horizontal output gate unit 6, and reference numeral 13 denotes a reset gate electrode constituting the reset gate unit 11.

The reset operation of the floating diffusion region 7 is realized by _applying a reset pulse _φRG to the reset gate electrode 13 so as to perform a complete reset in a state where the reset pulse _{φRG is at} a high level. That is, the potential is controlled by the concentration profile of the substrate or the like so that the potential value at the time of depletion under the reset gate when the reset pulse φ _RG (gate voltage) is at a high level becomes higher than the reset drain voltage value V _RD. ,
This is realized by giving an offset to the reset pulse.

FIGS. 10 and 11 show an example of the drive timing and potential diagram of the reset operation in the conventional example of FIG.

At time t ₁ , the reset gate unit 11
Reset pulse phi _RG high level is applied the reset gate portion 11 is turned on (see FIG. 10), the potential value under the reset gate becomes higher than the reset drain potential V _RD, the potential of the floating diffusion region 7 reset drain The potential is reset to V _RD (FIG. 11)
reference).

Next, at time t ₂ , the reset gate section 11 turns off (see FIG. 10). At this time, the potential variation 15 due to coupling is added to the potential of the floating diffusion region 7 (see FIG. 11).

[0008] Then, at time t _3, the signal charges e are transferred to the floating diffusion region 7 at the falling of the drive pulse .phi.H ₁ of the horizontal transfer register 1, the potential V _FD of the floating diffusion region 7 is changed, the voltage V _OUT Is output through the output amplifier 8 (see FIGS. 9, 10 and 11).

In a normal design, the potential under the reset gate is set to be deeper than the voltage V _RD of the reset drain region 10 when the reset pulse φ _RG is at a high level in order to perform a complete reset. In addition, the potential under the reset gate is set deeper with a margin in consideration of variations in potential between chips and variations in power supply voltage.

[0010]

However, as described above, the potential under the reset gate at the time of resetting is set deeper in consideration of variations in potential between chips and variations in power supply voltage. , the operation range of the floating diffusion region 7 as the charge-voltage converter is narrowed, that is, the signal dynamic range D ₁ is reduced, in particular the influence such as increase when reducing the power supply voltage. For example, as shown in FIG. 12, as the power supply voltage decreases, the dynamic range D of the signal increases.
₂ becomes small, which is disadvantageous for the signal-to-noise ratio of the signal.

The present invention has been made in view of the above circumstances, and provides a method of driving a solid-state charge transfer device that enables a charge-voltage converter having a wide dynamic range and a high SN ratio.

[0012]

According to the present invention, the reset operation of the charge-voltage converter is performed by lowering the potential value at the time of depletion under the reset gate when a reset pulse is applied, to be lower than the reset drain voltage value.

As described above, in the reset operation of the charge-voltage converter, the potential value under the reset gate at the time of reset is made lower than the reset drain voltage value, and the reset transistor of the charge-voltage converter is operated in a saturation region (Saturation) operation. And reset it,
The dynamic range of the signal in the charge-voltage converter increases, and a high SN ratio can be obtained. In addition, it is possible to cope with variations in the potential under the reset gate between chips and fluctuations in the power supply voltage, so that the solid-state charge transfer device can operate at a low power supply voltage.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method for driving a solid-state charge transfer device according to the present invention, a potential value at the time of depletion under a reset gate when a reset pulse is applied to the reset gate is set lower than a reset drain voltage value. The reset operation of the charge-voltage converter is performed.

According to the present invention, in the driving method of the solid-state charge transfer device, the reset drain is pulse-driven, and the potential of the reset drain is operated at a level higher or lower than a potential value under the reset gate when depleted.

Hereinafter, description will be made with reference to the drawings.

1 to 3 show an example of the present invention. FIG.
1 shows an example of the configuration of an end portion and an output section of the horizontal transfer register of the CCD solid-state imaging device according to the present invention. However, in this figure, parts corresponding to those in FIG. 9 are denoted by the same reference numerals. In the present invention, similarly to FIG. 9, the transfer electrode,
That is, a plurality of transfer units 3 each having the storage electrode 2S and the transfer electrode 2T are arranged, and the two-phase drive pulse φH ₁
A horizontal transfer register 1 for sequentially transferring signal charges in the horizontal direction at φH _2, a horizontal output gate unit 6 connected to the transfer unit 3 at the last stage of the horizontal transfer register 1, and a floating diffusion region 7 for charge-voltage conversion And a reset gate unit 11 for releasing the signal charges transferred to the floating diffusion region 7 to the reset drain region 10. Horizontal output gate 6
A gate voltage V _HOG is applied to the output gate electrode 12, and a gate voltage, that is, a reset pulse φ _RG is applied to the reset gate electrode 13 of the reset gate unit 11. Further, a reset drain voltage V _RD is applied to the reset drain region 10.

In the present invention, in particular, the floating diffusion region 7 serving as a charge-to-voltage converter is provided.
This reset operation is performed by a so-called saturation operation of a reset transistor including the floating diffusion region 7, the reset gate portion 11, and the reset drain region 10 without performing a complete reset as in the related art. That is, the potential value at the time of depletion under the reset gate when the high level of the reset pulse φ _RG is given to the reset gate unit 11 is set lower than the reset drain voltage value V _RD , and the floating diffusion region 7 is reset. To do.

FIG. 2 shows the drive timing of the reset operation in the present invention shown in FIG. 1, and FIG. 3 shows a potential diagram thereof.

First, at time t ₁ , a high level of a reset pulse φ _RG is applied to the reset gate section 11 (see FIG. 2). At this time, the potential at the time of depletion under the reset gate is the potential V _{RD of the} reset drain region 10.
It is set to be relatively shallower (see FIG. 3). For example, if the high level of the reset pulse phi _RG is the same as the reset pulse phi _RG conventional 10, the reset drain region 10 so that the potential relationship shown in the time t ₁ in FIG. 3
High to set the reset drain voltage V _RD to be applied to.
As a result, signal charges in the floating diffusion region 7 are released to the reset drain region 10 through the reset gate portion 11 by the so-called saturation region operation of the reset transistor, and the potential of the floating diffusion region 7 becomes lower than the potential at the time of depletion under the reset gate. It is reset to the corresponding potential.

Next, at time t ₂ , the reset gate section 11 turns off (see FIG. 2). At this time, the potential variation 15 due to the coupling is added to the potential of the floating diffusion region 7 (see FIG. 3). As is clear from the potential diagram of the time t _2, the dynamic range D ₃ signals at floating Defi-menu John region 7 is greater than the dynamic range D ₁ of the signal in the conventional time t ₂ (see FIG. 11) (D ₃ > D ₁ ).

Thereafter, at time t ₃ , the signal charge e is transferred to the floating diffusion region 7 at the falling of the driving pulse φH ₁ of the horizontal transfer register, and the potential V _{FD of the} floating diffusion region 7 changes.
The voltage is output through the output amplifier 8 as a voltage V _OUT proportional to the charge amount (see FIGS. 1, 2, and 3).

According to the reset operation, the reset potential of the floating diffusion region 7 is reduced by resetting by the so-called saturation region operation of the reset transistor including the floating diffusion region 7, the reset gate portion 11, and the reset drain region 10. Instead of the conventional reset drain potential V _RD ,
High level of the reset pulse phi _RG is defined by the potential of the depletion time under the reset gate when it is applied.

Therefore, the operating range of the floating diffusion region 7 is wide, that is, the dynamic range of the signal is large, and a high SN ratio of the signal can be obtained. Also,
It is possible to design the floating diffusion region 7 with no characteristic fluctuation even when the potential varies between chips or the power supply fluctuates.

Further, as shown in FIG. 4, even when the low power supply voltage operation is advanced, the dynamic range D _{4 of the} signal can be made larger than that of the conventional example shown in FIG. 12 (D ₄ >).
D ₂ ), a CCD solid-state imaging device having a high SN ratio can be realized.

The reset operation in the saturation region operation is as follows.
Response speed is slower than complete reset. That is, the potential difference between the floating diffusion region 7 and the reset drain region 10 becomes smaller as the signal charges in the floating diffusion region 7 are released to the reset drain region 10 at the time of reset, and accordingly, the source and drain of the reset transistor are reduced. Since the resistance component between them becomes large, the release of the signal charges to the reset drain region 10 is delayed.

FIGS. 5 to 8 show examples in which the reset response speed in the saturation region operation is improved. In this example, as shown in FIG. 5, the reset drain region 10 is pulse-driven by a pulse φ _RD during the reset period, and the potential of the reset drain region 10 is set below the reset gate when the high level of the reset pulse φ _RG is applied. High / low operation is performed with respect to the potential at the time of depletion.

The driving timing chart of FIG. 6 and FIGS. 7 and 8
This will be described with reference to the potential diagram of FIG. In the reset period in which the reset pulse φ _RG is applied to the reset gate unit 11, first, at time t ₁ in the previous stage, a high-level voltage V _RD1 is applied to the reset drain region 10 (see FIG. 6). the potential of 10 becomes higher than the potential value under the reset gate, the charge emission is made from the floating diffusion region 7 in the same manner as described in time t ₁ in FIG. 3 (see FIG. 7).

At the next middle stage time t ₂ , a reset drain pulse φ _RD is applied to the reset drain region 10,
That is, a low-level voltage V _RD2 is applied (see FIG. 6), and the potential of the reset drain region 10 becomes lower than the potential value under the reset gate (see FIG. 7). Thereby, the potential of the floating diffusion region 7 becomes
The potential is set to the same V _RD2 as the potential of the reset drain region 10.

Time t of the next subsequent stage_ThreeThen, reset again
A high level voltage V is applied to the rain region 10. _RD1Given
The potential of the set drain region 10 is
It becomes higher than the tension value (see FIG. 7). At this time,
When the potential of the set drain region 10 is V_RD2Resetge from
Until the potential corresponding to the potential value under the
The floating drain is connected to the potential of the reset drain region 10.
The potential of the fusion region 7 follows with good responsiveness. Soshi
And the potential of the reset drain region 10 is reset gate
V higher than the potential corresponding to the lower potential value_RD1Nana
Again, the signal charge has the same response as in FIG. 3 again.
It will be released to the reset drain region 10.

At the next time point t ₄ , the reset gate unit 11 is turned off (see FIGS. 6 and 8). At the subsequent time point t ₅ , the driving pulse φH ₁ of the horizontal transfer register falls,
The signal charge e is transferred to the floating diffusion region 7 and output as a voltage through the output amplifier 8 (see FIGS. 6 and 8).

According to this reset operation, while extending from time t ₂ to time t _3, the potential of the floating diffusion region 7 as a whole to follow the potential of the good response reset drain region 10, FIGS. 1 to 3 The response speed of the reset is faster than that of the example. Therefore, it is possible to cope with a case where the transfer charge amount of each bit varies greatly or a case where high speed is required.

The driving method of the present invention is applicable to CCD imagers, linear sensors, and the like.

[0034]

According to the driving method of the solid-state charge transfer device according to the present invention, the depletion under the reset gate when a reset pulse is given to the reset gate without performing a complete reset in the reset operation of the charge-voltage converter. The reset voltage is set lower than the reset drain voltage value, that is, reset operation is performed in the saturation region operation of the reset transistor, thereby realizing a charge-voltage converter having a wide dynamic range and a high SN ratio. be able to.

Further, it is possible to design a charge-to-voltage conversion unit which is not affected at all by variations in the potential under the reset gate between chips and fluctuations in the power supply voltage and without fluctuations in characteristics.

In addition, even in the low power supply voltage operation, a wide dynamic range and a high signal-to-noise ratio can be obtained, and the solid state charge transfer device can operate at a low power supply voltage.

Further, in the reset operation of the charge-voltage converter, the reset transistor is operated in the saturation region as described above, and the reset drain is driven by a pulse so that the potential of the reset drain becomes the potential value under the reset gate at the time of depletion. In contrast, when performing the high / low operation, the response speed of the reset operation can be further increased, and it is possible to cope with a case where the amount of transfer charge per bit varies greatly or a case where high speed is required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of an output portion of a solid-state imaging device according to the present invention.

FIG. 2 is a drive timing chart of the solid-state imaging device of FIG.

FIG. 3 is a potential diagram at the time of a reset operation of a charge-voltage converter of the solid-state imaging device of FIG. 1;

FIG. 4 is a potential diagram in a reset operation when the power supply voltage of the solid-state imaging device according to the present invention drops.

FIG. 5 is a configuration diagram showing another example of the output portion of the solid-state imaging device according to the present invention.

FIG. 6 is a drive timing chart of the solid-state imaging device of FIG. 5;

FIG. 7 is a potential diagram (part 1) during a reset operation of the charge-voltage converter of the solid-state imaging device in FIG. 5;

8 is a potential diagram (part 2) during a reset operation of the charge-voltage converter of the solid-state imaging device in FIG.

FIG. 9 is a configuration diagram of an output portion of a conventional solid-state imaging device.

FIG. 10 is a drive timing chart of the solid-state imaging device of FIG. 9;

11 is a potential diagram at the time of a reset operation of the charge-voltage converter of the solid-state imaging device of FIG. 9;

FIG. 12 is a potential diagram in a reset operation when a power supply voltage of a conventional solid-state imaging device drops.

[Description of Signs] 1 horizontal transfer register, 2T, 2S transfer electrode, 3 transfer section, 6 horizontal output gate section, 7 floating diffusion area, 8 output amplifier, 10 reset drain area, 11 reset Gate section, V _RD , V _RD1 ,
V _RD2 : reset drain voltage, φ _RD : reset drain pulse, φ _RG : reset pulse

Claims (2)

[Claims] 1. A reset operation of a charge-voltage converter is performed by setting a potential value at the time of depletion below a reset gate when a reset pulse is applied to the reset gate to be lower than a reset drain voltage value. For driving a solid-state charge transfer device. 2. The solid-state charge transfer device according to claim 1, wherein the reset drain is pulse-driven, and the potential of the reset drain is operated to be higher or lower than a potential value under the reset gate at the time of depletion. Drive method.