JP2002094047A - Charge-coupled device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce feedthroughs to an output. SOLUTION: The phase of a clock signal, driving a final transmission gate electrode 4, is set different by 180 deg. from the phase of a reset signal driving a second gate 8. The bias voltage of an output gate electrode 5 is set to voltage with the charge accumulating directly below the final transmission gate electrode 4 capable of reaching a first ohmic junction electrode 6, by passing directly below its output gate electrode 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a charge-coupled device, and more particularly, to a method of driving a charge-coupled device in which charges transferred by a transfer gate electrode are output from an ohmic junction electrode. The present invention relates to a charge-coupled device that reduces through.

[0002]

2. Description of the Related Art In recent years, charge-coupled devices (hereinafter referred to as CCDs) have been used in many fields such as image sensors and delay lines. In particular, how to detect the amount of charge transferred with high accuracy has become a major issue. FIG. 3 shows a conventional CCD and its driving method. FIG. 3 is a schematic diagram of a typical two-phase CCD, and the description will be given here with particular emphasis on the behavior of the output unit. However, the CCD used here is of the n-type (electrons are carriers), and all are discussed in terms of voltage. Therefore, the polarity is opposite to the discussion of the potential of the channel which is usually discussed in the CCD.

In FIG. 3, reference numerals 1 to 4 denote transfer gate electrodes having a Schottky junction, 5 an output gate electrode having a Schottky junction, 6 a first ohmic junction electrode, 7 a first gate electrode having a Schottky junction, and 8 a Schottky junction. The second gate electrode 9 is a second ohmic junction electrode. Electrodes 1
The lower surface of 4 is a semiconductor region constituting a CCD.
The lower surfaces of the electrodes 6 to 9 constitute a dual gate FET for resetting electric charges using the electrode 6 as a source, the electrodes 7 and 8 as dual gates, and the electrode 9 as a drain. 31, 32
Are two-phase clock signal sources (transfer clock signal sources) based on clock signals φ4 and φ5 having phases different by 180 degrees,
4 is a bias source, 15 is a reset signal source of a reset signal φ3 (having the same phase as the clock signal φ4), 16 is a power source, 17 is a high input impedance amplifier, and 18 is an output terminal.

FIG. 4 is a diagram for explaining the operation of the charge-coupled device of FIG. 3. (a) shows that the clock signal φ4 is “H” and the clock signal φ is
5 is “L”, the potential when the reset signal φ3 is “H”, and (b) is when the clock signal φ4 is “L”, the clock signal φ5 is “H”, and the reset signal φ3 is “L”. Shows the potential of Further, (c) is a waveform diagram of the clock signal φ5, (d) is a waveform diagram of the clock signal φ4, and (e)
Is a waveform diagram of the reset signal φ3.

The charge injected into the semiconductor region by a photodiode or a charge input mechanism (not shown) is applied to clock signal sources 31 applied to the transfer gate electrodes 1-4.
3 is transferred from the left side to the right side in FIG.

When the potential of the final transfer gate electrode 4 is "H", the output gate electrode 5 blocks the charge as shown in FIG. 4A, and when the potential is "L", the output gate electrode 5 shown in FIG. Is biased by the power supply 33 so that the electric charge passes through the output gate electrode 5 and flows into the first ohmic junction electrode 6 which is floating. Further, the output gate electrode 5 prevents the charge charged around the first ohmic junction electrode 6 from flowing backward in the direction of the transfer gate electrodes 1 to 4. Further, the output gate electrode 5 reduces the leakage (feedthrough) of the clock signal φ4 from the clock signal source 31 applied to the final transfer gate electrode 4 to the first ohmic junction electrode 6 through the parasitic capacitance. Also serves as a guard electrode.

The dual gate FET comprising the electrodes 6 to 9 discharges the electric charge stored in the first ohmic junction electrode 6 and the capacitance around the first ohmic junction electrode 6 to the power supply 16 so that the next charge packet transferred Function as a reset FET which allows the reset FET to be accepted. The second ohmic junction electrode 9 as a drain discharges electric charges to the power supply 16. The reset signal φ3 from the reset signal source 15 is applied to the second gate electrode 8, and the reset signal φ3
When the potential of No. 3 is “H”, as shown in FIG. 4A, a reset operation of discharging the electric charge on the first ohmic junction electrode 6 to the power supply 16 is performed. The first gate electrode 7
Is applied with a DC bias shallower than the pinch-off voltage by the bias source 14, and the reset signal φ applied to the second gate electrode 8 as in the output gate electrode 5 described above.
3 also serves as a guard electrode for reducing feedthrough toward the first ohmic junction electrode 6.

In the operation sequence, when the charge of the CCD reaches just below the final transfer gate electrode 4, the potential of the gate electrode 8 is set to "H" to charge the first ohmic junction electrode 6 and the capacitance around it. The generated charge is discharged as shown in FIG. Next, as shown in FIG.
The potential of the gate electrode 8 is set to “L” to make the dual gate FE
T is cut off, and at the same time, the potential of the final transfer gate electrode 4 is set to “L”, and the electric charge flows into the first ohmic junction electrode 6. The flowed charge charges the first ohmic junction electrode 6 and the capacitance around it, and the charge signal is converted into a voltage and output from the output terminal 18 to the outside by the high input impedance amplifier 17.

[0009]

The first ohmic junction electrode 6, which is a floating electrode, is guarded by the output gate electrode 5 and the first gate electrode 7, but it is still a final transfer gate electrode. 4 and the first ohmic junction electrode 6, and between the second gate electrode 8 and the first ohmic junction electrode 6, a coupling capacitance remains. On the other hand, in order to increase the signal level output from the CCD, it is necessary to suppress the capacitance around the first ohmic junction electrode 6, and a large feedthrough occurs even with a small coupling capacitance. Further, in this case, since the polarity of the clock signal φ4 of the clock signal source 31 applied to the final transfer gate electrode 4 and the polarity of the reset signal φ3 of the reset signal source 15 are the same, the reset is released and the final transfer gate electrode 4 Charge from the first ohmic junction electrode 6
4 (the timing of FIG. 4B), a large negative feedthrough (feedthrough by both φ4 and φ3) occurs. For this reason, the amplifier 17 and the circuit at the subsequent stage need to have a larger input range in order to accurately extract the charge signal, and there is a problem that the design becomes difficult.

[0010] The present invention has been made in view of the above points, and an object of the present invention is to provide a charge-coupled device in which feedthrough to an output is greatly reduced.

[0011]

For this purpose, a first aspect of the present invention provides a plurality of transfer gate electrodes to which a transfer clock signal is applied, and a first ohmic junction for taking out charges transferred by the transfer gate electrodes. An electrode, a second ohmic junction electrode to which a DC voltage is applied, and a gate electrode provided between the first ohmic junction electrode and the second ohmic junction electrode and to which a reset signal is applied, In the charge coupled device in which the first ohmic junction electrode, the second ohmic junction electrode, and the gate electrode form a charge reset FET, a transfer clock for driving a final transfer gate electrode among the plurality of transfer gate electrodes The signal and the reset signal for driving the gate electrode are set so as to have opposite phases to each other.

According to a second aspect, in the first aspect, an output gate electrode to which a DC voltage is applied is provided between the final transfer gate electrode and the first ohmic junction electrode, and an output gate electrode is provided immediately below the final transfer gate electrode. The stored charge is independent of the transfer clock signal level of the final transfer gate electrode.
A DC voltage to be applied to the output gate electrode was set so as to pass directly below the output gate electrode and reach the first ohmic junction electrode.

[0013]

FIG. 1 shows an embodiment of the present invention.
In FIG. 1, reference numerals 1 to 4 denote transfer gate electrodes of a Schottky junction, 5 denotes an output gate electrode of a Schottky junction, 6 denotes a first ohmic junction electrode, 7 denotes a first gate electrode of a Schottky junction, and 8 denotes a second gate electrode of a Schottky junction. The gate electrode, 9 is the second
Ohmic junction electrode. The lower surface of electrodes 1-4 is CC
This is a semiconductor region constituting D. The electrodes 6 to 9
The lower surface of FIG. 1 constitutes a reset dual-gate FET using the electrode 6 as a source, the electrodes 7 and 8 as dual gates, and the electrode 9 as a drain. 14 is a bias source, 15 is a reset signal source for the reset signal φ3, 16 is a power supply, 17 is a high input impedance amplifier, and 18 is an output terminal.
The above is the same as the configuration of FIG.

The difference between this embodiment and FIG.
D, the transfer clock signal source 11 for the transfer gate electrodes 1-4,
12, clock signals φ1,
A two-phase clock signal source for generating φ2 is used, and the clock signal φ1 is used as the reset signal φ3 of the reset signal source 15.
This is the opposite phase. Further, by making the bias level of the bias source 13 applied to the output gate electrode 5 shallower, the electric charge immediately below the final transfer gate electrode 4 can pass through the output gate electrode 5 at any time, and the first ohmic junction electrode 6 Is to be able to reach.

FIG. 2 is a diagram for explaining the operation of the charge-coupled device shown in FIG. 1. FIG. 2 (a) shows that the clock signal φ1 is “L”, φ2 is “H”
The potential when φ3 is “H”, (b) is the opposite, clock signal φ1 is “H”, φ2 is “L”, and φ3 is “L”.
The potential at the time of is shown. Also, (c) is a waveform diagram of the clock signal φ2, (d) is a waveform diagram of the clock signal φ1, (e)
Is a waveform diagram of the reset signal φ3.

In this embodiment, when the transfer charge of the CCD arrives immediately below the final transfer gate electrode 4, the second charge
The potential of the gate electrode 8 is set to “H”, and the electric charge charged in the first ohmic junction electrode 6 and the capacitance around it is shown in FIG.
Discharge is performed as shown in (a). Next, as shown in FIG. 2B, the potential of the gate electrode 8 is set to “L” to cut off the dual-gate FET, and at the same time, the potential of the transfer gate electrode 3 is set to “L”. Is set to “H”, and charges flow directly from the transfer gate electrode 3 to the first ohmic junction electrode 6. The flowed charge charges the first ohmic junction electrode 6 and the capacitance around it, and the charge signal is converted into a voltage and output from the output terminal 18 to the outside by the high input impedance amplifier 17.

As described above, in this embodiment, the transfer gate electrode 3 immediately before the final transfer gate electrode 4 is set to “H”.
When the state changes from “L” to “L”, the electric charge immediately below the transfer gate electrode 3 passes through the transfer gate electrode 4 and the output gate electrode 5 as shown in FIG. It flows into the electrode 6. At this time, since the clock signal φ1 of the final transfer gate electrode 4 and the reset signal φ3 of the reset signal source 15 which determine the feedthrough to the first ohmic junction electrode 6 have opposite polarities, the clock signals are It is canceled by the first ohmic junction electrode 6, and feedthrough to the output side can be reduced.

In a general CCD design, a reset signal is shared with a clock signal, and in this embodiment, a reset signal φ3 can be shared with a clock signal φ2. From this, it can be expected that the clock signal φ1 and the reset signal φ3 have the same amplitude, and furthermore, the coupling capacitance between the final transfer gate electrode 4 and the first ohmic junction electrode 6, which determines the amount of feedthrough, and the gate If the coupling capacity between the electrode 8 and the first ohmic junction electrode 6 is designed to be equal, the feedthrough is completely canceled and becomes zero.

FIG. 5 shows the output waveform of the CCD obtained in the experiment. (b) shows output waveforms obtained by the conventional driving method, and (a) shows output waveforms obtained by the driving method according to the present invention. In each case, a sinusoidal CCD input signal was provided.
In (a), the charge signal component obtained by delaying the CCD input signal appears as an envelope immediately below the reset level, and it can be seen that the feedthrough component of the clock signal is extremely small. On the other hand, in (b), the feedthrough component is large, and it can be seen that in the circuit at the subsequent stage of the output terminal 18, the input range needs to be enlarged in order to capture the charge signal component.

In the above description, the electrodes 1 to 5,
Metal electrodes 7 and 8 are not limited to Schottky junction electrodes, but are metal electrodes with an insulating film interposed on the upper surface of the semiconductor.
It may have an S structure.

[0021]

As described above, according to the present invention, it is possible to realize a method of driving a charge-coupled device with less feedthrough to the output side. As a result, the input range of the output amplifier and subsequent circuits can be reduced,
It contributes to improving system performance and reducing costs.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a method for driving a charge-coupled device of the present invention.

FIGS. 2 (a) and (b) are potential phase diagrams, (c),
(d) and (e) are waveform diagrams of clocks φ2, φ1, and φ3.

FIG. 3 is an explanatory diagram of a conventional method of driving a charge-coupled device.

FIGS. 4 (a) and (b) are potential state diagrams, (c),
(d) and (e) are waveform diagrams of clocks φ5, φ4, φ3.

5A is an input / output waveform diagram when the method of FIG. 1 is used, and FIG. 5B is an input / output waveform diagram when the method of FIG. 3 is used.

[Explanation of symbols]

1, 2, 3, 4: transfer gate electrode, 5: output gate electrode, 6: first ohmic junction electrode, 7: first gate electrode, 8: second gate electrode, 9: second ohmic junction electrode, 11, 12: clock signal source, 13, 14: bias power source, 15: reset signal source, 16: power source

Claims (2)

[Claims] 1. A plurality of transfer gate electrodes to which a transfer clock signal is applied, a first ohmic junction electrode for extracting charges transferred by the transfer gate electrode, and a second ohmic junction to which a DC voltage is applied. An electrode, and a gate electrode provided between the first ohmic junction electrode and the second ohmic junction electrode, to which a reset signal is applied, wherein the first ohmic junction electrode, the second ohmic junction Electrode and the gate electrode are F
In the charge-coupled device constituting the ET, a transfer clock signal for driving a final transfer gate electrode among the plurality of transfer gate electrodes and a reset signal for driving the gate electrode are set to have phases opposite to each other. A charge-coupled device characterized by the above-mentioned. 2. The charge-coupled device according to claim 1, further comprising: an output gate electrode provided with a DC voltage between the final transfer gate electrode and the first ohmic junction electrode; A DC voltage applied to the output gate electrode so that the received electric charge can pass directly below the output gate electrode and reach the first ohmic junction electrode regardless of the transfer clock signal level of the final transfer gate electrode. A charge-coupled device, wherein: