JPH09107504A - Solid-state image pickup element and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent reverse flow of signal charges when a CCD is reset by controlling a timing of a transfer clock pulse and a reset clock pulse. SOLUTION: A horizontal transfer register 1 is formed on an n-channel imbeded channel region 15 and a horizontal output gete section 6 is formed on the n-channel imbeded channel region 15. A reset gate section 11 is formed between an n-channel region between a floating diffusion region 7 and a reset drain region 10. Then the rising of a reset pulse given to the reset gate section 11 is set faster than the rising of a transfer clock pulse given to a transfer section 3 at a final stage.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device and a driving method thereof.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a final stage portion and an output portion of a horizontal transfer register of a conventional CCD solid-state image pickup device. In FIG. 7, reference numeral 1 indicates a horizontal transfer register. The horizontal transfer register 1 is provided with a plurality of transfer parts 3 each having a transfer electrode, that is, a storage electrode 2S and a transfer electrode 2T, and transfers signal charges in a horizontal direction by two-phase transfer clock pulses φH ₁ and φH _2. Is formed as. The transfer clock pulse φL given to the transfer unit 3 at the final stage
H (φH ₁ ) may be common to the transfer clock pulses φH ₁ and φH _{2 applied} to the transfer unit 3 before that, or may be applied independently. The transfer section 3 at the final stage of the horizontal transfer register 1 is connected to the floating diffusion region 7 via the horizontal output gate section 6 to which a fixed gate voltage V _HOG is applied, and the signal charge from the horizontal transfer register 1 is floated. It is transferred to the fusion area 7, converted into a charge-voltage, and output through the output amplifier 8. In the output section 9, in order to discharge the signal charge transferred to the floating diffusion region 7 to the reset drain region 10, both regions 7 and 10 are discharged.
The reset gate unit 11 to which the reset pulse φRG is applied is formed between them.

In the horizontal transfer register 1 and the output section 9, for example, the p-type well region 1 is formed on the n-type semiconductor substrate 13.
4 are formed in the n-type buried channel region 1 which forms the transfer path of the horizontal transfer register 1 in the p-type well region 14.
5 are formed. Storage electrodes 2S and transfer electrodes 2T are alternately formed on the n-type buried channel region 15 with an insulating film 16 interposed therebetween, and a pair of storage electrodes 2S is formed.
And transfer electrodes 2T are connected to form a plurality of transfer units 3.
Is formed. A p ⁻ layer 17 is formed below the transfer electrode 2T to form a potential difference.

The horizontal output gate section 6 is formed by forming a horizontal output gate electrode 18 on the buried channel region 15 to which a fixed gate voltage V _HOG , for example, a ground voltage is applied via an insulating film 16. Both floating diffusion region 7 and reset drain region 10 are n ⁺
The reset gate electrode 19 is formed on the n-type region between the regions 7 and 10 with the insulating film 16 interposed therebetween to form the reset gate portion 11.

The transfer clock pulses φH ₁ and φH ₂ and the reset pulse φRG applied to the horizontal transfer register 1 are applied at the timings shown in FIG. 8, and in particular, the transfer clock pulse φLH and the reset pulse φRG at the final stage are
It is given by starting up at almost the same timing. As a result, after the signal charge accumulated in the floating diffusion region 7 is released to the reset drain region 10, the next signal charge is transferred to the floating diffusion region 7 from the final transfer unit 3.

[0006]

By the way, as described above, in the conventional CCD solid-state image pickup device, the transfer clock pulse φLH (φH ₁ ) and the reset pulse φRG given to the final transfer unit 3 of the horizontal transfer register 1 are applied. Were rising at almost the same timing, but the reset gate section 11
Since there is a sufficient margin between the potential of the horizontal output gate section 6 and the potential of the horizontal output gate section 6, a signal charge accumulated in the floating diffusion region 7 flows back to the transfer section 3 side of the horizontal transfer register 1 at the time of resetting. There wasn't.

However, miniaturization of the CCD solid-state image sensor,
As the clock pulse becomes lower in amplitude, the reset gate unit 1
In the case of a CCD solid-state image pickup device in which the potential of 1 and the potential of the horizontal output gate section 6 are not sufficiently secured, there is a possibility that signal charges may flow back to the horizontal transfer register 1 side at the time of reset. That is, the potential level of the horizontal output gate unit 6 is modulated by the variation of the manufacturing potential or the influence of the coupling from the final stage transfer unit 3 (the broken line a in the potential diagram of FIG. 7).
However, backflow of signal charges to the horizontal transfer register 1 side is likely to occur at the time of resetting, which may lead to deterioration of image quality.

On the other hand, as shown in FIG. 9, a CCD solid-state image sensor having a structure in which the potential level of the reset gate section 11 is lower than the potential level of the horizontal output gate section 6 has been proposed. However, also in this case, when the amplitude of the clock pulse is reduced, in order to secure the dynamic range DL, when the difference d between the potential levels of the reset gate unit 11 and the horizontal output gate unit 6 is made as small as possible, As in the above example, the backflow phenomenon is likely to occur.

In view of the above points, the present invention provides a solid-state image pickup device and a driving method thereof, which prevent the signal charges from flowing back to the charge transfer register side at the time of resetting, and also have a large dynamic range. Is.

[0010]

According to a method of driving a solid-state image pickup device according to the present invention, a reset pulse applied to a reset gate section is applied more than a rising edge of a transfer clock pulse applied to a transfer section at a final stage on an output side of a charge transfer register. Try to get up faster. In this driving method, the rise of the reset pulse is made earlier than the rise of the transfer clock pulse given to the transfer unit at the final stage, whereby the signal charge can be prevented from flowing back to the transfer unit at the time of reset. At the same time, the dynamic range of the signal charge can be increased.

The solid-state image pickup device according to the present invention is configured to have a delay means for delaying the rising edge of the transfer clock pulse applied to the charge transfer register with respect to the rising edge of the reset pulse applied to the reset gate section. The delay means delays the rising edge of the transfer clock pulse given to the charge transfer register, especially the transfer section at the final stage, from the rising edge of the reset pulse, so that no backflow of the signal charge occurs at reset and the dynamic range of the signal charge is increased. An image sensor is obtained.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In the method for driving a solid-state image pickup device according to the present invention, signal charges are transferred to a charge transfer register and transferred to a charge-voltage conversion region via an output gate unit, and are transferred through a reset gate unit at reset. In the solid-state imaging device configured to emit to the reset drain region,
The rise of the reset pulse applied to the reset gate unit is made earlier than the rise of the transfer clock pulse applied to the final transfer unit on the output side of the charge transfer register.

The solid-state image pickup device according to the present invention includes a charge transfer register for transferring signal charges, an output gate section connected to the final stage of the register, and a charge-voltage for transferring the signal charges adjacent to the output gate section. A conversion region, a reset gate portion, and a reset drain region are included, and a delay unit that delays the rising edge of the transfer clock pulse applied to the charge transfer register with respect to the rising edge of the reset pulse applied to the reset gate portion is provided.

An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 show a CCD solid according to the present invention.
An example of a method for driving the image sensor will be shown. However, in the figure
The same reference numerals are given to the portions corresponding to those in FIGS. 7 and 8 described above.
Attached and shown. In this example as well, as in the case of FIG.
Transfer unit 3 having di-electrode 2S and transfer electrode 2T
, Two-phase transfer clock pulse φH₁as well as
φH _TwoHorizontal transfer to sequentially transfer signal charges in the horizontal direction
Register 1 and transfer unit 3 at the final stage of horizontal transfer register 1
A horizontal output gate unit 6 connected to and a charge-voltage conversion
Area or floating diffusion area 7 and flow
The output amplifier connected to the heating diffusion region 7.
And transferred to floating diffusion area 7.
The generated signal charge is discharged to the reset drain region 10.
And a reset gate section 11 for resetting.

The transfer unit 3 at the final stage of the horizontal transfer register 1
Transfer clock pulse φLH (φH₁) Is later
Transfer clock pulse φH applied to the previous transfer unit 3₁,
φH _TwoIt may be common with or may be given independently
Wear. A fixed gate voltage is applied to the horizontal output gate unit 6.
V_HOG, For example, ground voltage is applied, reset gate section
A reset pulse φRG is applied to 11.

The horizontal transfer register 1 is an n-type semiconductor substrate 1.
3 is formed by alternately forming the storage electrode 2S and the transfer electrode 2T via the insulating film 16 in the n-type buried channel region 15 formed via the p-type well region 14, and p ⁻ under each transfer electrode 2T. Layer 17 is formed. The horizontal output gate section 6 is formed by forming a gate electrode 18 on the n-type buried channel region 15 with an insulating film 16 interposed therebetween. Further, the floating diffusion region 7 and the reset drain region 10 are both formed of an n ⁺ layer, and the insulating film 1 is formed on the n-type region between the regions 7 and 10.
The gate electrode 19 is formed via 6 to form the reset gate portion 11.

Therefore, in this example, the reset game
The rising edge of the reset pulse φRG applied to the gate section 11,
The transfer clock supplied to the transfer unit 3 at the final stage of the horizontal transfer register
Clock pulse φLH (φH₁) Will start earlier than
Sea urchin FIG. 2 shows an example thereof. Horizontal transfer register 1
Clock pulse φH ₁, ΦH_TwoAnd the reset
Pulse φRG with the timing shown in FIG.
In particular, a transfer clock pulse φL given to the transfer unit 3 at the final stage
R rising edge of reset pulse φRG with respect to H rising edge
To advance.

According to the driving method of this embodiment, the rising edge of the reset pulse φRG applied to the reset gate unit 11 is determined from the rising edge of the transfer clock pulse φLH (φH ₁ ) applied to the final transfer unit 3 of the horizontal transfer register 1. By speeding up, when resetting, reset gate unit 1
1, the signal charges of the floating diffusion region 7 start to be released to the reset drain region 10, and the potential of the transfer unit 3 at the final stage becomes deeper after a delay. Therefore, it is possible to prevent the signal charges of the floating diffusion region 7 from flowing back to the transfer unit 3 side, and it is possible to prevent the deterioration of image quality due to the backflow.

Further, since the backflow of the signal charges does not occur at the time of reset, the dynamic range of the signal charges can be increased. In particular, the present driving method is suitable for application to a CCD solid-state image pickup device having a small size and a low drive pulse amplitude.

3 to 6 show the reset pulse φ described above.
C according to the present invention in which the rising edge of RG can be applied earlier than the rising edge of the transfer clock pulse φLH
Examples of the CD solid-state image pickup device will be shown.

In the figure, 20 is a CCD solid-state image pickup device main body, and 21 is a timing generator for generating each drive pulse. Divide the pulse from the original oscillation and reset pulse φRG and horizontal transfer clock pulse φ
H ₁ (φLH) and φH ₂ are generated, and the horizontal transfer clock pulse φH obtained from the timing generator 21.
₁ (φLH) and φH ₂ are supplied to the horizontal transfer register 1 of the CCD solid-state imaging device body 20, and the reset pulse φRG similarly obtained from the timing generator 21 is CC.
It is configured to be supplied to the reset gate unit 11 of the output unit 9 of the D solid-state imaging device body 20. Here, the pulse from the timing generator has the same phase as the CCD drive pulse.

Therefore, in the CCD solid-state image pickup device 31 according to the embodiment of FIG. 3, the delay means 24 is inserted in the supply line of the transfer clock pulses φH ₁ (φLH) and φH ₂ from the timing generator 21, and the transfer clock pulse is transmitted. φH
₁ (φLH) and φH ₂ through the delay means 24 to the CCD
Supply to the horizontal transfer register 1 of the solid-state image sensor body 20,
On the other hand, the reset pulse φRG is directly supplied to the reset gate unit 11 through the supply line. By the delay means 24, the transfer clock pulse φH
₁ (φLH) and φH ₂ are delayed from the reset pulse φRG, and the rising edge of the reset pulse φRG can be advanced from the rising edge of the transfer clock pulse φLH supplied to the transfer unit 3 at the final stage.

CCD solid-state image sensor 3 according to the embodiment of FIG.
2, interposed transfer clock pulses φH ₁ (φLH) and each capacitor element 25 in the supply line of .phi.H ₂ from the timing generator 21, the transfer clock pulses .phi.H ₁ (phi
LH) and φH ₂ are supplied to the horizontal transfer register 1 of the CCD solid-state imaging device body 20 through the capacitive element 25, while
The reset pulse φRG is supplied to the reset gate unit 11 through the supply line as it is. This capacitive element 25 allows the transfer clock pulse φH ₁ (φL
H) and φH ₂ are delayed from the reset pulse φRG, and the rising edge of the reset pulse φRG can be advanced from the rising edge of the transfer clock pulse φLH supplied to the transfer unit 3 at the final stage.

CCD solid-state image pickup device 3 according to the embodiment of FIG.
3, interposed the delay circuit 26 by the inverter to the supply line of the transfer clock pulses φH ₁ (φLH) and .phi.H ₂ from the timing generator 21, the transfer clock pulses φH ₁ (φLH), CCD and .phi.H ₂ through the delay circuit 26 The reset pulse φRG is supplied to the horizontal transfer register 1 of the solid-state imaging device body 20, while being supplied to the reset gate unit 11 through the supply line as it is.

By the delay circuit 26, the transfer clock pulses φH ₁ (φLH) and φH ₂ are reset pulse φR.
Delayed from G, the rising edge of the reset pulse φRG can be advanced from the rising edge of the transfer clock pulse φRG provided to the final stage transfer unit 3.

CCD solid-state image sensor 3 according to the embodiment of FIG.
4 is a transfer clock pulse φH ₁ (φLH) from the timing generator 21 and an output buffer circuit 27 is inserted in the supply line of φH ₂ to transfer clock pulse φH ₁
(ΦLH) and φH ₂ are supplied to the horizontal transfer register 1 of the CCD solid-state imaging device body 20 through the output buffer circuit 27, while the reset pulse φRG is supplied to the reset gate unit 11 through the supply line as it is.

By the output buffer circuit 27, the transfer clock pulses φH ₁ (φLH) and φH ₂ are delayed from the reset pulse φRG, and the rising edge of the reset pulse φRG is given to the transfer unit 3 at the final stage.
The phase can be advanced from the rise of LH.

The solid-state image pickup devices 31, 3 according to the above-mentioned embodiment
According to Nos. 2, 33 and 34, the rise of the reset pulse φRG at the time of reset can be made earlier than the rise of the transfer clock pulse φLH provided to the transfer unit 3 in the final stage, and the backflow of the signal charge can be suppressed. Also, the dynamic range of signal charges in the floating diffusion region can be increased. Therefore, it is possible to obtain a highly reliable CCD solid-state imaging device.

The present invention can also be applied to a CCD solid-state image sensor in which the potential level of the reset gate section 11 is lower than the potential level of the horizontal output gate section 6 as shown in FIG.

Further, the gate voltage V of the horizontal output gate section
_{The present} invention can also be applied to a CCD solid-state image sensor in which the _HOG is not fixed and is applied by oscillating in a phase opposite to the transfer clock pulse φLH in order to reduce the amplitude of the transfer clock pulse.

Further, in the above example, the present invention is applied to the case where the floating diffusion amplifier system is used as the output section, but it is also applicable to the case where the floating gate amplifier system is used. In this floating gate amplifier system, a floating gate region of the first conductivity type (that is, a charge-voltage conversion region) is formed adjacent to the final stage of the horizontal transfer register with a first output gate unit to which a fixed voltage is applied interposed. And the floating gate region is formed
The floating gate region is formed under the floating gate electrode, and the floating gate region is connected to the reset drain region via the reset gate portion and the second output gate to which a fixed voltage is applied. The rising edge of the reset pulse applied to the reset gate section is made earlier than the rising edge of the transfer clock pulse applied to the final transfer section of the horizontal transfer register.

In the above example, the present invention is applied to a two-dimensional solid-state image pickup device, but it can also be applied to a one-dimensional solid-state image pickup device such as a line sensor and its driving method.

[0034]

According to the method of driving the solid-state image pickup device of the present invention, it is possible to reliably prevent the backflow of the signal charges to the charge transfer register side at the time of resetting, and avoid the deterioration of the image quality due to the backflow. it can. Moreover, since the backflow can be prevented, the dynamic range of the signal charge can be increased.

According to the solid-state imaging device of the present invention, the transfer clock pulse is applied to the charge transfer register via the delay means, whereby the rising edge of the transfer clock pulse can be delayed from the reset pulse. . Therefore, it is possible to provide a highly reliable solid-state imaging device in which signal charges do not flow back at the time of resetting and image quality deterioration does not occur. Further, it is possible to provide a solid-state image sensor having a large dynamic range of signal charges.

Therefore, the present invention is preferably applied to a solid-state image pickup device in which the amplitude of a drive pulse is reduced and the size thereof is reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram and a potential diagram showing an example of a solid-state imaging device according to the present invention.

FIG. 2 is a timing diagram of drive pulses showing an example of a drive method according to the present invention.

FIG. 3 is a configuration diagram showing an embodiment of a solid-state imaging device of the present invention.

FIG. 4 is a configuration diagram showing another embodiment of the solid-state imaging device of the present invention.

FIG. 5 is a configuration diagram showing another embodiment of the solid-state imaging device of the present invention.

FIG. 6 is a configuration diagram showing another embodiment of the solid-state imaging device of the present invention.

FIG. 7 is a configuration diagram and a potential diagram of a solid-state image sensor according to a conventional example.

FIG. 8 is a timing diagram of drive pulses in a conventional example.

FIG. 9 is a potential diagram of a solid-state imaging device according to another conventional example.

[Explanation of symbols]

 1 Horizontal Transfer Register 3 Transfer Section 2S Storage Electrode 2T Transfer Electrode 6 Horizontal Output Gate Section 7 Floating Diffusion Area 8 Output Amplifier 9 Output Section 10 Reset Drain Area 11 Reset Gate Section 20 CCD Solid State Imaging Device Main Body 21 Timing Generator 24 Delay Means 25 Capacitance element 26 Delay circuit by inverter 27 Output buffer circuit 31, 32, 33, 34 Solid-state imaging device

Claims (2)

[Claims] 1. A method for driving a solid-state image pickup device, characterized in that the rising edge of a reset pulse applied to a reset gate section is set earlier than the rising edge of a transfer clock pulse applied to a final stage transfer section on the output side of a charge transfer register. . 2. A solid-state image pickup device comprising delay means for delaying a rising edge of a transfer clock pulse applied to a charge transfer register with respect to a rising edge of a reset pulse applied to a reset gate section.