JPS5913373A - Charge transfer device - Google Patents

Abstract

PURPOSE:To enable to reduce a reset drain voltage holding transfer efficiency high as it is by a method wherein potential of a transfer channel in the neighborhood of an output part is reduced by adding impurities the reverse conductive type of conductive layers forming buried channels. CONSTITUTION:Pulses phi1 are applied to electrodes 7, 15, 16, pulses phi2 are applied to electrodes 14, 8, and a pulse phiR is applied to an electrode 12 respectively. Moreover an electrode 17 is the output gate, and is applied with a DC voltage. The p type layers 18, 19, 20 are formed at the parts nearby the surface of a substrate 1. The p type layers 18, 19 are for decision of the transfer direction, and because the p type layer 20 formed on the surface of the substrate is provided under the electrode 16 and the output gate 17 of the output part, n type impurity concentration at the n type layer of the substrate coming close to an output diode 3 is reduced, and channel potentials at the upper and lower parts of the electrode 16 are reduced when the pulse phi1 is in a low level. Accordingly the reset drain voltage can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge coupled device (Charge Coup, Ie
dDevice is hereinafter referred to as CCD. ), and particularly relates to the signal charge readout output section.

CCDs are becoming widely used in analog delay lines and solid-state imaging devices, but their operating voltage must be low in order to make devices smaller, lighter, and consume less power.

is desirable. The present invention has been made in view of this point, and provides a technique for reducing the operating voltage near the output section.

First, the operating principle of the output section of a conventional CCU will be explained below.

FIG. 1 is a cross-sectional view of the two-phase drive CCD in the signal transfer direction. That is, an n-type layer 2 is formed as a buried channel on a p-substrate 1 surface, an n-type layer 3 is formed as an output diode, and an n-type layer 4 is formed as a reset drain. A polysilicon electrode 7, 8.9° 10.11.12 is formed on the n-type layer 2 with a gate insulating film 5 interposed therebetween. 7
．． 8.12 is formed of the first layer polysolicon, 9,10
．． 11 is made of a second layer of polysilicon, and is separated by an insulating film 6. Electric i9. Immediately below the gate insulating film 5 under lOO, an n-type layer 13 is formed by ion implantation or the like for transfer purposes. Electrode 7.1
0, the transfer pulse φ1 is applied to the electrode PI? A transfer pulse φ2 is applied to the electrode 12, and a recent pulse φR is applied to the electrode 12. φ5. A timing diagram of φ2°φR is shown in FIG. The electrode 11 is an output gate (hereinafter referred to as OG), to which a DC voltage is applied.
A DC voltage is also applied to. The output signal is obtained by varying the potential of the output diode 3 in accordance with the amount of signal charge.

Figure 3 shows a channel potential diagram. Here (a)
are conceptual diagrams corresponding to Figure 1, and (b) and (c) are conceptual diagrams corresponding to Figure 2.
It is a channel potential diagram at j=tb and t=tC in the figure. Since φR is at a high level at t''tb, the potential of the output diode is the potential of the reset drain 4 vRD.
K is set. - The force signal charge is accumulated under the φ1 gate because φ1 is at a high level.

On the other hand, when 1=1, φRVi is at a low level, so the output diode is in a floating state, and at this time, φ1. becomes low level, and the signal charge is transferred to the output diode 3 through OGl'l.

This changes the potential of the output diode, which becomes an "output signal."

As is clear from FIG. 3(c), in order to transfer the signal charge, it is necessary that VRD be smaller than the one-channel potential VL under the electrode 7 when φ1 is at a low level. Therefore, in order to lower the reset drain voltage and lower the voltage, it is necessary to reduce VL. To achieve this, the concentration of the n-type layer 2 that forms the buried channel can be lowered by reducing the depth, but if such a method is used, the signal charges will spread close to the surface. . Approximately 111 $ exists near the interface between silicon and the gate insulating film (Table II), and since signal charges are captured on this surface unit, surface channel CCDs have the problem of poor transfer efficiency, while buried channel CCDs have This method is used to transfer signal charges inside the substrate to avoid the influence of each surface.

However, if VL is made small, the signal charges will spread near the surface and the short transfer efficiency will decrease, as described above.

Mujiang Xiao was created in view of the above, and by applying the present invention, the transfer efficiency was kept high! ! Also, it becomes possible to reduce the reset drain voltage.

FIG. 4 shows a cross-sectional structure near the output section of an embodiment to which the present invention is applied.

An n-type layer 2 is formed as a buried channel on the l-plane of a p-substrate, an n-type layer 3 is formed as an output diode, and an n-type layer 4 is formed as a reset drain.

Polysilicon electrodes 7 . Electrode'7.8
I/'i, the first layer is made of polysilicon, the electrode 16 is made of second layer polysilicon, and the bent electrodes 14.15.
17, a third layer of polysilicon is formed. The type of transfer pulse to be applied may be the same as conventional ones, and for example, the one shown in FIG. 2 is used.

φ1 pulse is applied to electrode 7, 15, 16, φ2 pulse is applied to electrode 14
8, the φR pulse is applied at 12, respectively. Further, the electrode 17 (d) is a gate to which a DC voltage is applied. An n-type layer 18.19°20 is formed near the surface of the substrate l. Therefore, the electrode 16 of the output section and the n-type layer 20 formed on the substrate surface of the OGI"7 are the p-type layer according to the present invention. By providing the p-type layer 20, the output diode 3 The n-type concentration in the adjacent n-type layer substrate decreases, and φ
The channel potential directly under the electrode 16 when 1 is at a low level becomes small. Therefore, it becomes possible to lower the reset drain voltage.

When forming the n-type layer 20, ions are implanted in a state where the ion-implanted heads of the n-type layer 19 partially overlap, so that the @ region 19 becomes the lowest in the potential curve.

In the charge transfer device having the above structure, except for the vicinity of the output, the concentration and depth of the buried channel CCD can be kept as before, and no deterioration in transfer efficiency occurs.

Further, the p-type layer 20 can be formed by ion implantation using the polysilicon electrode 8 as a mask, and the electrode 8 and the n-type layer 20
The ends of the two parts can be made to coincide with each other, and there is no problem of potential undulations caused by overlapping or separation of these parts. Note that the n-type layers 18 and 19 may be formed at the same time, or the n-type layers 18 and 20 may be formed at the same time. Also poly7
It is clear that the same effect can be obtained even if the recon electrode 17 is formed of the first layer of polysilicon or the polysilicon electrode 14 is formed of the second layer of polysilicon.

FIG. 5 is a sectional view showing another embodiment to which the present invention is applied. Here, polysilicon electrodes 7, 8, 21, 22, 23 are formed on the n-type layer 2 with an insulating film 5 interposed therebetween.
These electrodes are separated by an insulating film 6. Electrode 7.8
．． 23 is formed of first layer polysilicon, and electrode 21.2
2 is formed of second layer polysilicon. A φ1 pulse is applied to the electrodes 7 and 22, a φ2 pulse is applied to the electrode 21.8, and a φR pulse 75 is applied to the electrode 12. For example, the baluses shown in FIG. 2 are used. Further, the electrode 23 is an output gate, and a DC voltage is applied thereto. The n-type layers 18, 19 near the surface are for directing the transfer, and the p-type layer 20 serves to reduce the channel potential directly under the electrode 22. As in the previous embodiment, the reset drain voltage can be reduced without deterioration of transfer efficiency due to the n-type layer 20. The n-type layer 20 can be formed by ion implantation using the polysilicon layers 8 and 23 as masks, and can be formed using the twisted p-type layer 19Vi polysilicon layer 8 and resist as a mask. Therefore, the ends of the polysilicon electrode 8 and the n-type layer 19, 20 are aligned, and no undulation of the bottom surface occurs.

The p-type layers 18 and 19 or 18 and 20 can be formed at the same time.

By applying the present invention as described above, low voltage operation is possible without deterioration of transfer efficiency when reading signal charges.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing the output section of a conventional CCD, Fig. 2 is a timing chart of clock pulses, and Fig. 3 is a potato-p base 2...n type near the output section of a conventional CCD. Layer (embedded channel/l/CCD) 3.
(Output diode) 4゛ 〃 (Reset train) 5. Gate insulating film 6... Insulating film 7.8, 9, 10, 11.12.14, 15.16.1
7.21, 22.23. Polysilicon electrode r3. ts, t9, 2o...P type layer agent, patent attorney Yoshihiko Fukushi (and 2 others)
f-fc Fig. 2

Claims (1)

[Claims] (1) In a buried channel charge transfer device, the potential of the transfer channel near the output section is reduced by adding an impurity of a conductivity type opposite to that of the conductive layer forming the buried channel. Characteristic charge transfer device. 2. Addition of an impurity having a conductivity type opposite to that of the conductive layer forming the buried channel is formed at a transfer electrode or at a position using a transfer electrode and a resist as a mask. The charge transfer device described in Section 1. )