JP2910648B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a solid-state imaging device FIELD OF THE INVENTION, in particular improves the transfer efficiency of signal charge, a solid-state imaging device capable of preventing deterioration of the transfer efficiency when an image of low luminance subject.

[0002]

2. Description of the Related Art A conventional solid-state imaging device having a charge transfer device accumulates a signal charge obtained from an optical signal in a photoelectric conversion element, transfers the signal charge by a vertical transfer register, and further transfers the signal charge from a plurality of vertical transfer registers. The transferred signal charges are transferred by a horizontal transfer register, and output from the floating diffusion capacitance section to an output amplifier. For example, as shown in FIG. 9, the layout of the impurity concentration at the joint between the vertical transfer register 10 and the horizontal transfer register 2 is shown in FIG.
, Transfer electrodes including a first gate 3 and a second gate 4 are arranged. FIGS. 10A and 10B are cross-sectional views of a structure including the first and second gates.
It is sectional drawing corresponding to I and JJ line. A barrier region including an N layer 5 and an N ⁻ layer 6 is formed on a P-type substrate 1. A first gate 3 is provided on the N layer 5, and a second gate 4 is provided on the N ⁻ layer 6. Is formed through. Drive pulses φH1 and φH2 are alternately applied to the transfer electrodes at timings as shown in FIG. As a result, the potentials of the line segments II and JJ at t = t1 in the drawing are as shown in FIGS. 11B and 11C. The output terminal of the transfer electrode of the horizontal transfer register 20 is configured as an output gate, to which a DC voltage is applied to prevent noise from entering the output amplifier.

As described above, the transfer electrodes to which the drive pulses φH1 and φH2 are applied are alternately arranged, and are separated from each other by a barrier region in each electrode. Therefore, the transfer electric field is strengthened, and the signal charges are easily transferred. And
The signal charge transferred to the vertical transfer register is transferred in the transfer area of the horizontal transfer register 20 as shown by a signal transfer path indicated by an arrow line L3 in FIG. The potential fluctuation of the section 30 is amplified by the output amplifier 40 and output to an external signal processing circuit (not shown). In this case, the width of the horizontal transfer register 20 is determined by the maximum transfer charge amount. When the signal charge is small, it is considered that the signal charge passes through the path having the deepest potential in the horizontal transfer register 20, that is, the center of the potential shown in FIG. The transfer path L3 indicates this.

[0004]

As described above, in the charge transfer register of the conventional solid-state imaging device, when the signal charge is small, the signal passes through the center of the low potential path. Are transferred in a so-called large turn toward the center of the horizontal transfer register 20, as indicated by an arrow line L3 in FIG. 9, and the signal charge transfer path becomes longer. Therefore, when an image of a low illuminance subject having a small signal charge is taken, the path of the signal charge becomes long, and the transfer time is increased by that amount, causing transfer deterioration and deteriorating the image quality. In the case of high-frequency driving, since the transfer electric field is limited by the number of electrodes or the length of one electrode, transfer deterioration occurs, and a problem occurs in that the resolution deteriorates when a low-illuminance subject is imaged. Further, when the transfer width of the horizontal transfer register is wide, the transfer speed is degraded by the straight line of the floating diffusion capacitance part, which causes a problem that the resolution is degraded. In addition, when the driving voltage of the horizontal transfer register is increased to solve these problems, the power consumption of the driving circuit increases, and image defects become visible due to heat generation and the activation of the crystal defects of the elements accompanying the heating. There is a problem.

It is an object of the present invention to provide a solid-state image pickup device which has improved transfer efficiency, especially when signal charges are small such as when a low-illuminance subject is imaged.

[0006]

SUMMARY OF THE INVENTION The present invention is directed to a photoelectric conversion device.
Vertical transfer of multiple columns to transfer the obtained signal charge
Registers and one end of these vertical transfer registers
A horizontal transfer register coupled in an orthogonal state,
The impurity layer forming the transfer region of the horizontal transfer register includes
Split at least in the direction perpendicular to the horizontal transfer direction
Divided area on the side closer to the vertical transfer register side
Has a deeper potential than the divided area on the far side
And the side close to the vertical transfer register.
Area extends to one end area of the vertical transfer register.
The presence of multiple regions with different extended impurity concentrations
It is characterized by.

Here, a transfer electrode of the horizontal transfer register is provided.
Floating signal that converts the signal charge transferred by the
And an output amplifier for amplifying and outputting this voltage signal.
And the floating diffusion capacitance section includes the vertical transfer register.
It is arranged at the end of the divided area closer to the data area.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a first embodiment of the present invention, particularly a plan view of an impurity concentration layout at a joint between a part of a vertical transfer register 10 and a horizontal transfer register 20, and FIGS. 2 (a) and 2 (b). 2) and 2 (c) are cross-sectional views corresponding to lines AA, BB, and CC in FIG. 1, respectively. The point that the first gates 3 and the second gates 4 are alternately arranged on the main surface of the P-type semiconductor substrate 1 via the gate insulating film 2 is the same as before. Further, the same applies to the point that an N layer 5 is formed on the main surface of the P-type semiconductor substrate 1 and an N ²⁻ layer 7 is formed immediately below the second gate 4 to form a barrier region. However, the region immediately below the first gate 3 is divided into two in the gate width direction, that is, in the direction perpendicular to the signal charge transfer direction of the horizontal transfer register 20, and in the region on the side of the vertical transfer register 10, N layers are formed. 5
However, the region farther from the vertical transfer register is configured as an N ⁻ layer 6 having a lower impurity concentration. Therefore, in this horizontal transfer register, N ^- type regions having different impurity concentrations such as the N layer 5, the N ⁻ layer 6 and the N ²⁻ layer 7 exist, so that the barrier region is configured in two stages. Become. Further, the floating diffusion capacitance section 30 on the side of the horizontal transfer register 20 to which the signal charges are transferred is disposed at the end near the vertical transfer register.

FIG. 3 shows a method of manufacturing such a horizontal transfer register 20. FIG. 3 shows only the X region in FIG. First, as shown in FIG. 3A, an N-type impurity is implanted into the P-type semiconductor substrate 1, and then, as shown in FIG. Further, a gate insulating film 2 is formed. Then, as shown in FIG.
Of the region where the first gate 3 is formed, only the region on the side of the vertical transfer register 20 is masked and a P-type impurity is implanted at a low concentration to form the N ⁻ layer 6. Then, as shown in FIG. 3D, polysilicon is selectively formed to form a first gate 3.
And this is covered with an insulating film. Further, as shown in FIG. 3E, using the first gate 3 as a mask, a P-type impurity is implanted at a low concentration, and an N ²⁻ layer 7 is formed in a region where the second gate is to be formed. Then, as shown in FIG. 3F, the second gate 4 is formed by selectively forming polysilicon, thereby forming the horizontal transfer register 20 shown in FIGS.

In this case, the barrier regions formed in two stages are set so as to have half the impurity concentration of the conventional one-stage barrier region. For example, if the P-type impurity implantation amount at the time of one-step formation is 8E11 cm ⁻² , the implantation amount at the time of implanting each of the low-concentration P-type impurities is 4E11 cm ⁻² .
Therefore, the N ⁻ layer 6 into which the P-type impurity is implanted once.
Is 4E11 cm ^-2 , and the N ² -layer 7 implanted twice is 8
E11 cm ⁻² and the above-described two-stage barrier region is formed.

Therefore, φH1 and φH as shown in FIG.
2 are applied, AA, BB, CC in FIG.
FIG. 4A is a potential diagram of signal charges corresponding to each of the lines.
To (c). When this barrier region No. that shown in FIG. 11 (c) is compared with the conventional potential of one stage, Po
It can be seen that the region with a deep tension is shifted to the vertical transfer register 10 side. As described above, since the small signal charges pass through the center position of the region having the deepest potential , the signal charge transfer path is located closer to the vertical transfer register 10 as shown by the arrow line L1 in FIG. It turns into a small turning state, and is transferred to the floating diffusion capacitance section 30 in that state, and is output to the output amplifier 40 from here. Therefore, the horizontal transfer register 20
The transfer distance of the signal charge in the above is greatly shortened, whereby the transfer time is shortened by the shortened transfer distance, the transfer efficiency is improved, and the deterioration of the image quality is prevented. Also, since the actual transfer width is narrowed,
It is also possible to prevent the transfer speed from decreasing immediately before the floating diffusion capacitance unit 30.

The potential depth shown in FIG.
Due to the difference, an electric field is generated in the transfer direction of the horizontal transfer register 20 and in the vertical direction.
On the output side of 0, an electric field perpendicular to the transfer direction is applied in addition to the sum of the electric field in the transfer direction and the electric field due to the narrow channel effect, and the transfer speed of the signal charge is further increased. This electric field is apparent from comparing the potentials in FIGS. 4A and 4B. As a result, the transfer speed of the entire signal charge can be improved, the transfer efficiency can be increased, and the image quality and resolution can be improved. Since the transfer time of the signal charge is obtained by integrating the reciprocal of the transfer electric field value in the transfer section, the overall transfer speed of the signal charge is improved by shortening the signal charge transfer path and strengthening the transfer electric field.

FIG. 5 is a plan view of an impurity concentration layout of a joint between a vertical transfer register and a horizontal transfer register according to a second embodiment of the present invention. In this embodiment, the point that a barrier region is formed immediately below the first gate 3 in a direction perpendicular to the transfer direction of the horizontal transfer register 20 is the same as that of the first embodiment, but just below the second gate 4. Also forms a barrier region in the transfer direction of the horizontal transfer register 20.
That is, DD, EE, FF, and G are shown in FIGS.
As shown in the cross-sectional structures corresponding to the G and HH lines, on the side close to the vertical transfer register 10, N layers 5 and N ⁻ layers 6 are formed immediately below the first gate 3 in a direction perpendicular to the transfer direction. Immediately below the second gate 4, an N ²⁻ layer 7 and an N ³⁻ layer 8 are formed side by side in the transfer direction. On the side farther from the vertical transfer register, an N ²⁻ layer is formed immediately below the first gate, and an N ³⁻ layer is formed immediately below the second gate. Therefore, in the cross-sectional structure in the direction perpendicular to the transfer direction of the horizontal transfer register, the first
Immediately below the gate 3, the N layer 5, the N ⁻ layer 6, and the N ²⁻ layer 7
Is formed. Thus, in this structure, two-stage barrier regions are formed in the transfer direction of the horizontal transfer register, and three-stage barrier regions are formed in the vertical direction.

FIG. 7 shows a method of manufacturing the horizontal transfer register according to the second embodiment. This figure shows the area X in FIG. First, as shown in FIG. 7A, an N-type impurity is implanted into the P-type semiconductor substrate 1, and a P-type impurity is further implanted to perform element isolation 50. Further, a gate insulating film 2 is formed. Next, as shown in FIG. 7B, of the regions where the first gate 3 is formed, only approximately a half of the region on the side of the vertical transfer register 10 is masked, and a P-type impurity is implanted at a low concentration.
^-Forming layer 6; Next, as shown in FIG. 7C, the mask is slightly wider in the direction perpendicular to the transfer direction, including the mask.
Then, a P-type impurity is implanted at a low concentration by masking to cover the respective regions of / 2 to form the N ²⁻ layer 7. Then, FIG.
As shown in (d), polysilicon is selectively formed to form the first gate 3, and this is covered with an insulating film. Further, FIG.
As shown in (e), the first gate 3 is used as a mask to implant a P-type impurity at a low concentration. Thus, the N ² -layer 7 and the N ³ -layer 8 are formed in the region where the second gate is formed. To form Then, as shown in FIG. 7 (f), polysilicon is selectively formed to form the second gate 4, thereby forming the horizontal transfer register 20 of FIG.

Therefore, φH1 and φH as shown in FIG.
2 are applied, DD, EE, and F in FIG.
The electric potential diagrams of the signal charges corresponding to the F and GG lines are as shown in FIGS. 8A, 8B, 8C, and 8D, and a three-stage potential difference occurs. This what barrier region shown in FIG. 11 is a conventional one-stage, or when the barrier region shown in FIG. 4 is compared with the potential of the first embodiment of the two-stage, potentiometer
It can be seen that the deepest region is further shifted to the vertical transfer register side. Accordingly, as shown by the arrow L2 in FIG. 5, the signal charge transfer path is further turned to a smaller position closer to the vertical transfer register side, and the transfer distance is further greatly reduced. As a result, the transfer time is shortened by the further shortening of the transfer distance as compared with the second embodiment, the transfer efficiency is improved, and the deterioration of the image quality is prevented. Further, since the substantial transfer width is narrowed, it is possible to prevent the transfer speed from decreasing immediately before the floating diffusion capacitance portion.

Further, an electric field is generated in the vertical direction and the transfer direction of the horizontal transfer register 20 due to the potential difference shown in FIG. 8 (d). As in the first embodiment, an electric field perpendicular to the transfer direction is applied in addition to the sum of the electric fields due to the channel effect, and the transfer speed of the signal charge is further increased as in the first embodiment. In the second embodiment, the electric field is evident from comparing the electric fields in FIGS. 8A, 8B, and 8C. As a result, the transfer speed of the entire signal charge can be improved, the transfer efficiency can be increased, and the image quality and resolution can be improved.

Furthermore, in this embodiment, since the number of steps in the barrier region is increased in each of the transfer direction and the direction perpendicular thereto, the number of electrodes is equivalently increased. For this reason, the portion where the potential is flat in the transfer direction, that is, the portion where the electric field is weak, is reduced, and the length of each electrode is shortened, and the transfer under each electrode is performed by the fringe electric field by the adjacent electrode. The electric field is improved and the transfer efficiency is improved.

In each of the above embodiments, an example in which the present invention is applied to a horizontal transfer register is shown. However, the present invention can be similarly applied to a vertical transfer register and other CCD type charge transfer registers. Transfer efficiency can be improved.

[0019]

As described above, according to the present invention, the horizontal
The impurity layer constituting the transfer region of the transfer register has a small
At least it is divided in the direction perpendicular to the horizontal transfer direction,
The divided area closer to the vertical transfer register side is farther
Is configured so that the potential is deeper than
And the area near the vertical transfer register is
Extended into one end area of the vertical transfer register
Configurations where multiple regions with different impurity concentrations exist
Since that, it is possible to enhance the transfer direction field of the signal charge, and the electric field is formed also in the transfer direction and the direction perpendicular it is possible to transfer signal charges in a small turn state
As a result, the transfer speed of signal charges can be improved. As a result, the transfer efficiency is improved, and the transfer efficiency is not degraded even when the signal charge is low when the low-illuminance subject is imaged, that is, the image quality and the resolution are improved.
Further, it is possible to prevent an increase in power consumption and an occurrence of an image defect without increasing the drive voltage of the transfer register.

[Brief description of the drawings]

FIG. 1 is a plan view showing a layout of an impurity concentration according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional configuration diagram corresponding to lines AA, BB, and CC in FIG. 1;

FIG. 3 is a plan view showing a step of manufacturing the transfer region of FIG. 1;

FIG. 4 is a potential diagram for each of lines AA, BB, and CC in FIG. 1;

FIG. 5 is a plan view of an impurity concentration layout according to a second embodiment of the present invention.

6 is a cross-sectional configuration diagram corresponding to lines DD, EE, FF, GG, and HH in FIG. 5;

FIG. 7 is a plan view showing a step of manufacturing the transfer region of FIG. 5;

8 is a potential diagram for each of the lines DD, EE, FF, and GG in FIG.

FIG. 9 is a plan view of an impurity concentration layout of a conventional transfer register.

10 is a sectional configuration diagram corresponding to line II and JJ in FIG. 9;

FIG. 11 is a potential diagram at each of lines II and JJ in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 Gate insulating film 3 1st gate 4 2nd gate 5 N layer 6 N ^- layer 7 N2 ^- layer 8 N3 ^- layer 10 Vertical transfer register 20 Horizontal transfer register 30 Floating diffusion capacity part 40 Output amplifier 50 element separation

Claims (1)

(57) [Claims] 1. A vertical transfer register of a plurality of columns for transferring signal charges obtained by photoelectric conversion, a horizontal transfer register connected in an orthogonal state at one end of the vertical transfer registers, A floating diffusion capacitance section that converts a signal charge transferred by the transfer electrode into a voltage signal, and an output amplifier that amplifies and outputs the voltage signal; and an impurity layer that forms a transfer region of the horizontal transfer register includes: It is divided at least in a direction perpendicular to the horizontal transfer direction, and the divided region closer to the vertical transfer register side is configured to have a deeper potential than the divided region farther away, and closer to the vertical transfer register. There are a plurality of regions having different impurity concentrations, the regions on the side extending to one end region of the vertical transfer register. The solid-state imaging device according to claim 1, wherein the dispersion unit is disposed at an end of the divided region closer to the vertical transfer register.