JPH04207077A - Manufacture of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To obtain an element separation region in spacer width by performing ion-implantation of boron for a transfer electrode which is formed by a poly Si, etc., and phosphor to a side wall insulation film which is formed on a side wall of the transfer electrode in self-aligned manner. CONSTITUTION:A transfer electrode 4 is used as a mas and boron B is ion- implanted to a substrate 6, thus forming a p<+> region. Then, an SiO2 film 8a is deposited on an entire surface by the CVD method, etc., and then etchback is performed, thus enabling the SiO2 film 8 to remain on a side wall of the transfer electrode 4. After that, the side wall insulation film 8 which is located at an opposite side of an element separation side is eliminated. Then, using the SiO2 film which remains on this side wall as a mask and performing ion- implantation of a phosphor P, an n<+> region is formed. Then, a region where P is ion-implanted becomes an n<+> type accumulation diode 1 and only a region below the side wall insulation film 8 where B rather than P is implanted becomes a p<+> type element separation region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a solid-state image sensor, and particularly to a method for manufacturing a solid-state image sensor in which a method for forming an element isolation region is improved.

(Prior Art) A CCD type solid-state image sensor has functions such as photoelectric conversion, signal charge accumulation, and signal charge transfer, and in the case of an interline transfer type, it has a configuration as shown in FIG. has been done. That is, storage diodes 1 are arranged in a two-dimensional matrix, a plurality of vertical CCD channels 2 are provided adjacent to them, and element isolation regions 3 are provided between adjacent elements. Transfer electrodes 4.5 are provided above these. When viewed horizontally, the storage diode section (SD).

Signal readout gate section (FSG), signal charge transfer section (VC
CD), and element isolation portions (CS) are repeated in succession.

FIG. 8 shows a cross section taken along line BB' in FIG. 7 and its potential profile. n on the surface layer of the p-type semiconductor substrate 60
A storage diode of type 1, an n+ type COD channel 2 and a p type element separation region 3 are formed, and a transfer electrode 4 made of poly-Si is formed on the substrate 6 with a gate oxide film 7 interposed therebetween. Here, a part of the transfer electrode 4 also serves as a signal output gate 4a.

In this type of solid-state imaging device, the method for forming the element isolation region 3 is as follows. First, an n region is formed by ion-implanting P or the like at a location away from the transfer electrode 4 using a photomask. After that, PolyS
A method was used in which B was ion-implanted in a self-aligned manner in i and the p region and n region were shifted.

However, since this method uses a photomask to form the element isolation region, it is necessary to design the mask by adding the conversion difference and relative alignment error to the margin.

For this reason, it is difficult to shorten the width a of the element isolation region shown in FIG. 8, and there is a limit to the reduction of the element isolation width and the uniformity of the finished product. In order to increase the number of pixels and miniaturize the device without deteriorating the device characteristics such as sensitivity and smear, is it necessary to form the device isolation region, which is an inactive region, narrowly? could not be achieved.

(Problems to be Solved by the Invention) As described above, in the conventional device isolation region forming method in which ion implantation is performed using a photomask, margins due to conversion differences and relative alignment errors are required when designing the mask. Therefore, it has been difficult to stably form a narrow element isolation.

The present invention has been made in consideration of the above circumstances, and its purpose is to manufacture a solid-state imaging device that does not require a margin due to alignment error and can further reduce the width of the device isolation region. The purpose is to provide a method.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to
The purpose is to form an element isolation region with only self-aligned lines.

That is, in the present invention, a storage diode, C
In a method for manufacturing a solid-state imaging device, which includes forming a CD channel and an element isolation region and also forming a transfer electrode on a substrate, a step of forming a transfer electrode for transferring signal charges on a semiconductor substrate, and a step of forming a transfer electrode on a semiconductor substrate. A process of doping n-type impurities into the semiconductor substrate using the insulating film and the transfer electrode as a mask, and forming an insulating film on at least one side of the transfer electrode with self-alignment, and doping the semiconductor substrate with n-type impurities using the insulating film and the transfer electrode as a mask. The method is characterized in that an n-type storage diode is formed in the region doped with both pm impurity and n-type impurity, and a p-type element isolation region is formed in the region doped only with n-type impurity.

(Function) According to the present invention, the substrate surface is doped only with n-type impurities by doping with n-type impurities using only the transfer electrode as a mask and doping with n-type impurities using the transfer electrode and sidewall insulating film as masks. A region doped with an n-type impurity and a region doped with both n-type impurities are formed. Here, if the doping amount of the n-type impurity is made sufficiently larger than the doping amount of the n-type impurity, the region doped with both the n-type impurity and the n-type impurity becomes an n-type (storage diode). Therefore, it is possible to form a p-type element isolation region only under the sidewall insulating film using a self-line.
It becomes possible to narrow the width of the element isolation region.

That is, by self-aligningly implanting B into a transfer electrode formed of poly-Si or the like and P into a sidewall insulating film (spacer) formed on the sidewall of the transfer electrode, the width of the spacer can be adjusted. Accordingly, the n-type regions and the n-type regions are formed to be shifted from each other to obtain an element isolation region having a spacer width.

Since this method can form an element isolation region without using a mask that requires patterning by photolithography or the like, it is possible to obtain an element isolation region that is narrower and more uniform than conventional methods.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a plan view showing a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention, and FIG. 2 is a plan view taken along arrow AA' in FIG.
It is a figure showing a cross section and a potential profile. The basic configuration is the same as that of the conventional element, and as shown in Figure 1, when viewed in the horizontal direction, there are a storage diode section (SD), a signal readout gate section (FSG), a signal charge transfer section (VCCD).
), the element isolation portions (CS) are repeated and continuous.

Further, as shown in FIG. 2, an n''' type storage diode 1, an n+ type CCD channel 2, and a p+ type element isolation region 3 are formed on the surface layer of the p type semiconductor substrate 6.
A transfer electrode 4 made of poly-Si is formed thereon with a gate oxide film 7 interposed therebetween. Here, a part of the transfer electrode 4 also serves as a signal readout gate 4a.

Further, a sidewall insulating film 8 is formed at the end of the transfer electrode 4 on the signal readout gate side, and the element isolation region 3 is formed under this insulating film 8 as a self-aligning line.

The potential profile in this structure is similar to that of the conventional device described above, and it is clear that it functions as a solid-state imaging device. Although not shown in the figure, a horizontal signal charge transfer section (HCCD) is disposed at an end of the vertical signal charge transfer section (VCCD). Also,
Although the storage diode section (SD) may also have a photoelectric conversion function, it is more preferable to form a stacked solid-state imaging device in which a photoelectric conversion film is stacked on the structure shown in FIG.

Next, a method of manufacturing the above-mentioned example element will be explained with reference to FIG. First, as shown in FIG. 3(a), S
It is assumed that an n+ type CCD channel 2 is formed on the surface of the i-substrate 6, and a transfer electrode 4 is formed on the CCD channel 2. From this state, using the transfer electrode 4 as a mask, boron (B) ions are implanted into the substrate 6 to form a p'' region.

Next, as shown in FIG. 3(b), a 5in2 film 8a is deposited over the entire surface by CVD or the like.

Next, this 5IO2 film 8a is etched and hacked to form an 8102 film 8 on the side wall of the transfer electrode 4, as shown in FIG. 3(C).
leave. Thereafter, the sidewall insulating film 8 on the side opposite to the element isolation side is removed. Then, using 5iO2H8 remaining on this side wall as a mask, phosphorus (P) is ion-implanted to form an n'' region.

Here, the region into which P ions are implanted becomes the n+ type storage diode 1, and only the region under the sidewall insulating film 8 into which only B is implanted without P becomes the p+ type element isolation region 3.

Then, the width of the element isolation region 3 is the same as the width of the sidewall insulating film 8, and becomes extremely narrow.

As described above, in the method of this embodiment, since the element isolation region 3 can be formed by self-line, there is no need to take into account misregistration when forming the element isolation region 3.
width can be narrowed. Therefore, it is possible to increase the number of pixels and miniaturize the device without deteriorating the characteristics of the device such as sensitivity and smear, and its usefulness is enormous.

FIG. 4 is a diagram showing a schematic configuration and potential profile of a second embodiment of the present invention.

Note that the same parts as in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted.

This embodiment differs from the first embodiment described above as follows:
The gate oxide film of the transfer electrode portion on the signal readout gate side is formed thinner than that on the vertical CCD side. in this case,
When a readout voltage is applied to the transfer electrode 4 (signal readout gate 4a), the potential of the readout region is strongly influenced by the gate, so it is possible to eliminate the potential barrier on the signal readout side and perform signal readout faster. Become.

FIG. 5 is a diagram showing a schematic configuration and potential profile of a third embodiment of the present invention.

Note that the same parts as in FIG. 2 are given the same reference numerals, and detailed explanation thereof will be omitted.

This embodiment differs from the first embodiment described above as follows:
This is because the sidewall insulating film 8 is left on both ends of the transfer electrode 4. At this time, as shown in the potential diagram, the height of the potential barrier on the signal reading gate side is formed to be lower than the potential barrier on the element isolation part between the vertical CCD and the storage diode on the opposite side. , to prevent the barrier on the vertical CCD side from disappearing even when reading signals.

FIG. 6 is a diagram showing a schematic configuration and potential profile of a fourth embodiment of the present invention.

Note that the same parts as in FIG. 5 are given the same reference numerals, and detailed explanation thereof will be omitted.

This embodiment differs from the third embodiment described above as follows:
In this method, ions of, for example, n-type P or As are implanted at the position where the barrier is generated so as to eliminate the potential barrier generated on the signal readout gate side. Thereby, even if the sidewall insulating film 8 is formed on both ends of the transfer electrode 4, the potential barrier on the signal readout side can be reliably lowered, and the signal readout can be performed reliably.

Alternatively, as explained in the second embodiment, the gate oxide film 7 on the signal readout side may be formed thin.

Note that the present invention is not limited to the embodiments described above. In the examples, either the p-type head region was formed first using the transfer electrode as a mask, or the n-type region was first formed using the transfer electrode and sidewall insulating film as a mask, and then the sidewall insulating film was removed to form the p-type head region. Alternatively, a region may be formed. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, the element isolation region can be formed using only self-alignment lines without using a photomask, etc., and there is no need to take a margin due to alignment error. The width of the separation region can be made shorter, and it becomes possible to manufacture a solid-state imaging device that can increase the number of pixels and be miniaturized without deteriorating device characteristics such as sensitivity and smear.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a schematic configuration of a solid-state image sensor according to a first embodiment of the present invention, FIG. 2 is a diagram showing a cross section taken along arrow A-A in FIG. A sectional view showing the manufacturing process of the same embodiment, FIG. 4 is a second embodiment of the present invention.
*5 is a diagram showing the schematic configuration and potential profile of the third embodiment of the present invention, and Figure 6 is the schematic configuration of the fourth embodiment of the present invention. FIG. 7 is a cross-sectional view showing a schematic configuration of a conventional solid-state image sensor, and FIG. 8 is a cross-sectional view taken along arrow B-B in FIG. 7 and a potential profile. DESCRIPTION OF SYMBOLS 1... Storage diode, 2... Vertical CCD channel, 3... Element isolation region, 4.5... Transfer electrode, 6... Semiconductor substrate, 7... Gate oxide film, 8...・Side wall insulation film. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 ■ Kidney Figure 2 Figure 3 Figure 5 Figure 7

Claims (1)

[Claims] A step of forming a transfer electrode for transferring signal charges on a semiconductor substrate, and a step of forming a transfer electrode on the semiconductor substrate using the transfer electrode as a mask.
a step of doping with a type impurity, and a step of forming an insulating film on at least one side of the transfer electrode by self-alignment, and doping the semiconductor substrate with an n-type impurity using the insulating film and the transfer electrode as a mask, n-type impurity and n-type impurity doping region
1. A method of manufacturing a solid-state imaging device, comprising: forming a p-type storage diode, and forming a p-type element isolation region in a region doped only with p-type impurities.