JP3247163B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device,
In particular, it relates to a highly miniaturized photosensitive area of a CCD area sensor.

[0002]

2. Description of the Related Art A solid-state imaging device is an LSI having functions of photoelectric conversion, accumulation, and transfer, and the degree of integration on a semiconductor substrate has been remarkably improved in recent years. FIG. 14 shows an example of a conventional solid-state imaging device proposed by the inventor (Japanese Patent Application No. 3-11 / 1990).
No. 221). An N-type silicon semiconductor substrate 1 is used as a semiconductor substrate, and a P-type impurity diffusion region P
^- to form a well 2. A pixel portion 5, a charge transfer shift register portion 3, a control gate portion 9, and an element isolation region 10 are formed on a semiconductor substrate.
^A buried channel 4 is formed; A P ⁺ impurity diffusion region 52 is formed apart from one side of the buried channel 4. An N ⁺ buried photodiode 51 is formed below and in contact with impurity diffusion region 52. The photodiode 51 partially extends to the main surface of the semiconductor substrate and is exposed to the main surface. The main surface of the semiconductor substrate 1 is covered with an insulating film 7 such as silicon oxide, and a transfer electrode 31 such as polysilicon or polycide is formed on the buried channel 4 via the insulating film 7. The control gate electrode 6 is formed on the transfer electrode 31 and its periphery via an insulating film.

If the control gate electrode 6 is formed between the transfer electrode 31 and the pixel section 5 and at least on a portion of the photodiode 51 exposed on the main surface of the semiconductor substrate, the function of the control gate electrode 6 is achieved. However, in this conventional example, the control gate electrode 6 has the above-described structure because it also serves as an optical shield film. The control gate electrode 6 is covered and protected by an insulating protective film 12 such as a silicon oxide film. A P barrier well 8 having an impurity concentration higher than that of the P well 2 is formed around the buried channel 4 to prevent carriers generated around the pixel portion 5 from flowing into the buried channel 4 and improve smear characteristics. . That is, a pixel portion is constituted by the photodiode 51 and the impurity diffusion region 52,
The charge transfer shift register section 3 is constituted by the transfer electrode 31 and the buried channel 4, and the transfer of signal charges is controlled between the transfer electrode 31 and the photodiode 51 and the control gate electrode 6 thereon. A region of the buried channel 4 opposite to the control gate portion 9 constitutes a control gate portion 9 and is an element isolation region 10 in which a P ⁺ impurity diffusion region 52 of another element is formed. ing. The P well 2 is thinned under the photodiode 51 as shown. This makes it easier for excess charges to flow into the semiconductor substrate 1.

FIG. 15 shows an example of another conventional solid-state imaging device. Since the solid-state imaging device in FIG. 14 is formed on a flat semiconductor substrate surface, there is a limit to miniaturization. In this example, a trench is formed on the surface to achieve further miniaturization. A trench is formed on the surface of the P well 2 of the N-type silicon semiconductor substrate 1, and a buried channel 4 is formed on the bottom and side walls thereof. A control gate portion 9 is provided adjacent to one side of the trench, and a pixel portion 5 including a photodiode 51 and a P ⁺ impurity diffusion region 52 is formed adjacent to the control gate portion 9. An element isolation region 10 is formed adjacent to one side of the trench opposite to the one side. An insulating film 7 of silicon oxide or the like is formed on the surface of the semiconductor substrate 1 including the inside of the trench, and a buried channel 4, a control gate portion 9, and an element isolation region 10 are formed on the insulating film 7 from polysilicon or the like. Transfer electrode 31 is formed. The optical shield film 11 is formed on the transfer electrode 31 via an insulating film 71. Transfer electrode 3
The portion covering the control gate portion 9 is used as a control gate electrode. The optical shield film 11 is covered and protected by an insulating protective film 12 such as a silicon oxide film or a nitride film. The pixel section 5 has a buried photodiode structure as in the case of FIG. As shown in the figure, the light shield film 11 has an opening in the pixel portion 5 so that the incident light is applied only to the embedded photodiode portion 3.

As described above, in both the case of FIG. 14 and the case of FIG. 15, the photodiode formed on the surface of the silicon semiconductor substrate is in contact with the silicon oxide film formed on the surface thereof, so that the depletion layer formed there is formed. Of course comes into contact with this oxide film. Therefore, the current generated from the level at the silicon-silicon oxide film interface greatly affects the output current in the dark.
A buried photodiode has been considered as a method for reducing the dark current from the photodiode.
That is, a P-type high-concentration impurity diffusion region is formed between the silicon oxide film and the photodiode. Photo Diode
Silicon to cover the surface of the gate with a P ⁺ impurity diffusion region.
The silicon oxide film interface is separated from the photodiode.
Therefore, since the depletion layer does not extend to the interface, the level at this interface has a significantly reduced effect on dark current. Therefore, if this structure is adopted, it is possible to reduce the dark current to about 1/10 as compared with the conventional structure without using a buried photodiode.

[0006]

In the solid-state imaging device having the structure shown in FIG. 14, the embedded photodiode width is L1,
Assuming that the control gate length is L2, the charge transfer shift register width is L3, and the element separation width is L4, the width of one pixel, that is, the pixel pitch Ph is L1 + L2 + L3 + L4.
A typical example of the current microfabrication technology is as follows.
Since 1 and L3 are approximately equal, about 2 μm, and L2 and L4 are about 1 μm, Ph is about 6 μm. 40
Since the horizontal pitch is about 5 μm in a 10,000 pixel sensor or a 2 million pixel sensor for HDTV, it is extremely difficult to manufacture such a sensor without deteriorating its characteristics.

Therefore, a solid-state image pickup device having the structure shown in FIG. 15 has been developed. In this structure, the buried channel 4 of the charge transfer shift register 3 is formed along the inner wall of the trench. Compared to the conventional case where it is formed on a flat portion, the accumulated charge amount per unit length in the horizontal direction increases. However, since the control gate portion and the element isolation region are formed on the semiconductor substrate on the same plane as the pixel portion, the pixel pitch is improved because the width of the charge transfer shift register can only be reduced by improving the integration degree in the horizontal direction. No improvement in the degree of integration in the horizontal direction is observed. Also, since the buried photodiode 51 and the buried channel 4 are close to each other,
Carriers generated below the buried photodiode easily flow to the buried channel 4, and as a result, the smear characteristics often deteriorate significantly. Further, a P ⁺ impurity diffusion region 52 formed on a buried photodiode which has been considered as a method of reducing dark current (see FIG. 14)
May be displaced from the buried channel 4 and the buried photodiode 51. In such a case, a potential barrier is generated between the control gate section 9 and the pixel section 5, and in order to transfer the charges generated in the pixels to the charge transfer shift register section 3, a considerably high read pulse is required. Has to be applied to the control gate electrode 6. The present invention has been made in view of such circumstances, and has a structure in which the integration degree is improved, the smear characteristic is excellent, and the transfer of the signal charge from the pixel to the charge transfer shift register is facilitated. It is intended to provide a manufacturing method thereof.

[0008]

The present invention is characterized in that a trench is formed in a semiconductor substrate on which a solid-state imaging device is formed, and a pixel portion is formed at the bottom. The buried photodiode of the pixel portion formed at the bottom is extended, and the photodiode is arranged so as to be below the buried channel of the charge transfer shift register. It is characterized in that charges are transferred by causing punch through between the buried channel and the buried channel.

That is, in the solid-state imaging device of the present invention, a semiconductor substrate having a trench formed on a main surface thereof, a first-conductivity-type high-concentration impurity diffusion region formed at the bottom of the trench; Below the high concentration impurity diffusion region of the mold,
A second conductivity type buried photodiode formed in contact with the high concentration impurity diffusion region and having one end exposed at the bottom of the trench; and a buried photodiode formed on the main surface of the semiconductor substrate adjacent to the trench. A buried channel of the second conductivity type, a transfer electrode formed on the buried channel, and a control gate formed in a region of the semiconductor substrate between the buried channel and the buried photodiode. And at least the control gate on the main surface of the semiconductor substrate.
And a control gate electrode formed so as to cover the transfer electrode. The transfer electrode and the buried channel constitute a charge transfer shift register, and the first conductivity type high-concentration impurity diffusion is performed. The region and the buried photodiode of the second conductivity type constitute a pixel portion, and the control gate electrode also serves as an optical shield film.

Further, according to the present invention, there is provided a solid-state imaging device, comprising: a semiconductor substrate having a trench formed on a main surface thereof; and a buried channel of a second conductivity type formed on the semiconductor substrate main surface adjacent to the trench. A transfer electrode formed on the buried channel, a first conductive type high-concentration impurity diffusion region formed in the semiconductor substrate along the trench bottom and sidewalls thereof, and a first conductive type high-concentration impurity diffusion region. An impurity diffusion region is formed below and in contact with the high-concentration impurity diffusion region, and one end is formed below the buried channel of the second conductivity type.
A second conductivity type buried photodiode extending away from the buried channel, and an optical system formed on the main surface of the semiconductor substrate so as to cover the transfer electrode and the trench side wall. A transfer film, wherein the transfer electrode and the buried channel constitute a charge transfer shift register, wherein the first conductivity type high-concentration impurity diffusion region and the second
The conductive type buried photodiode constitutes a pixel portion, and the transfer electrode also serves as a control gate electrode. A region of the first conductivity type is provided between the buried channel of the semiconductor substrate and the one end of the buried photodiode which extends, and the impurity concentration of this region is the same as that of the buried photo diode of the semiconductor substrate. The impurity concentration of the region of the first conductivity type below the diode may be lower.

Further, according to a method of manufacturing a solid-state imaging device of the present invention, a step of forming a second conductivity type buried photodiode by ion-implanting impurities from a main surface of a semiconductor substrate to the inside, Forming a trench above the buried photodiode, and implanting impurities into the trench to form a first conductive type high concentration impurity diffusion region along the bottom and side walls of the trench. Forming the buried photodiode in contact with the high-concentration impurity diffusion region, and projecting the tip of the buried photodiode in the horizontal direction from the high-concentration impurity diffusion region; and forming a second conductivity type adjacent to the trench. A buried channel is formed on the main surface of the semiconductor substrate, and the tip of the buried photodiode is separated from the buried channel below the buried channel. And forming a transfer electrode on the buried channel, and forming a control gate electrode also serving as an optical shield film so as to cover the transfer electrode and the trench side wall. It is characterized by having.

[0012]

Since the pixel portion is formed at the bottom of the trench, the pixel pitch can be made smaller than before, and most of the carriers generated below the buried photodiode are absorbed by the semiconductor substrate and diffuse into the buried channel. The smear characteristics are improved because they are very small. Further, since the buried photodiode portion extends below the buried channel, a high-concentration impurity diffusion region of a conductivity type opposite to that of the photodiode formed on the buried photodiode. Not affected by Therefore, this solid-state imaging device does not require a high read pulse.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIG.
The figure is a cross-sectional view of an element part of an inter-line area sensor. In the surface region of the N-type silicon semiconductor substrate 1, a P well 2 is formed. It is also possible to use a P-type silicon semiconductor substrate without forming a well. Trench 50 is formed in P well region 2 in the surface region of semiconductor substrate 1. Since multiple elements are formed on the semiconductor substrate,
A plurality of trenches are also formed correspondingly. At the bottom of the trench 50, a P ⁺ impurity diffusion region 52 is formed by, for example, ion implantation. The P ⁺ impurity diffusion region 52 extends on the main surface of the semiconductor substrate along one side wall of the trench 50, and thus the side wall portion becomes the element isolation region 10. The semiconductor substrate region along the other side wall is a control gate 9. Subsequent to the control gate portion 9, a buried channel 4 is formed in the semiconductor substrate region adjacent to the trench 50. At the bottom of the trench 50, the P ⁺ impurity diffusion region 52
The tip of a buried photodiode 51 formed adjacent to the bottom of the trench 50 extends in the direction of the control gate 9 and a part of the buried photodiode 51 is exposed at the bottom of the trench 50.

A P-type barrier well 8 having an impurity concentration higher than that of the P-well 2 is formed under the buried channel 4 to prevent carriers generated around the pixel portion 5 from flowing into the buried channel 4, thereby achieving a smear characteristic. Has been improved. The main surface of the semiconductor substrate 1 including the inner surface of the trench is covered with an insulating film 7 made of silicon oxide or the like. A transfer electrode 31 made of polysilicon or the like is formed on the buried channel 4 via the insulating film 7. After the transfer electrode 31 is covered with the insulating film 71 of silicon oxide, the control gate electrode 6 is formed so as to cover the transfer electrode 31 and the control gate portion 9 and the isolation region 10 on the inner wall of the trench. . Since the control gate electrode 6 also serves as an optical shield film, it not only covers the control gate portion 9 but also covers other predetermined regions as described above. The surface of the semiconductor substrate 1 including the control gate electrode 6 is protected by a transparent insulating protective film 12 of several thousands angstroms such as SiO ₂ or Si ₃ N ₄ . The pixel unit 5 includes a P ⁺ impurity diffusion region 52 and a buried photodiode 51, and the charge transfer shift register unit 3 includes a buried channel 4 and a transfer electrode 31.

Since the control gate length L2 and the element isolation width L4 are formed on the side walls of the trench 50, they are substantially zero. Therefore, the horizontal pixel pitch Ph formed on the semiconductor substrate 1 is substantially equal to the sum of the buried photodiode width L1 and the charge transfer shift register width L3. The high integration of the semiconductor substrate in the horizontal direction is more remarkable than that of the conventional example shown in FIGS. A typical value is L1
And L3 are both approximately 2 .mu.m, so that a 1/4 inch optical system 400,000 pixel sensor and a 2/3 inch optical system 2 million pixel sensor having a horizontal pixel pitch of about 5 .mu.m can be manufactured relatively easily. In the present invention, as shown in FIG. 1, the buried channel 4 is a control gate which is an optical shield film.
Since the upper part and the side part are covered by the gate electrode 6, the smear component is only from the leakage component of the carrier generated below the embedded photodiode 51. But,
Since the buried photodiode 51 is formed at the bottom of the trench 50, most of the carriers generated here are
Carriers that are absorbed by the semiconductor substrate 1 and diffuse to the buried channel side are extremely small.

Further, since the barrier well region 8 having a higher impurity concentration than the P well region 2 is formed under the buried channel 4 so as to surround the buried channel, this carrier also has a barrier potential of the barrier well region 8. The rate of flowing into the buried channel 4 is further reduced to greatly improve the smear characteristics. Needless to say, the barrier well region is not always necessary, and the present invention includes a structure in which the barrier well is not used. As a normal broadcast sensor, a frame proposed by the inventor earlier to improve the smear characteristic.
Frame Interline Tran
sfer) type charge transfer shift register
No. 2675), high-speed transfer is performed, but in the present invention, smear characteristics can be further improved without using this method. The pixel portion 5 is provided on the bottom surface inside the trench 50.
Is formed, there is a concern about whether or not a sufficient amount of received light can be obtained. However, since the optical shield film is formed on the side wall of the trench, light impinging on the optical shield film is reflected and the Since it is supplied to the pixel section, it is not necessary to take special measures such as enlarging the area of the pixel section. If Al is used for the optical shield film, that is, Al for the control gate electrode 6, 100% reflectance can be obtained. However, since Al is liable to form hillocks by heat treatment, even if the reflectance is somewhat inferior, high melting point metal or It is preferable to use the silicide or the like from the viewpoint of stability of the solid-state imaging device.

The light reflectance of MoSi ₂ is 80% and M
o is 60% and Ti is 40%. In the first embodiment, since the control gate electrode 6 also functions as an optical shield film, the control gate and the charge transfer shift register 3 are electrically independent. The electrode and the transfer electrode can be individually controlled. For example, an ON pulse can be applied only at the time of reading, and the potential can be normally kept at a potential (for example, a negative potential) at which the control gate is cut off under the control gate. Further, since no control gate electrode is formed on the side wall of the trench, the horizontal pitch of pixels can be reduced accordingly.

Next, a reference example will be described with reference to FIG.
The figure is a cross-sectional view of an element part of an inter-line area sensor. In the surface region of the N-type silicon semiconductor substrate 1, a P well 2 is formed. Trench 50 is formed in P well region 2 in the surface region of semiconductor substrate 1. At the bottom of trench 50, a P ⁺ impurity diffusion region 52 is formed. The P ⁺ impurity diffusion region 52 extends along one side wall of the trench 50 to the main surface of the semiconductor substrate, so that the side wall portion becomes the element isolation region 10. The semiconductor substrate region along the other side wall is a control gate 9. Subsequent to the control gate portion 9, a buried channel 4 is formed in the semiconductor substrate region adjacent to the trench 50. At the bottom of the trench 50,
The tip of the buried photodiode 51 formed adjacently below the P ⁺ impurity diffusion region 52 extends in the direction of the control gate portion 9 and a portion is exposed at the bottom of the trench 50. . A P-type barrier well 8 having a higher impurity concentration than the P-well 2 is formed below the buried channel 4.
The main surface of the semiconductor substrate 1 including the inner surface of the trench is covered with an insulating film 7. Up to this point, this area sensor has the same structure as in the first embodiment. A transfer electrode 31 of polysilicon is formed on the buried channel 4 via the insulating film 7.

The transfer electrode 31 extends on the side wall of the trench 50 so as to cover the control gate 9. After the transfer electrode 31 is covered with the insulating film 71, the optical shield film 11 is formed so as to cover the transfer electrode 31, the control gate 9 on the inner wall of the trench, and the element isolation region 10. The surface of the semiconductor substrate 1 including the optical shield film 11 is protected by a silicon oxide insulating protection film 12 such as PSG. The pixel unit 5 includes a P ⁺ impurity diffusion region 52 and a buried photodiode 51, and the charge transfer shift register unit 3 includes a buried channel 4 and a transfer electrode 31. Here, the transfer electrode 3 of the charge transfer shift register 3
Since 1 also serves as a control gate electrode, the optical shield film has only a light shielding function. However, since the optical shield film 11 and the control gate electrode overlap each other and are formed on the side walls of the trench, the horizontal pitch of the pixels is not improved as compared with that of FIG.

Next, a reference example will be described with reference to FIG.
The figure is a partial sectional view of the area sensor. This structure
Except for the transfer electrode portion, it is almost the same as that of FIG. In this case, the transfer electrode 31 is formed only of the buried channel 4 and the control gate electrode 6 made of polysilicon or the like is formed on the control gate 9. Therefore, since the transfer electrode and the control gate are separated, the amplitude of the transfer pulse applied to the transfer electrode can be increased, and the transfer charge amount can be increased. This effect is the same as in the first embodiment. Again, the horizontal pitch of the pixels is not improved over that of FIG. next,
FIG. 4 shows a schematic plan view of the entire inter-line type CCD area sensor shown in FIG. 2, and FIG. 5 shows an enlarged plan view of the R region, and the area sensor will be described. A plurality of pixel portions 5 are formed in columns, and control gates 9 for reading out signals are formed adjacent to each pixel portion, respectively.
Are connected to the charge transfer shift register 3. The charge transfer shift register 3 includes a vertical CCD (VCCD) and is connected to a horizontal CCD (HCCD) register. The horizontal CCD register is connected to an output circuit.

A plurality of pixel columns are formed.
The signal charges formed in the buried photodiode 51 of the pixel section 5 are transferred to a charge transfer shift register (VCCD) 9 by a read pulse applied to the control gate electrode 6 of the control gate 9, and are transferred to the VCCD. For example, a four-phase transfer clock pulse φ1 applied to the transfer electrode 31,
The data is sequentially transferred to the HCCD register by φ2, φ3, and φ4. The HCCD register sequentially transfers the signal charges transferred from the VCCD register to an output circuit. The output circuit outputs the signal charge from the HCCD register to the outside. As described above, in the inter-line type CCD area sensor, the pixel portions are separated from each other, and the lump of signal charge is transferred to the light-shielded vertical VCCD register through the control gate for each pixel portion. The lump of signal charges in each pixel column is sequentially sent out from the VCCD register to the HCCD register, and is read out as a time-series signal. Since the present invention is applied to a solid-state imaging device having a charge transfer shift register for transferring signal charges for each pixel portion, a frame inter-line area sensor is also applied to the present invention.

Next, a second embodiment will be described with reference to FIGS. FIG. 6 is a partial sectional view of the area sensor in which FIG. 2 is enlarged. FIG. 7 shows the P of the semiconductor substrate 1.
FIG. 9 is a distribution diagram of potential wells in a region along the A to F portions in the well 2. In the area sensor having this structure, the transfer electrode 31 also serves as the control gate electrode 6. The signal charges generated in the pixel portion 5 are transferred to the buried channel by modulating the potential wells of the control gate portion 9 and the buried channel 4 by a positive read pulse applied to the control gate electrode 6. The signal charge transferred from the pixel unit 5 is modulated by the potential well of the buried channel 4 (A) below the transfer electrode 31 by the transfer clock pulse of 0 to negative voltage (VH, VL) applied to the transfer electrode 31. Data is transferred through the charge transfer shift register. The P ⁺ impurity diffusion region 52 (F) of the pixel portion 5 is normally kept at 0 potential, and the buried photodiode 51 (E) is at the full depletion potential VPD. When the signal charges accumulated in the buried photodiode 51 by photoelectric conversion are transferred to the charge transfer shift register by a positive read pulse, the potential of the corner (C) at the bottom of the trench is controlled by a control gate.
The gate of the potential well is formed as shown by a potential curve (1) shown by a dotted line in FIG. 7 which is less susceptible to potential modulation of the control gate electrode 6 than the central portion (B).

The end (B) adjacent to the control gate of the buried photodiode 51 is a portion where the buried photodiode 51 protrudes from the P ⁺ impurity diffusion region 52 by lateral diffusion. The potential well is deeper than the complete depletion potential of the photodiode 51. This C,
Since the potential well of the portion D is in an irregular state as described above, if the amplitude of the positive read pulse applied to the control gate electrode 6 is small, the potential curves of the portions A to D (1)
As described above, the barrier generated in the C portion is not eliminated, and it is difficult to transfer the pixel portion to the charge transfer shift register. Therefore, in order to eliminate this barrier and to smoothly transfer the signal charge as shown by the potential curve (2), it is necessary to increase the amplitude of the read pulse. However, increasing the pulse amplitude imposes great restrictions on peripheral circuits, such as providing a separate power supply. In addition, since the control gate is formed on the side wall of the trench 50, the light incident width (W) of the opening of the trench is reduced, so that the sensitivity is also deteriorated.

FIG. 8 is a sectional view of an inter-line area sensor according to the second embodiment. In the surface region of the N-type silicon semiconductor substrate 1, a P well 2 is formed. A trench 5 is formed in the P-well region 2 in the surface region of the semiconductor substrate 1.
0 is formed. At the bottom of the trench 50, a P ⁺ impurity diffusion region 52 is formed by, for example, ion implantation. The P ⁺ impurity diffusion region 52 extends on the main surface of the semiconductor substrate along the side wall of the trench 50, so that the side wall portion becomes the element isolation region 10. Subsequent to the impurity diffusion region 52, a buried channel 4 is formed in the semiconductor substrate region adjacent to the trench 50. At the bottom of the trench 50, the P ⁺ impurity diffusion region 52
A buried photodiode 51 is formed adjacent to and below the substrate. One of the tips 13 extends in the horizontal direction and is located below the buried channel 4 formed on the main surface of the semiconductor substrate 1 and away from the buried channel.
Even if the tip 13 extends below the buried channel 4, it does not come into contact with the buried photodiode of the adjacent pixel part, and its distance must be sufficiently large to allow element isolation. For this purpose, a distance of about 1 μm or less is required. When the width of the charge transfer shift register is about 2 μm, the portion of the buried photodiode 51 extending below the buried channel 4 is approximately Can cover half.

In this embodiment, a P-type barrier well 8 having a higher impurity concentration than the P-well 2 shown in the embodiment of FIG.
Need not be formed. The main surface of the semiconductor substrate 1 including the inner surface of the trench is covered with an insulating film 7 made of silicon oxide or the like. The transfer electrode 3 made of polysilicon or the like is formed on the buried channel 4 via the insulating film 7.
1 is formed. Then, the transfer electrode 31 is covered with an insulating film 71 of silicon oxide, and then the transfer electrode 31 and the MoSi ₂ are formed so as to cover the element isolation region 10 on the inner wall of the trench.
An optical shield film 11 is formed. The surface of the semiconductor substrate 1 including the optical shield film 11 is made of SiO ₂ or Si.
Number 1000 such as ₃ N ₄ angstroms - is protected by a transparent dielectric protective film 12 of about beam. The pixel unit 5 has P ⁺
The charge transfer shift register 3 includes an impurity diffusion region 52 and a buried photodiode 51, and the buried channel 4
And a transfer electrode 31. The transfer electrode 31 also serves as a control gate electrode. The tip 13 of the embedded photodiode 51 is hereinafter referred to as a storage unit 13.

Next, the operation of the area sensor which is the solid-state imaging device of this embodiment will be described. FIG. 9 shows a semiconductor substrate 1 (A), a P well 2 (B), a storage section 13 (C), a boundary portion (D) between the storage section 13 and the buried photodiode 51, and a buried photodiode 51 (E). 10 is a potential well distribution diagram along the P ⁺ impurity diffusion region 52 (F), and FIG. 10 shows a buried channel 4 (A ′), and a P well 2 (B ′) between the buried channel 4 and the storage unit 13. And C
It is a potential well distribution map along -F. Semiconductor substrate 1 and P
A reverse bias is applied between the wells 2. The P-well (B) between the buried photodiode 51 and the storage section 13 and the semiconductor substrate 1 is in a punch-through state, and an excessive amount of electric charge stored in the buried photodiode 51 and the storage section 13 is obtained. The components leak to the semiconductor substrate 1. Storage unit 13 and embedded photodiode 51
The potential well is deeper in the accumulation portion 13 by the absence of the P ⁺ impurity diffusion region 52. The impurity concentration of the P well in the portion (B ') between the buried channel 4 and the accumulation 13 is about 1 × 10 ¹⁵ cm ^-3 , and the potential well of the P well transfers the signal charge through the charge transfer shift register. Is in the punch-through state. The potential well in this portion (B ′) is shallower than the P well 2 in the portion (B) between the storage section 13 and the semiconductor substrate 1.

Therefore, the embedded photodiode 51
And the excess charge accumulated in the accumulation unit 13
, So as not to leak into the buried channel 4. The phenomenon that excess charge leaks into the buried channel 4 of the charge transfer shift register is called blooming, and the potential difference Vm is appropriately determined according to the degree of leakage. The transfer of the signal charges stored in the storage section 13 and the buried photodiode 51 to the buried channel 4 is performed by a positive read pulse applied to the control gate electrode serving also as the transfer electrode 31. The potential well of the buried channel 4 is made deep by the read pulse as shown by the potential curve of the dotted line in FIG. 10 to make the portion B ′ punch-through, and the signal charge is transferred to the buried channel 4 via the storage unit 13. As described above, in order to transfer the signal charges from the pixel portion to the charge transfer shift register, the potential of the buried channel is deepened as shown by a potential distribution curve indicated by a dotted line in FIG. Therefore, as compared with the case where the transfer is performed using the surface portion as in the conventional case, there is no barrier well along the transfer channel, the transfer channel width is widened, and the transfer time is shortened. The reading of the signal voltage became possible.

Further, the amount of signal charges that can be stored in the pixel portion increases as compared with the structure without the storage portion 13 using only the embedded photodiode 51. The buried photodiode 51 has a structure extending to the lower part of the buried channel 4, and the upper part and the side wall of the buried channel 4 are covered with the optical shield film 11, so that the buried photodiode 51 is formed around the buried channel. Most of the generated carriers flow into the semiconductor substrate 1, the buried photodiode 51, the storage section 13, and the like, and almost no carriers leak into the buried channel 4, so that the smear characteristics are greatly improved. Since there is no control gate electrode, high integration is advanced.

Next, a method of manufacturing the area sensor according to the second embodiment will be described with reference to FIGS. 9, 11 and 12.
First, a P-type silicon semiconductor substrate 1 on which a P well 2 is formed
Then, using a high-acceleration ion implanter whose ion energy (monovalent ions) exceeds 1 MeV, phosphorus is ion-implanted to a depth of about 2 to 3 μm from the main surface of the semiconductor substrate 1 at an energy of about 2 to 4 MeV, Diffusion and embedded photodiode
A doped region 51 is formed (FIG. 11). Next, a trench 50 is formed in the main surface of the semiconductor substrate 1 by anisotropic etching or the like, and boron is ion-implanted around the trench 50 with an energy of 40 to 50 KeV to form a P ⁺ impurity diffusion region 52. Then, an impurity such as phosphorus is diffused from the main surface of the semiconductor substrate to form a buried channel 4 (FIG. 12). Further, a transfer electrode 31 and an optical shield film 11 are formed on the surface of the semiconductor substrate 1 via an insulating film, thereby completing an area sensor (see FIG. 8).

Next, a third embodiment will be described with reference to FIG. The basic structure of the area sensor in this figure is the same as that in FIG. In this embodiment, the tip of the buried photodiode 51 protruding toward the buried channel 4, that is, the accumulating portion 13 has an extension portion 131, which is one layer higher than that of the previous embodiment. Are close to the buried channel 4. Therefore, the read pulse is reduced in voltage and the amount of accumulated signal charge is increased. Expansion section 13 of storage section formed adjacent to storage section 13
1 is formed by implanting phosphorus from a surface of a main surface of a semiconductor substrate on which a buried channel 4 is to be formed by using a high-acceleration ion implanter with high energy.
In the fourth and fifth embodiments, the impurity concentration of the region (B ′) between the buried channel 4 of the P well 2 and the storage portion 13 is higher than the impurity concentration of the other region of the P well 2 such as the B region. Can be lower. If the impurity concentration in the B 'region is reduced, punch-through becomes easier and the transfer of signal charges becomes easier. The material of the transfer electrode is not limited to polysilicon, but may be a silicide such as MoSi ₂ , W, Mo, or Ti, or a high melting point metal.

[0031]

According to the present invention, with the above-described structure, as the degree of integration increases, the smear characteristics are improved, and the signal charges can be read with a low-voltage read pulse.

[Brief description of the drawings]

FIG. 1 is a sectional view of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a solid-state imaging device according to a reference example.

FIG. 3 is a cross-sectional view of a solid-state imaging device according to a reference example.

FIG. 4 is a plan view of an area sensor for explaining the present invention.

FIG. 5 is an enlarged plan view of a portion R of the area sensor of FIG. 4;

FIG. 6 is a partially enlarged cross-sectional view of the solid-state imaging device in FIG. 2;

7 is a potential distribution diagram of the solid-state imaging device of FIG.

FIG. 8 is a sectional view of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 9 is a potential distribution diagram of the solid-state imaging device of FIG.

FIG. 10 is a potential distribution diagram of the solid-state imaging device of FIG.

FIG. 11 is a sectional view of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing a manufacturing process of the solid-state imaging device according to the second embodiment of the present invention;

FIG. 13 is a sectional view showing a manufacturing process of the solid-state imaging device according to the third embodiment of the present invention.

FIG. 14 is a cross-sectional view of a conventional solid-state imaging device.

FIG. 15 is a cross-sectional view of another conventional solid-state imaging device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-type silicon semiconductor substrate 2 P well 3 Charge transfer shift register 4 Buried channel 5 Pixel part 6 Control gate electrode 7, 71 Insulating film 8 Barrier well 9 Control gate part 10 Element isolation region 11 Optical shield film DESCRIPTION OF SYMBOLS 12 Insulating protective film 13 Storage part 31 Transfer electrode 50 Trench 51 Buried photodiode 52 P ⁺ impurity diffusion region 131 Extension part of storage part

Claims (4)

(57) [Claims] A first conductive type high-concentration impurity diffusion region formed at a bottom of the trench; a first conductivity-type high-concentration impurity diffusion region formed at a bottom of the trench; A buried photodiode of a second conductivity type formed below and in contact with the high-concentration impurity diffusion region and having one end exposed at the bottom of the trench; and the main surface of the semiconductor substrate adjacent to the trench and adjacent to the trench. A buried channel of a second conductivity type formed on the buried channel, a transfer electrode formed on the buried channel, and a control formed in a region between the buried channel and the buried photodiode of the semiconductor substrate. A gate portion; and a control gate electrode formed on the main surface of the semiconductor substrate so as to cover at least the control gate portion and the transfer electrode. Write channel constitutes a charge transfer shift register, said first conductivity type high concentration impurity diffusion region and said second conductivity type buried type photo die Oh - de constitute a pixel unit, the control gate - gate electrode is A solid-state imaging device, which also serves as an optical shield film. 2. A semiconductor substrate having a trench formed in a main surface thereof, a buried channel of a second conductivity type formed in the main surface of the semiconductor substrate adjacent to the trench, and formed on the buried channel. A transfer electrode, a first conductive type high-concentration impurity diffusion region formed in the semiconductor substrate along the trench bottom and the side wall thereof, A second conductivity type buried photodiode which is formed in contact with the high-concentration impurity diffusion region and has one end extending below and distant from the second conductivity type buried channel; An optical shield film formed on the main surface of the semiconductor substrate so as to cover the transfer electrode and the side wall of the trench, wherein the transfer electrode and the buried channel are a charge transfer shift register Configure, wherein the first conductivity type high concentration impurity diffusion region of a second conductivity type buried photo die Oh - de constitute a pixel unit, and the transfer electrodes control gate -, characterized in that also serves as a gate electrode Solid-state imaging device. 3. A region of the first conductivity type between the buried channel of the semiconductor substrate and the one end of the buried photodiode extending, and the impurity concentration of this region is the semiconductor conductivity. 3. The solid-state imaging device according to claim 2, wherein the impurity concentration of the region of the first conductivity type below the buried photodiode of the substrate is lower. 4. A step of forming a second conductivity type buried photodiode by ion-implanting impurities from the main surface of the semiconductor substrate into the inside, and etching the buried photodiode by etching the main surface of the semiconductor substrate. Forming a trench on the trench; ion-implanting an impurity into the trench to form a high-concentration impurity diffusion region of a first conductivity type along the bottom and side walls of the trench; Contacting the high-concentration impurity diffusion region, and projecting the tip of the tip in the horizontal direction from the high-concentration impurity diffusion region; and forming a buried channel of a second conductivity type adjacent to the trench on the main surface of the semiconductor substrate. Arranging the buried channel such that the tip of the buried photodiode is separated from the buried channel below the buried channel; Forming a transfer electrode thereon, and forming a control gate electrode which also serves as an optical shield film formed so as to cover the transfer electrode and the trench side wall. A method for manufacturing a solid-state imaging device.