JPH0697416A - Solid-state image sensing device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a solid-state image sensing device which enhances the degree of integration and which excels in smear properties and facilitates the transfer of signal charges to a charge transfer shit resistor from picture elements. CONSTITUTION:A plurality of trenches 50 are formed in a P well 2 of an N type silicon semiconductor board 1 where a photodiode 51 for a picture element section 5 which constitutes a solid-state image sensing device is formed with a P + impurity diffusion area 52. This construction makes it possible to enhance the degree of integration. It is also possible to facilitate the transfer of charges by extending the tip of the photodiode 51 up to the lower part of the transfer electrode 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device,
In particular, it relates to a highly miniaturized photosensitive area of a CCD area sensor.

[0002]

2. Description of the Related Art A solid-state image pickup device is an LSI having functions of photoelectric conversion, storage, and transfer, and the degree of integration on its semiconductor substrate has been remarkably improved in recent years. FIG. 14 shows an example of a conventional solid-state imaging device proposed by the inventor (Japanese Patent Application No. 3-11).
221). An N-type silicon semiconductor substrate 1 is used as a semiconductor substrate, and a P-type impurity diffusion region P
^- to form a well 2. A pixel portion 5, a charge transfer shift register portion 3, a control gate portion 9 and an element isolation region 10 are formed on a semiconductor substrate.
^A buried channel 4 is formed. A P ⁺ impurity diffusion region 52 is formed apart from one side of the buried channel 4. An N ⁺ buried type photodiode 51 is formed below the impurity diffusion region 52. A part of this photodiode 51 extends to the main surface of the semiconductor substrate and is exposed on this main surface. The main surface of the semiconductor substrate 1 is covered with an insulating film 7 such as silicon oxide, and a transfer electrode 31 such as polysilicon or polycide is formed on the buried channel 4 via the insulating film 7. A control gate electrode 6 is formed on the transfer electrode 31 and its periphery through an insulating film.

The control gate electrode 6 has its function if it is formed between the transfer electrode 31 and the pixel portion 5 and at least on the portion exposed on the main surface of the semiconductor substrate of the photodiode 51. Although this can be achieved, in this conventional example, since the control gate electrode 6 also serves as an optical shield film, it has the structure as described above. The control gate electrode 6 is covered and protected by an insulating protective film 12 such as a silicon oxide film. A P barrier well 8 having an impurity concentration higher than that of the P well 2 is formed around the buried channel 4 to prevent carriers generated around the pixel portion 5 from flowing into the buried channel 4 and improve smear characteristics. . That is, the pixel portion is composed of the photodiode 51 and the impurity diffusion region 52,
The transfer electrode 31 and the buried channel 4 constitute the charge transfer shift register section 3, and the transfer of the signal charge is controlled between the transfer electrode 31 and the photodiode 51 and the control gate electrode 6 thereon. The control gate portion 9 is formed, and the region of the buried channel 4 opposite to the control gate portion 9 is an element isolation region 10, and a P ⁺ impurity diffusion region 52 of another element is formed. ing. Under the photodiode 51, the P well 2 is thin as shown in the figure. In this way, excess charges easily flow out to the semiconductor substrate 1.

FIG. 15 shows an example of another conventional solid-state image pickup device. Since the solid-state imaging device of FIG. 14 is formed on a flat semiconductor substrate surface, there is a limit to miniaturization thereof. In this example, a trench is formed on the surface for further miniaturization. A trench is formed in the surface of the P well 2 of the N-type silicon semiconductor substrate 1, and a buried channel 4 is formed in the bottom surface and side wall of the trench. A control gate portion 9 is provided adjacent to one side of the trench, and a pixel portion 5 including a photodiode 51 and a P ⁺ impurity diffusion region 52 is formed adjacent to the control gate portion 9. The element isolation region 10 is formed adjacent to one side of the trench opposite to the one side. An insulating film 7 of silicon oxide or the like is formed on the surface of the semiconductor substrate 1 including the inside of the trench, and polysilicon or the like is formed so as to cover the buried channel 4, the control gate portion 9 and the element isolation region 10 thereon. The transfer electrode 31 is formed. Further, the optical shield film 11 is formed on the transfer electrode 31 with an insulating film 71 interposed therebetween. Transfer electrode 3
The portion covering the control gate portion 9 of No. 1 is used as a control gate electrode. The optical shield film 11 is covered and protected by an insulating protective film 12 such as a silicon oxide film or a nitride film. The pixel portion 5 has a buried photodiode structure as in the case of FIG. As shown in the figure, the light shield film 11 is opened in the pixel portion 5, and the incident light is applied only to the embedded photodiode portion 3.

As described above, in both the case of FIG. 14 and the case of FIG. 15, the photodiode formed on the surface of the silicon semiconductor substrate is in contact with the silicon oxide film formed on the surface, so that the depletion layer formed there is formed. Of course comes into contact with this oxide film. Therefore, the current generated from the level at the silicon-silicon oxide film interface greatly affects the output current in the dark.
An embedded photo diode was conceived as a method for reducing the dark current from the photo diode.
That is, a P-type high-concentration impurity diffusion region is formed between the silicon oxide film and the photodiode. Photodio
Silicon to cover the surface of the cathode with P ⁺ impurity diffusion regions.
The silicon oxide film interface is separated from the photodiode.
Therefore, since the depletion layer does not extend to the interface, the influence of the level at this interface on the dark current is significantly reduced. Therefore, if this structure is adopted, it is possible to reduce the dark current to about 1/10 as compared with the conventional structure which does not use the buried photodiode.

[0006]

In the solid-state imaging device having the structure shown in FIG. 14, the embedded photodiode width is L1,
Assuming that the control gate length is L2, the charge transfer shift register width is L3 and the element separation width is L4, the width of one pixel, that is, the pixel pitch Ph is L1 + L2 + L3 + L4.
A typical example of the current fine processing technology is L
Since 1 and L3 are approximately equal to each other and about 2 μm, and L2 and L4 are about 1 μm, Ph becomes about 6 μm. 40
Since the horizontal pitch is about 5 μm in the one million pixel sensor and the two million pixel sensor for HDTV, it is extremely difficult to manufacture such a sensor without deteriorating the characteristics.

Therefore, a solid-state image pickup device having the structure shown in FIG. 15 was developed. In this structure, the buried channel 4 of the charge transfer shift register section 3 is formed along the inner wall of the trench. The amount of accumulated charge per unit length in the horizontal direction increases as compared with the case of forming the conventional flat portion. However, since the control gate portion and the element isolation region are formed on the semiconductor substrate in the same plane as the pixel portion, the pixel pitch is improved in the degree of integration in the horizontal direction because the width of the charge transfer shift register is only reduced. , No improvement in horizontal integration is observed. Moreover, since the buried photodiode 51 and the buried channel 4 are close to each other,
Carriers generated in the lower part of the buried photodiode easily flow into the buried channel 4, and as a result, smear characteristics are often significantly deteriorated. Also, a P ⁺ impurity diffusion region 52 (see FIG. 14) formed on the buried photodiode, which is considered as a method for reducing the dark current.
There is a case where the position is shifted and the state is interposed between the buried channel 4 and the buried photodiode 51. In such a case, a potential barrier is generated between the control gate unit 9 and the pixel unit 5, and in order to transfer the charges generated in the pixel to the charge transfer shift register unit 3, a fairly high read pulse is required. There is also a problem that it is necessary to apply the voltage to the control gate electrode 6. The present invention has been made in view of the above circumstances, and has a solid-state imaging device having a structure that improves the degree of integration, has an excellent smear characteristic, and facilitates the transfer of signal charges from pixels to the charge transfer shift register. It is intended to provide a manufacturing method thereof.

[0008]

The present invention is characterized in that a trench is formed in a semiconductor substrate on which a solid-state image pickup device is formed and a pixel portion is formed at the bottom thereof. Further, the embedded photodiode of the pixel portion formed on the bottom portion is extended so that the photodiode is located below the embedded channel of the charge transfer shift register, and the extension of the photodiode is performed. It is characterized in that punch-through occurs between the existing portion and the buried channel to transfer charges.

That is, in the solid-state image pickup device of the present invention, a semiconductor substrate having a trench formed in the main surface thereof, a first-conductivity-type high-concentration impurity diffusion region formed at the bottom of the trench, and the first conductivity type are provided. Below the high-concentration impurity diffusion region of the mold,
A second conductivity type buried photo diode formed in contact with the high concentration impurity diffusion region and having one end exposed at the bottom of the trench, and formed on the main surface of the semiconductor substrate adjacent to the trench. A buried channel of the second conductivity type, a control gate portion formed in a region of the semiconductor substrate between the buried channel and the buried photodiode, and at least the main surface of the semiconductor substrate. A control gate electrode formed so as to cover the control gate portion, and a light formed on the main surface of the semiconductor substrate so as to cover the transfer electrode and the control gate electrode. A shield film, the transfer electrode and the buried channel constitute a charge transfer shift register, and the first conductivity type high-concentration impurity diffusion region and the second conductivity type buried photodiode are pixels. It is the first feature to configure.

The optical shield film can also serve as the control gate electrode. The control gate electrode may be connected to the transfer electrode. The buried channel may be surrounded by a barrier well of the first conductivity type. Further, a semiconductor substrate having a trench formed on a main surface thereof, a buried channel of a second conductivity type adjacent to the trench and formed on the semiconductor substrate main surface, the trench bottom portion and the sidewall thereof are provided along the trench. A high-concentration impurity diffusion region of a first conductivity type formed on a semiconductor substrate;
It is formed below the conductivity type high-concentration impurity diffusion region and in contact with the high-concentration impurity diffusion region, and one end extends under the second conductivity-type buried channel and apart from the buried channel. A second conductive type buried photodiode and an optical shield film formed on the main surface of the semiconductor substrate so as to cover the transfer electrode and the sidewall of the trench are provided. The buried channel constitutes a charge transfer shift register, and comprises a high-concentration impurity diffusion region of the first conductivity type and a buried photodiode of the second conductivity type.
The second feature is that the gate constitutes a pixel portion, and the transfer electrode also serves as a control gate electrode. A region of the first conductivity type is between the buried channel of the semiconductor substrate and the one end of the buried photo diode extending, and the impurity concentration of this region is the buried photo region of the semiconductor substrate. The impurity concentration in the first conductivity type region below the diode can be set lower than the impurity concentration.

The method of manufacturing a solid-state image pickup device according to the present invention comprises the steps of implanting impurities from the main surface of the semiconductor substrate to form an embedded photodiode of the second conductivity type, and the main surface of the semiconductor substrate. To form a trench on the buried photo diode, and impurities are ion-implanted into the trench to form a high-concentration impurity diffusion region of the first conductivity type along the bottom and side walls of the trench. The buried photodiode is formed in contact with the high-concentration impurity diffusion region, and the tip of the buried photodiode is horizontally projected from the high-concentration impurity diffusion region; and the second conductivity type is adjacent to the trench. A buried channel is formed on the main surface of the semiconductor substrate, and the tip of the buried photodiode is separated from the buried channel under the buried channel. And a step of forming a transfer electrode on the buried channel, and a step of forming a control gate electrode which also serves as an optical shield film so as to cover the transfer electrode and the sidewall of the trench. It is characterized by being.

[0012]

Since the pixel portion is formed at the bottom of the trench, the pixel pitch can be made smaller than before, and most of the carriers generated in the lower portion of the buried photodiode are absorbed by the semiconductor substrate and diffused into the buried channel. The smear characteristic is improved because the amount is very small. Further, since the buried photodiode portion is extended below the buried channel, a high-concentration impurity diffusion region of a conductivity type opposite to the photodiode formed above the buried photodiode is formed. Not affected by. Therefore, this solid-state imaging device does not require a high read pulse.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIG.
The figure is a cross-sectional view of an element portion of an inter-line type area sensor. A P well 2 is formed in the surface region of the N-type silicon semiconductor substrate 1. It is also possible to use a P-type silicon semiconductor substrate without forming a well. A trench 50 is formed in the P well region 2 in the surface region of the semiconductor substrate 1. Since multiple elements are formed on the semiconductor substrate,
A plurality of trenches are also formed in accordance with it. A P ⁺ impurity diffusion region 52 is formed at the bottom of the trench 50 by, for example, ion implantation. The P ⁺ impurity diffusion region 52 extends along the one side wall of the trench 50 on the main surface of the semiconductor substrate, and thus the side wall portion serves as the element isolation region 10. Further, the semiconductor substrate region along the other side wall is the control gate portion 9. Subsequent to the control gate portion 9, a buried channel 4 is formed in the semiconductor substrate region adjacent to the trench 50. The P ⁺ impurity diffusion region 52 at the bottom of the trench 50
The buried photodiode 51 formed under and adjacent to the bottom of the trench extends in the direction of the control gate 9 and is partially exposed at the bottom of the trench 50.

Below the buried channel 4, a P-type barrier well 8 having an impurity concentration higher than that of the P well 2 is formed to prevent carriers generated around the pixel portion 5 from flowing into the buried channel 4 and smear characteristics. Has improved. The main surface of the semiconductor substrate 1 including the inner surface of the trench is covered with an insulating film 7 made of silicon oxide or the like. A transfer electrode 31 made of polysilicon or the like is formed on the buried channel 4 via the insulating film 7. Then, the transfer electrode 31 is covered with an insulating film 71 of silicon oxide, and then the control gate electrode 6 is formed so as to cover the transfer electrode 31, the control gate portion 9 of the inner wall of the trench, and the element isolation region 10. . Since the control gate electrode 6 also serves as a light shield film, it not only covers the control gate portion 9 but also covers other predetermined regions as described above. The surface of the semiconductor substrate 1 including the control gate electrode 6 is protected by a transparent insulating protective film 12 of about several thousand angstroms such as SiO ₂ or Si ₃ N ₄ . The pixel section 5 includes a P ⁺ impurity diffusion region 52 and a buried photodiode 51, and the charge transfer shift register section 3 includes a buried channel 4 and a transfer electrode 31.

Since the control gate length L2 and the element isolation width L4 are formed on the side wall of the trench 50, they are substantially zero. Therefore, the horizontal pixel pitch Ph formed on the semiconductor substrate 1 is almost equal to the sum of the embedded photodiode width L1 and the charge transfer shift register width L3. The high integration of the semiconductor substrate in the horizontal direction is more remarkable than that of the conventional example shown in FIGS. A typical value is L1
Since both L3 and L3 are approximately 2 .mu.m, it is relatively easy to manufacture a 1/4 inch optical system 400,000 pixel sensor and a 2/3 inch optical system 2 million pixel sensor having a horizontal pixel pitch of about 5 .mu.m. In the present invention, as shown in FIG. 1, the buried channel 4 is a control gate which is an optical shield film.
Since the upper portion and the side surface portion thereof are covered with the gate electrode 6, the smear component is composed only of the leakage component of the carrier generated in the lower portion of the embedded photodiode 51. But,
Since the buried photo diode 51 is formed at the bottom of the trench 50, most of the carriers generated here are
Very few carriers are absorbed by the semiconductor substrate 1 and diffuse to the buried channel side.

Further, since the barrier well region 8 having a higher impurity concentration than the P well region 2 is formed below the buried channel 4 so as to surround the buried channel, this carrier also has a barrier potential of the barrier well region 8. The rate of inflow into the buried channel 4 is further reduced, and the smear characteristic is significantly improved. Of course, this barrier well region is not always necessary, and the present invention also includes a region in which this barrier well is not used. In order to improve the smear characteristic, a sensor for normal broadcasting uses the frame previously proposed by the inventor.
Frame Interline Tran
sfer) charge transfer shift register (Japanese Patent Laid-Open No. 55-5
However, in the present invention, the smear characteristic can be further improved without using this method. The pixel portion 5 is formed on the bottom surface inside the trench 50.
However, since the optical shield film is provided on the side wall of the trench, the light hitting the optical shield film is reflected and the pixel is reflected. Since it is supplied to the pixel section, it is not necessary to take special measures such as increasing the area of the pixel section. If Al is used for the light shield film, that is, the control gate electrode 6, a reflectance of 100% can be obtained, but since Al easily causes hillocks by heat treatment, even if the reflectance is slightly inferior, refractory metal or It is preferable to use the silicide or the like from the standpoint of stability of the solid-state imaging device.

The light reflectance of MoSi ₂ is 80% and M
o is 60% and Ti is 40%. In the first embodiment, since the control gate electrode 6 also serves as the light shield film, the control gate and the charge transfer shift register 3 are electrically independent, so that the control gate is formed. The electrodes and the transfer electrodes can be controlled individually, and for example, an on-pulse can be applied only during reading and normally held at a potential (eg, a negative potential) that cuts off under the control gate. Further, since the control gate electrode is not formed on the side wall of the trench, the horizontal pitch of the pixels can be reduced accordingly.

Next, a second embodiment will be described with reference to FIG. The figure is a cross-sectional view of an element portion of an inter-line type area sensor. A P well 2 is formed in the surface region of the N-type silicon semiconductor substrate 1. A trench 50 is formed in the P well region 2 in the surface region of the semiconductor substrate 1. A P ⁺ impurity diffusion region 52 is formed at the bottom of the trench 50. The P ⁺ impurity diffusion region 52 is the trench 5
0 extends to the main surface of the semiconductor substrate along one side wall, and thus the side wall portion serves as the element isolation region 10. Also, the semiconductor substrate region along the other side wall is
It is a control gate unit 9. Subsequent to the control gate portion 9, a buried channel 4 is formed in the semiconductor substrate region adjacent to the trench 50. The buried photodiode 51 formed at the bottom of the trench 50 under the P ⁺ impurity diffusion region 52 and adjacent thereto has a tip extending toward the control gate portion 9 and a part thereof being a trench. It is exposed at the bottom of 50. Below the buried channel 4, a P-type barrier well 8 having a higher impurity concentration than the P well 2 is formed. The main surface of the semiconductor substrate 1 including the inner surface of the trench is covered with an insulating film 7. Up to this point, this area sensor has the same structure as in the first embodiment. A transfer electrode 31 made of polysilicon is formed on the buried channel 4 via the insulating film 7.

The transfer electrode 31 extends on the side wall of the trench 50 so as to cover the control gate portion 9. After the transfer electrode 31 is covered with the insulating film 71, the optical shield film 11 is formed so as to cover the transfer electrode 31, the control gate portion 9 of the inner wall of the trench, and the element isolation region 10. The surface of the semiconductor substrate 1 including the optical shield film 11 is protected by a silicon oxide-based insulating protective film 12 such as PSG. The pixel section 5 includes a P ⁺ impurity diffusion region 52 and a buried photodiode 51, and the charge transfer shift register section 3 includes a buried channel 4 and a transfer electrode 31. Here, the transfer electrode 3 of the charge transfer shift register 3
Since 1 also serves as a control gate electrode, the light shield film has only a light shielding function. However, since the optical shield film 11 and the control gate electrode overlap each other and are formed on the side wall of the trench, the horizontal pitch of the pixel is not improved as compared with that of FIG.

Next, a third embodiment will be described with reference to FIG. The figure is a partial cross-sectional view of the area sensor. This structure is almost the same as that of FIG. 2 except the transfer electrode portion. Here, the transfer electrode 31 is formed only by implanting the buried channel 4, and the control gate electrode 6 made of polysilicon or the like is formed on the control gate portion 9.
Therefore, since the transfer electrode and the control gate are separated from each other, the amplitude of the transfer pulse applied to the transfer electrode can be increased and the transfer charge amount can be increased. This effect is the same as that of the first embodiment. Again, the horizontal pixel pitch is not improved over that of FIG. Next, a schematic plan view of the whole inter-line type CCD area sensor shown in the above embodiment is shown in FIG. 4, and an enlarged plan view of the R region thereof is shown in FIG. 5 to explain the area sensor of the embodiment. A plurality of pixel portions 5 are formed in columns, control gates 9 for reading signals are formed adjacent to the respective pixel portions, and the control gates 9 are connected to the charge transfer shift register 3. There is. The charge transfer shift register 3 is a vertical CC
It consists of a D (VCCD) and is connected to a horizontal CCD (HCCD) register. The horizontal CCD register is connected to the output circuit.

Further, a plurality of pixel columns are formed.
The signal charges formed in the embedded photodiode 51 of the pixel portion 5 are transferred to the charge transfer shift register (VCCD) 9 by the read pulse applied to the control gate electrode 6 of the control gate 9, and the signal charges of the VCCD are transferred. For example, four-phase transfer clock pulses φ 1 applied to the transfer electrode 31,
It is sequentially transferred to the HCCD register by φ2, φ3, and φ4. The HCCD register sequentially transfers the signal charges transferred from the VCCD register to the output circuit. The output circuit outputs the signal charge from the HCCD register to the outside. As described above, the inter-line type CCD area sensor separates the pixel parts from each other, and the lump of signal charges for each pixel part is transferred to the vertical VCCD register shielded through the control gate. A mass of signal charges of each pixel column is sequentially sent out from each VCCD register to the HCCD register and read out as a time series signal. Since the present invention is applied to a solid-state image pickup device of a type including a charge transfer shift register for transferring signal charges for each pixel portion, a frame interline type area sensor is also applied to the present invention.

Next, a fourth embodiment will be described with reference to FIGS. FIG. 6 is a partial cross-sectional view of the area sensor in which FIG. 2 is enlarged. FIG. 7 shows P of the semiconductor substrate 1.
FIG. 6 is a distribution diagram of potential wells in a region along a portion A to F in well 2. In the area sensor having this structure, the transfer electrode 31 also serves as the control gate electrode 6. The signal charges generated in the pixel section 5 are transferred to the buried channel by modulating the potential wells of the control gate section 9 and the buried channel 4 by the positive read pulse applied to the control gate electrode 6. The signal charge transferred from the pixel portion 5 is modulated in the potential well of the buried channel 4 (A) under the transfer electrode 31 by the transfer clock pulse of 0 to negative voltage (VH, VL) applied to the transfer electrode 31. Transfers in the charge transfer shift register. The P ⁺ impurity diffusion region 52 (F) of the pixel portion 5 is normally held at 0 potential, and the buried photodiode 51 (E) is at full depletion potential VPD. When the signal charge accumulated in the buried photodiode 51 by photoelectric conversion is transferred to the charge transfer shift register by the positive read pulse, the potential of the corner part (C) at the bottom of the trench is controlled by the control gate.
The barrier of the potential well is formed as shown by the potential curve (1) shown by the dotted line in FIG. 7 because it is less susceptible to the potential modulation of the control gate electrode 6 compared to the central portion (B).

The end portion (B) adjacent to the control gate of the buried photodiode 51 is a portion of the buried photodiode 51 protruding from the P ⁺ impurity diffusion region 52 by lateral diffusion. The potential well is deeper than the full depletion potential of the photodiode 51. This C,
Since the potential well of the D portion is in such an irregular state, if the amplitude of the positive read pulse applied to the control gate electrode 6 is small, the potential curve of the A to D portions (1)
As described above, the barrier generated in the C portion is not eliminated, and transfer from the pixel portion to the charge transfer shift register becomes difficult. Therefore, in order to eliminate this barrier and to smoothly transfer the signal charges as in the potential curve (2), it is necessary to increase the amplitude of the read pulse. However, in order to increase the pulse amplitude, a separate power supply is provided, which imposes great restrictions on the peripheral circuits. Further, since the light entrance width (W) of the trench opening is reduced because the control gate is formed on the side wall of the trench 50, the sensitivity is also deteriorated.

FIG. 8 is a sectional view of an interline type area sensor according to the fourth embodiment. A P well 2 is formed in the surface region of the N-type silicon semiconductor substrate 1. A trench 50 is formed in the P well region 2 in the surface region of the semiconductor substrate 1.
Is formed. A P ⁺ impurity diffusion region 52 is formed at the bottom of the trench 50 by, for example, ion implantation. The P ⁺ impurity diffusion region 52 extends on the main surface of the semiconductor substrate along the side wall of the trench 50, and thus the side wall portion serves as the element isolation region 10. Subsequent to the impurity diffusion region 52, the buried channel 4 is formed in the semiconductor substrate region adjacent to the trench 50. At the bottom of the trench 50, a buried photodiode 51 is formed under the P ⁺ impurity diffusion region 52 and adjacent thereto. One of the tips 13 extends in the horizontal direction, and the buried channel 4 is formed on the main surface of the semiconductor substrate 1.
Located underneath and away from this buried channel. Even if the tip 13 extends below the buried channel 4, it does not come into contact with the buried photodiode of the adjacent pixel portion, and its distance must be sufficiently large for element isolation. For that purpose, a distance of about 1 μm or less is required, and when the width of the charge transfer shift register is about 2 μm, the portion of the buried photodiode 51 extending below the buried channel 4 is about the buried channel 4. Can cover half.

In this embodiment, a P-type barrier well 8 having a higher impurity concentration than the P well 2 shown in the embodiment of FIG.
Need not be formed. The main surface of the semiconductor substrate 1 including the inner surface of the trench is covered with an insulating film 7 made of silicon oxide or the like. A transfer electrode 3 made of polysilicon or the like is formed on the buried channel 4 via the insulating film 7.
1 is formed. Then, the transfer electrode 31 is covered with a silicon oxide insulating film 71, and then MoSi _{2 is formed} so as to cover the transfer electrode 31 and the element isolation region 10 on the inner wall of the trench.
A light shield film 11 made of, for example, is formed. The surface of the semiconductor substrate 1 including the optical shield film 11 is made of SiO ₂ or Si.
It is protected by a transparent insulating protective film 12 of about several thousand angstroms such as ₃ N ₄ . The pixel unit 5 is P ⁺
The charge transfer shift register unit 3 includes an impurity diffusion region 52 and a buried photodiode 51.
And a transfer electrode 31. The transfer electrode 31 also serves as a control gate electrode. The tip 13 of the embedded photo diode 51 is hereinafter referred to as a storage unit 13.

Next, the operation of the area sensor which is the solid-state image pickup device of this embodiment will be described. FIG. 9 shows the semiconductor substrate 1 (A), the P well 2 (B), the storage portion 13 (C), the boundary portion (D) between the storage portion 13 and the buried photodiode 51, and the buried photodiode 51 (E). FIG. 10 is a potential well distribution diagram along the P ⁺ impurity diffusion region 52 (F), and FIG. 10 shows the buried channel 4 (A ′) and the P well 2 (B ′) between the buried channel 4 and the storage portion 13. And C
FIG. 6 is a potential well distribution diagram along F. Semiconductor substrate 1 and P
A reverse bias is applied between the wells 2. The P well (B) between the embedded photo diode 51 and the accumulating portion 13 and the semiconductor substrate 1 is in a punch-through state, and the excess charge accumulated in the embedded photo diode 51 and the accumulating portion 13 is exceeded. The components leak to the semiconductor substrate 1. Storage unit 13 and embedded photo diode 51
The potential well of is deeper in the storage portion 13 because the P ⁺ impurity diffusion region 52 does not exist. The impurity concentration of the P well in the portion (B ′) between the buried channel 4 and the storage 13 is about 1 × 10 ¹⁵ cm ⁻³ , and its potential well transfers the signal charge in the charge transfer shift register. It is in the punch-through state when doing. The potential well of this portion (B ′) is shallower than the P well 2 of the portion (B) between the storage portion 13 and the semiconductor substrate 1.

Therefore, the embedded photo diode 51
And the excess charge accumulated in the accumulation unit 13 causes the semiconductor substrate 1
So that it does not leak to the buried channel 4. The phenomenon in which excess charges leak into the buried channel 4 of the charge transfer shift register is called blooming, and the potential difference Vm thereof is appropriately determined depending on the degree of leakage. The transfer of the signal charges stored in the storage section 13 and the embedded photodiode 51 to the embedded channel 4 is performed by a positive read pulse applied to the control gate electrode which also serves as the transfer electrode 31. By the read pulse, the potential well of the buried channel 4 is deepened as shown by the dotted potential curve in FIG. 10 so that the B ′ portion is in the punch-through state, and the signal charge is transferred to the buried channel 4 via the storage section 13. As described above, in order to transfer the signal charge from the pixel portion to the charge transfer shift register, the potential of the buried channel is deepened and the punch-through is performed from the storage portion as shown by the potential distribution curve of the dotted line in FIG. Therefore, compared to the conventional case where transfer is performed using the surface portion, there is no barrier well along the transfer channel, the transfer channel width becomes wider, and the transfer time becomes shorter. The signal voltage can be read.

Further, the amount of signal charges that can be stored in the pixel portion is increased as compared with the structure in which the embedded portion 51 alone does not have the storage portion 13. The buried photodiode 4 has a structure extending to the lower part of the buried channel 4, and the upper part and the side wall of the buried channel 4 are covered with the optical shield film 11. Most of the generated carriers flow into the semiconductor substrate 1, the buried photodiode 51, the storage portion 13, etc., and almost no carriers leak into the buried channel 4, so that the smear characteristic is significantly improved. Since there is no control gate electrode, high integration can be achieved.

Next, a method of manufacturing the area sensor of the fourth embodiment will be described with reference to FIGS. 9, 11 and 12.
First, a P-type silicon semiconductor substrate 1 having a P well 2 formed therein
In addition, using a high-acceleration ion implanter whose ion energy (monovalent ions) exceeds 1 MeV, phosphorus is ion-implanted at a depth of about 2 to 3 μm from the main surface of the semiconductor substrate 1 with an energy of about 2 to 4 MeV. Diffusion and embedded photodio
A region 51 is formed (FIG. 11). Next, a trench 50 is formed on the main surface of the semiconductor substrate 1 by anisotropic etching or the like, and boron is ion-implanted around the trench 50 with an energy of 40 to 50 KeV to form a P ⁺ impurity diffusion region 52. Then, the buried channel 4 is formed by diffusing impurities such as phosphorus from the main surface of the semiconductor substrate (FIG. 12). Further, the transfer electrode 31 and the optical shield film 11 are formed on the surface of the semiconductor substrate 1 via an insulating film to complete the area sensor (see FIG. 8).

Next, a fifth embodiment will be described with reference to FIG. The basic structure of the area sensor of this figure is the same as that of FIG. In this embodiment, the tip portion of the buried photodiode 51 projecting toward the buried channel 4, that is, the accumulating portion 13 has an expanding portion 131, which is a single layer as compared with the former embodiment. Are close to the buried channel 4. Therefore, the read pulse is lowered in voltage and the amount of accumulated signal charges is increased. The expansion portion 13 of the accumulation portion formed adjacently on the accumulation portion 13
1 is formed by implanting phosphorus with high energy from a surface of a region on which the buried channel 4 is to be formed on the main surface of the semiconductor substrate by using a high acceleration ion implanter.
In the fourth and fifth embodiments, the impurity concentration of the region (B ′) between the buried channel 4 of the P well 2 and the storage portion 13 is higher than the impurity concentration of the other regions of the P well 2 such as the B region. Can be lowered. If the impurity concentration in the B'region is lowered, punchthrough becomes easier and the signal charges can be easily transferred. The material of the transfer electrode is not limited to polysilicon, but a silicide such as MoSi ₂ , W, Mo, or Ti, a refractory metal, or the like can be used.

[0031]

According to the present invention, due to the above-mentioned structure, the degree of integration is improved, the smear characteristic is improved, and the signal charge can be read by a low-voltage read pulse.

[Brief description of drawings]

FIG. 1 is a sectional view of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a solid-state imaging device according to a third embodiment of the present invention.

FIG. 4 is a plan view of an area sensor of the present invention.

5 is an enlarged plan view of an R portion of the area sensor of FIG.

6 is a partially enlarged cross-sectional view of the solid-state imaging device in FIG.

7 is a potential distribution diagram of the solid-state imaging device of FIG.

FIG. 8 is a sectional view of a solid-state imaging device according to a fourth embodiment of the present invention.

9 is a potential distribution diagram of the solid-state imaging device of FIG.

10 is a potential distribution diagram of the solid-state imaging device of FIG.

FIG. 11 is a sectional view of a solid-state imaging device according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view showing the steps of manufacturing the solid-state imaging device according to the fourth embodiment of the present invention.

FIG. 13 is a sectional view of the manufacturing process of the solid-state imaging device according to the fourth embodiment of the present invention.

FIG. 14 is a sectional view of a conventional solid-state imaging device.

FIG. 15 is a sectional view of another conventional solid-state imaging device.

[Explanation of symbols]

1 N-type silicon semiconductor substrate 2 P well 3 Charge transfer shift register 4 Transfer electrode 5 Pixel part 6 Control gate 7, 71 Insulating film 8 Barrier well 9 Control gate part 10 Element isolation region 11 Optical shield film 12 Insulation protection film 13 Storage part 31 Transfer electrode 50 Trench 51 Embedded photodiode 52 P ⁺ Impurity diffusion region 131 Expansion part of storage part

Claims (7)

[Claims] 1. A semiconductor substrate having a trench formed on a main surface thereof, a first-conductivity-type high-concentration impurity diffusion region formed at the bottom of the trench, and a first-conductivity-type high-concentration impurity diffusion region. A second conductivity type buried photodiode formed below in contact with the high-concentration impurity diffusion region and having one end exposed at the bottom of the trench; and adjacent to the trench, the main surface of the semiconductor substrate. A buried channel of the second conductivity type formed on the semiconductor substrate, a control gate portion formed in a region of the semiconductor substrate between the buried channel and the buried photodiode, and the semiconductor substrate main surface. A control gate electrode formed so as to cover at least the control gate portion, and formed on the main surface of the semiconductor substrate so as to cover the transfer electrode and the control gate electrode. hand An optical shield film, the transfer electrode and the buried channel constitute a charge transfer shift register, the high-concentration impurity diffusion region of the first conductivity type and the buried-type photodiode of the second conductivity type. Is a pixel portion, and is a solid-state imaging device. 2. The solid-state image pickup device according to claim 1, wherein the control gate electrode is also used as the optical shield film. 3. The solid-state imaging device according to claim 1, wherein the control gate electrode is connected to the transfer electrode. 4. The solid-state image pickup device according to claim 1, wherein the buried channel is surrounded by a barrier well of a first conductivity type. 5. A semiconductor substrate having a trench formed in a main surface thereof, a second conductivity type buried channel formed in the semiconductor substrate main surface adjacent to the trench, and at a bottom of the trench and a sidewall thereof. A first conductivity type high-concentration impurity diffusion region formed along the semiconductor substrate, and below the first conductivity-type high-concentration impurity diffusion region in contact with the high-concentration impurity diffusion region; A buried photodiode of a second conductivity type that extends below the buried channel of the second conductivity type and apart from the buried channel; and the transfer electrode and the trench on the main surface of the semiconductor substrate. An optical shield film formed so as to cover the side wall, the transfer electrode and the buried channel constitute a charge transfer shift register, and the first conductivity type high-concentration impurity diffusion region is provided. It said second conductivity type buried photo die and - de constitute a pixel portion, and said transfer electrodes control gate - solid-state imaging device, characterized in that also serves as a gate electrode. 6. A region of the first conductivity type is provided between the buried channel of the semiconductor substrate and the one end of the buried photodiode, and the impurity concentration of the region is the semiconductor of the first conductivity type. 6. The solid-state image pickup device according to claim 5, wherein the impurity concentration is lower than a first conductivity type region of the substrate below the buried photodiode. 7. A step of forming a second conductivity type buried photodiode by ion-implanting impurities into the inside of the semiconductor substrate main surface, and etching the semiconductor substrate main surface to form the buried photodiode. Forming a trench on the trench, and ion-implanting impurities into the trench to form a high-concentration impurity diffusion region of the first conductivity type along the bottom and sidewalls of the trench; and the buried photodiode. A step of contacting the high-concentration impurity diffusion region and projecting its tip in the horizontal direction from the high-concentration impurity diffusion region, and forming a second conductivity type buried channel on the main surface of the semiconductor substrate adjacent to the trench. And arranging the tip of the buried photodiode so as to be separated from the buried channel under the buried channel, and the buried channel. The method further comprises the step of forming a transfer electrode thereon, and the step of forming a control gate electrode which also functions as an optical shield film formed so as to cover the transfer electrode and the sidewall of the trench. Manufacturing method of solid-state imaging device.