JPH0425714B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] The present invention relates to a CCD type monochrome and color solid-state image sensor in which a photoelectric conversion element for extracting a plurality of color signals and optical information, and a scanning element are integrated on a semiconductor substrate. It is related to.

[Prior art]

Solid-state image sensors require an image pickup plate with a resolution comparable to that of the imaging electron tube used in current television broadcasting, and therefore require a photoelectric conversion element that constitutes a matrix of approximately 500 x 500 pixels and an equivalent A scanning element of this type is required. Therefore, the above-mentioned solid-state image sensor is manufactured using MOS large-scale integrated circuit technology, which is relatively easy to achieve high integration, and generally consists of a CCD (photodiode + CCD shift register) or a MOS transistor (photodiode + MOS) as a component. shift register) etc. are used.

FIG. 1a shows the basic configuration of a conventional CCD type solid-state image sensor, which is characterized by low noise. 1 is a photoelectric conversion element made of, for example, a photodiode; 2 and 3 are vertical CCD shift registers and horizontal CCDs for taking out optical signals accumulated in the photoelectric conversion elements to output terminals;
It is a shift register.

If this device is used as is, it can be used for black and white imaging, but if a color filter is stacked on top of the device, it can be used for color imaging. In recent years, research into color solid-state image sensing devices has been active with the aim of color cameras for VTRs, but conventional devices have been pointed out to have problems such as field afterimages and low resolution. Therefore, the present inventors developed a new
We proposed the configuration of a CCD type color solid-state image sensor and improved the conventional drawbacks.

That is, as shown in Fig. 1b, a multi-row CCD
A shift register is provided to separate each color signal.
This is a color solid-state image sensor that uses a CCD shift register to transfer data. In this element, the color signals accumulated in the photoelectric conversion element 1 are transferred to different vertical CCD shift registers 2-1, 2-2, 2-3.
The color signals of two columns in the vertical direction are simultaneously read out. For example, the three primary colors (green, red, blue)
When a color filter is stacked on top of a semiconductor,
Vertical CCD register 2-1 transfers the green signal, 2-2 transfers the red signal, and 2-3 transfers the blue signal, and each of these signals in the two vertical columns is simultaneously transferred to the corresponding horizontal register (for example, 3-1 is Green signal, 3-2 is transferred to red and blue (like red and blue).

However, the amount of signal charge that can be handled is
Limited by the storage capacity of CCD shift registers, especially vertical CCD shift registers;
Storage capacity is reduced due to small dynamic range (ratio of saturation light amount to noise), blooming (a phenomenon that occurs when excess charge exceeding the saturation light amount flows into adjacent pixels or vertical transfer areas) suppression rate, and dark current generation. It gets even smaller. There are problems such as the inability to reduce the pixel size, and it is important to solve these problems in order to improve image quality. The conventional CCD type solid-state image sensor shown in Figure 1a also had the above problem, but in particular, the improved CCD type shown in Figure 1b
type solid-state image sensor, multiple vertical CCDs
Since it is necessary to provide a shift register, the storage capacity becomes smaller and the problem solving becomes more important. Therefore, in order to surpass image pickup tubes and put solid-state image pickup devices into practical use, it is urgently necessary to expand the signal storage capacity of CCD registers.

[Purpose of the invention]

The purpose of the present invention is to improve the above-mentioned drawbacks of the prior art, in which the vertical
An object of the present invention is to provide a solid-state imaging device that can improve dynamic range, reduce dark current, improve blooming suppression rate, and reduce pixel size by expanding the signal storage capacity of a CCD shift register.

[General description of the invention]

In order to achieve the above object, the present invention provides vertical
The device structure should be improved so that the channel depth of the embedded CCD channels that make up the CCD shift register is shallower than the channel depth of the embedded CCD channels that make up the horizontal CCD shift register, or the CCD electrodes formed in the vertical CCD shift register should be The feature is that the potential barrier between the CCD electrodes is made larger than the potential barrier between the CCD electrodes created by the horizontal CCD shift register.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 2 is a diagram showing the structure of a CCD type solid-state image sensor, which is the gist of the present invention. 4 is the area where vertical CCD shift registers are integrated, 5 is the horizontal area
Area where CCD shift registers are integrated, 6
7 is a semiconductor substrate of the first conductivity type (for example, n-type), and 7 is a low concentration diffusion layer for the buried channel, which is of the conductivity type opposite to that of the substrate (for example, p-type) and has a higher impurity concentration than the substrate. be. Here, the substrate 6
The impurity concentration is substantially uniform (to the extent obtained in normal wafer manufacturing) in the region 4 where the vertical CCD shift register is provided and the region 5 where the horizontal CCD shift register is provided. 8,9
indicates a CCD electrode (gate electrode), which is generally made of a first layer of polycrystalline silicon and a second layer of polycrystalline silicon that slightly overlaps the first layer. Here, the semiconductor surface 11 under the second layer polycrystalline silicon electrode 9 has a first layer, in order to make a difference from the surface potential formed under the first layer electrode.
A conductivity type impurity layer is provided. 10 is a gate oxide film. Here, the diffusion depth of channel 7-1 forming the vertical CCD shift register is X _er1
is set to be shallower than the diffusion depth _Xer2 of the channel 7-2 forming the horizontal CCD shift register.

In general, when the diffusion depth is made shallower, the position of the channel that transfers the signal charge rises toward the surface of the substrate, so it is affected by the interface states (traps).
Transfer efficiency decreases with decreasing diffusion depth. As a result, when the transfer rate is increased to 10 ⁶ Hz or higher, the transfer efficiency drops sharply and shading occurs in the image (a phenomenon in which the signal at a position away from the output section decreases and becomes darker).

However, the transfer loss due to the shallow diffusion depth is hardly a problem in the present invention for the following reason. In other words, compared to horizontal CCD shift registers whose transfer speed is 5 to 10MHz, vertical CCD shift registers
This is because the transfer rate of the shift register is 15.7KHz, which is two orders of magnitude slower. Therefore, it is virtually impossible to reduce the diffusion depth of the horizontal CCD shift register below a predetermined value, but according to the inventor's experimental results,
The diffusion depth of the vertical CCD shift register is
It was found that the depth could be reduced to a fraction of that of a CCD shift register.

The capacitance of a CCD electrode per unit area is given by the following equation, assuming that the maximum surface potential is formed at a position half the diffusion depth.

C=1/d _px /ε _px +d _eh /2ε _s ...(1) C: Capacitance d _px : Thickness of gate oxide film ε _px : Electrical conductivity of gate oxide film d _eh : Diffusion depth ε _s : Diffusion Layer conductivity Here, the thickness of the gate oxide film d _px is set to a typical value of 500
Å, if the diffusion depth of the horizontal CCD shift register is again a common value d _eh2 Å1 μm, and the diffusion depth of the vertical CCD shift register is chosen as d _eh1 =0.4 μm, then
Compared to a conventional element in which both registers are set to approximately 1 μm (d _eh1 =d _eh2 =1 μm), approximately twice the capacitance can be obtained. Therefore, the maximum accumulated charge amount is doubled, the dynamic range can be expanded, and the above-mentioned drawbacks can be corrected.

On the other hand, it is necessary to increase the transfer capacity of the horizontal CCD shift register by the amount of charge transferred by the vertical CCD shift register, but unlike the vertical CCD shift register whose dimensions are limited in both two dimensions,
Since the horizontal CCD shift register has a dimension margin in the vertical direction, there will be no problem if the channel width W ₂ of the horizontal CCD shift register is designed to be twice the channel width W ₁ of the vertical CCD shift register.

Next, we will discuss the present invention in which the electrode storage capacity per unit area is increased by a structure different from that of the above-mentioned embodiments.
Figure 3 shows a CCD type image sensor. 4 is vertical CCD
Area where shift registers are integrated, 5 is horizontal
This is the area where CCD shift registers are integrated. 8-1 and 9-1 are polycrystalline silicon for the first and second layers of CCD electrodes constituting the vertical CCD shift register, and 8-2 and 9-2 are the first and second layers constituting the horizontal CCD shift register. second layer
Polycrystalline silicon for CCD electrodes. 11 is the second
This is an impurity layer of the same type as the substrate 6 (that is, the opposite type to the diffusion layer 7) formed on the semiconductor surface under the layer electrode. Here, the impurity concentration C _B1 of the impurity layer 11-1 forming the vertical CCD shift register region is set higher than the impurity concentration C _B2 of the impurity layer 11-2 forming the horizontal CCD shift register region.

FIG. 4a shows the state of the surface potential formed by setting the condition C _B1 >C _B2 . FIG. 4b shows the surface potential formed by a conventional element with C _B1 =C _B2 set. As shown in Figure 4, clock pulses φ ₁ and φ ₂ of “1” level (high voltage) are applied to the right set of CCD electrodes of each vertical and horizontal register, and the “0” level is applied to the left set of CCD electrodes. Consider the situation where clock pulses ₁ and ₂ (0V or low voltage) are applied. In FIG. 5A, due to the condition C _B1 >C _B2 , the potential under the second layer electrode in the vertical CCD shift register is lower than that in the horizontal CCD shift register. Therefore, the potential difference V _B1 between the two electrodes (8-1, 9-1) of the vertical CCD shift register is larger than the potential difference V _B2 of the horizontal CCD shift register. By that amount, the potential difference between the two electrodes on the other side (right side)
V _B1 becomes smaller, and V _B1 < V _B2 .

In the _{case of the} conventional element structure, as _{shown in FIG} .

As a result, the following relationship holds between the potential difference (V' _B1 ) between the present invention and the conventional element.

V _B1 >V' _B1 ...(2) The maximum amount of charge that can be accumulated on the CCD electrode is the product of the CCD electrode capacitance C and V _B (C
×V _B ), V _B1 >V' _B1 Due to the relationship (2), the amount of accumulated charge in the vertical CCD shift register in the device of the present invention is larger than that in the conventional device. This size is 2 to 3 times larger. The reason why there is a limit of 2 to 3 times is as follows. In other words, the amount of accumulated charge depends on the setting conditions of the impurity concentration C _B1 ,
Although it increases as the concentration increases, the electrode 9-
If a situation occurs where the potential drops below the potential _B (V _B1 = 0), a transfer barrier occurs (the potential difference between the front and rear rows disappears or is reversed, so the charge does not move as intended). Therefore, an upper limit is added to the concentration C _B1 .

On the other hand, in the device structure of the present invention, since V _B1 decreases (that is, the drift electric field decreases), a decrease in transfer speed is expected. However,
As mentioned above, the transfer speed of vertical CCD shift registers is several hundred times slower than that of horizontal CCD shift registers, so there is no charge left behind due to charge transfer, and it can be used in horizontal CCD shift registers that require high speed. V _B2 is the same as the conventional element (V _B2 = V′ _B2 )
If you set it to , there will be no problem with leftovers. V _B2 =
To set V′ _B2 , the impurity concentration of the horizontal CCD shift register can be selected in the same way as for conventional elements.

The CCD solid-state imaging device of the present invention can be easily manufactured, for example, by the following manufacturing process. In the embodiment shown in FIG. 2, the amount of ion implantation of impurity atoms for the low concentration diffusion layer is changed from the vertical CCD shift register region to the horizontal CCD shift register region.
The number of shift register regions may be increased, and then annealing for impurity diffusion may be performed for a predetermined period of time.
Here, in order to increase the amount of ion implantation in the horizontal CCD shift register area, a photoresist for photolithography is applied to the vertical CCD register area in advance to serve as a mask during implantation, and after implanting a predetermined amount of impurities, It is sufficient to remove the resist of the vertical CCD shift register, and then implant a predetermined amount in both the horizontal and vertical register areas.

In the case of the embodiment shown in FIG. 3, after forming the first layer of polycrystalline silicon electrodes, using this polycrystalline silicon as a mask, impurities are implanted into the region corresponding to the second layer of silicon electrodes. conduct. Here, the amount of implantation in the vertical CCD shift register area is
In order to make the CCD shift register area larger than the CCD shift register area, contrary to the above case, cover the horizontal register area with resist in advance, remove only the vertical register area first, then remove the resist, and then remove the vertical and horizontal register areas. In both cases, a predetermined amount of implantation may be performed.

The above explanation has focused on the interline type, which has a high degree of integration among CCD type image sensors, but without going beyond the scope of the present invention, it may also be applied to the frame transfer type, which is another type. It is obvious that the present invention can also be applied to. Furthermore, even in the case of a two-story image sensor in which a photoconductive thin film is laminated instead of the above-mentioned photodiode as a photoelectric conversion element, the present invention can be directly applied to the scanning element that serves as the laminated substrate. In the embodiments described above, the photodiode may be replaced by an amorphous photoconductive thin film element.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to expand the signal accumulation capacity of the vertical CCD shift register that imposes an upper limit on the amount of accumulated charge, thereby increasing the dynamic range with respect to the amount of incident light. In addition, the blooming suppression effect is improved, and since it is less susceptible to the adverse effects of dark current, high-quality images can be obtained even at high temperatures, and the pixel density can be increased (i.e., resolution) because the pixel size can be reduced. .

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of a conventional CCD type solid-state image sensor, and Fig. 2 is a diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing the structure of a CCD solid-state image sensor according to another embodiment of the present invention. FIG. 4 is a diagram showing the structure of a CCD solid-state image sensor according to another embodiment of the present invention. FIG. 1...Photoelectric conversion element, 2...Vertical CCD shift register, 3...Horizontal CCD shift register, 4
...Vertical CCD shift register area, 5...Horizontal
CCD shift register region, 6...first conductivity type semiconductor substrate, 7...buried channel diffusion layer,
8, 9...CCD electrode, 10...gate oxide film,
11... Second conductivity type impurity layer.

Claims (1)

[Claims] 1. A group of photoelectric conversion elements for extracting optical information, an embedded vertical CCD shift register and a horizontal CCD shift register that sequentially transfer optical signal charges accumulated in the elements are integrated on the same semiconductor substrate. In solid-state imaging devices, the above vertical CCD shift register and horizontal CCD
The impurity concentration in the region where the shift register is provided is substantially uniform, and the charge storage capacity per unit area of the electrode in the vertical CCD shift register is equal to that of the horizontal CCD shift register.
A solid-state imaging device characterized by having a structure in which the charge storage capacity is larger than the charge storage capacity per unit area of an electrode in a shift register. 2. The potential difference between the potential under the storage electrode and the potential under the transfer electrode in the vertical CCD shift register is set higher than the potential difference between the potential under the storage electrode and the potential under the transfer electrode in the horizontal CCD shift register. Characteristic claim 1
The solid-state imaging device described in Section 1. 3. The solid-state imaging device according to claim 1 or 2, wherein the impurity concentration under the transfer electrode of the vertical CCD shift register is higher than the impurity concentration under the transfer electrode of the horizontal CCD shift register. element. 4. The solid-state imaging device according to claim 1, wherein the depth of the buried channel forming the vertical CCD shift register is shallower than the depth of the buried channel forming the horizontal CCD shift register.