JPH0789581B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a device structure suitable for electrically isolating and shielding a desired region and a manufacturing method thereof.

[Background of the Invention]

The present invention relates to a device structure that separates and shields a desired region, and can be effectively applied to a semiconductor memory and an image pickup device, and therefore will be described here in connection with an image pickup element.
The configuration of a conventional solid-state image pickup device is as shown in FIGS. 1 and 2 as shown in Japanese Patent Publication No. 59-17585.

FIG. 1 is an example of the configuration of a solid-state imaging device. Reference numeral 1 is one picture element of the light receiving portion consisting of the photodiode 101 and the vertical switching MOS transistor 102. Reference numerals 2 and 3 are vertical and horizontal shift registers, 103 is a horizontal switching MOS transistor, 104 is a video voltage source, 4 is a vertical gate line, and 5 is a vertical gate line.
Is a vertical signal line, and 6 is a signal output line.

FIG. 2 is a sectional structure of one picture element. 7,8 correspond to 4,5 in Fig. 1. 9 is, for example, a P-type Si substrate (usually an impurity concentration of about 10 ¹⁵ mm ⁻³ ), 10 is polycrystalline Si for gate electrode, 11 is a field oxide film, 12 is a gate insulating film, 121 and 122 are N ⁺ diffusion layers (impurity concentration). About 10 ²⁰ cm ^-3 is formed by ion implantation, thermal diffusion, etc., 13 is P ⁺ layer (usually impurity concentration 2 × 10 ¹⁵ cm ^-3
~ 10 ¹⁷ cm ^-3 , formed by ion implantation, thermal diffusion, etc.). In addition, 30 has shown the incident light. This conventional P ⁺
The advantages of providing layer 13 are listed below.

Only the charge accumulated in the photodiode composed of the N ⁺ diffusion layer 121 and the P-type Si substrate 9 is taken into 122 through the gate 10 and the photogenerated charge (due to the blooming or smear phenomenon) in another region is 122. 13 P ^{+ to get in}
It can be prevented by using a layer barrier.

Due to the P ⁺ layer 13, it is possible to prevent charges generated by light and charges overflowing from 121 from entering the vertical signal line 8 via the drain region 122 at a deep portion in the substrate. That is, the smear charge can be suppressed by the P ⁺ layer 13.

However, the following points have not been taken into consideration in this conventional example. That is, since the junction capacitance between the drain 122 and the P ⁺ layer 13 increases and the parasitic capacitance of the vertical signal line 8 increases,
Random noise caused by switching the vertical signal line was increased, and the S / N (signal-to-noise ratio) of the device was deteriorated. Furthermore, since the effective barrier is determined not by the surface concentration of the P ⁺ layer 13 but by the lower concentration near the junction, a large amount of ion implantation was achieved (for example, P ⁺ depth 3 μm, drain depth If the thickness is 1 μm, the concentration near the junction will drop to about 1/2 of the surface).

[Object of the Invention]

An object of the present invention is to provide a solid-state imaging device that shields a predetermined area and suppresses performance deterioration such as increase in parasitic capacitance.

[Outline of Invention]

The present invention selectively forms a high-concentration layer in a region adjacent to the drain bottom surface (junction surface), suppresses an increase in capacitance near the junction, and efficiently forms a high-concentration layer.

Example of Invention

 Hereinafter, the present invention will be described using examples.

FIG. 3 shows a pixel structure of a conventional MOS type image pickup device (second
It corresponds to the figure). The high concentration layer 113 of the present invention is provided only around the drain 122. The impurity concentration distribution in the cross section AA ′ in this figure is as shown in FIG. 4, and the high concentration P ⁺ layer 113 of the present invention has a depth x
_It has a peak at _P , and is close to the substrate impurity concentration near the junction (x _J ). At this time, P ⁺ layer 113 is N
⁺ It may be in contact with or out of the layer 122, and it can be freely controlled. Note that this side surface region does not necessarily have to be provided. The presence or absence of this side surface region is determined according to the purpose of other element characteristic control, and the effect of the present invention does not change even without this side surface region. Therefore, it is possible to prevent the pseudo signal from being mixed into the signal line 8 due to blooming, smearing, or the like due to the potential barrier due to the concentration difference (Δn) without significantly increasing the junction capacitance.

Next, an example of a manufacturing method for realizing the device of FIG. 3 will be described with reference to FIG. For example, the thick oxide film 130 formed on the P-type Si substrate 9 is selectively removed and re-oxidized to form a thin oxide film 131 (a). Next, we focused on high voltage (high energy ion implantation technology)
The boron ions accelerated by 100 keV) are focused to about 1 μm and scanned (132), and the boron ions 133 are implanted on the substrate to form the high concentration layer 134 of the present invention (up to the figure b).
At this time, the peripheral portion 135 of the high-concentration layer 134 can be formed in a self-aligned manner by making the peripheral portion 135 of the oxide film 130 inclined (in order to prevent boron from reaching the substrate 9 in a thick oxide film portion). There is a need). Where the oxide film 130
The width of the side surface region of the high-concentration layer 134 can be freely controlled by changing the inclination angle around the driving portion. For example, if the inclination angle is made steep, the side surface region of the high concentration layer 134 can be substantially eliminated. As another method, the peripheral portion 135 of the high concentration layer can be formed by controlling the acceleration voltage of boron ions in the peripheral portion 135 of the high concentration layer.

Next, after selectively removing the oxide film, the film is re-oxidized to form a gate oxide film 136 (up to FIG. C). The following is similar to the normal MOS transistor formation method.
138 is selectively formed, and N ⁺ layer 137 serving as a source and a drain is formed by A _S ion implantation in a self-aligned manner (up to the figure d).

Similarly, in the following embodiments, the focused ion beam technique (high energy ion implantation technique) can be used for manufacturing, and therefore the present invention will be described with reference to cross-sectional views.

FIG. 6 shows the device in the P-type well layer 140 on the N-type substrate 139 in which the invention of FIG. 3 is implemented.

Here, the bottom surface of the high concentration P ⁺ layer 13 may be in contact with or away from the substrate 139. The presence or absence of the side surface region of the high-concentration P ⁺ layer 13 is determined according to the purpose of controlling other element characteristics, but the presence or absence of this side surface region does not affect the effect of the present invention.

FIG. 7 shows an example of an N-type substrate, but a predetermined area (122
And 142) are shielded, the bottom surface is formed by reverse biasing a normal PN junction, and the periphery is provided with the high concentration layer 141 of the present invention. 141 may be in contact with or out of 122. The bottom surface of 141 may be in contact with the substrate 139 or may be separated therefrom.

FIG. 8 shows the high-concentration layer 143 only around the drain of the P-type substrate 9.
It has a shield effect on the side. 143
May be in contact with 122 or may be remote.

Although the MOS type image pickup device has been described in the above embodiments, the CC part in which the drain portion is the channel of the charge transfer device is used.
The present invention can be similarly applied to the D-type image pickup device. Also, the effect of the present invention does not change even if the conductivity type is reversed.

In the following embodiment, a predetermined region is formed in a well layer of a CMOS device.

In FIG. 9, 150 is an N-type Si substrate, 151 is a P-type well layer,
This is a semiconductor device in which an N-channel MOS transistor 152 is integrated in a predetermined well layer 153 to be shielded. A high concentration P ⁺ layer 154 of the present invention is formed around 153. This P ⁺ layer 154
As a result, the diffusion of charges from the other well region 151 can be prevented, and the resistance of the well layer 153 can be substantially reduced, so that the malfunction of the MOS transistor due to the potential fluctuation of the well layer can be prevented.

In FIG. 10, the inside of 153 is further separated and shielded to prevent jumping of clocks or the like between MOS transistors.

11 and 12 show the bottom of the well layer 153 shown in FIGS. 9 and 10 which is separated and shielded by joining with the substrate.

9 to 12, a P-type substrate is used instead of the N-type substrate 150, and the well layer 151 is formed on the surface, and the present invention has the same effect. Further, the effect can be exhibited even if the present invention is carried out without providing the well layer on the P-type substrate.

Even if the conductivity type is completely reversed in the above embodiment, the effect of the present invention does not change.

〔The invention's effect〕

According to the present invention, by forming a high-concentration layer in a predetermined region, it is possible to prevent deterioration of device characteristics due to unnecessary diffused charges and the like, and prevent malfunction of the device. Output diffusion layer (N ⁺ layer or charge transfer device channel) in the pixel section of a solid-state image sensor
If it is implemented in the periphery, it is effective in preventing the mixing of pseudo signals due to smear, blooming, etc., and suppressing the increase in parasitic capacitance and the like.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an image sensor, FIG. 4 is a diagram showing impurity distribution, FIG. 5 is a diagram showing a method for manufacturing a semiconductor device, and FIG.
FIGS. 3, 3 and 6 to 12 are sectional views of the semiconductor device. 122 …… Drain, 113 …… High concentration layer, 134,13,141,143,1
54 …… High concentration layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Nakamura 1-280 Higashi Koigakubo, Kokubunji City, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hitoshi Kume 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Inside the Central Research Laboratory (56) References: Actual development Sho 55-45245 (JP, U)

Claims (2)

[Claims] 1. A photoelectric conversion element serving as a source of a plurality of MOS transistors on a semiconductor substrate, and a plurality of photoelectric conversion elements for reading out optical signal charges accumulated in the photoelectric conversion element via gates of the plurality of MOS transistors. A vertical signal transfer element that functions as a drain of a MOS transistor, and a horizontal signal transfer element that drives the vertical signal transfer element to transfer the optical signal charge in the vertical direction and then transfers the optical signal charge in the horizontal direction are provided. In the solid-state imaging device, the vertical signal transfer element is provided for transferring a first semiconductor layer provided on the semiconductor substrate and the optical signal charge provided on a surface of the first semiconductor layer. A second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer, and the first semiconductor layer provided in a region of the first semiconductor layer in contact with the bottom surface of the second semiconductor layer. Conductivity type And a third semiconductor layer having an impurity concentration higher than that, and the impurity concentration in the third semiconductor layer has a peak value at a position away from the bottom surface of the second semiconductor layer. A solid-state imaging device characterized in that 2. A photoelectric conversion element serving as a source of a plurality of MOS transistors on a semiconductor substrate, and a plurality of the photoelectric conversion elements for reading out optical signal charges accumulated in the photoelectric conversion elements via gates of the plurality of MOS transistors. A vertical signal transfer element that functions as a drain of a MOS transistor, and a horizontal signal transfer element that drives the vertical signal transfer element to transfer the optical signal charge in the vertical direction and then transfers the optical signal charge in the horizontal direction are provided. A method of manufacturing a solid-state imaging device, comprising:
The vertical signal transfer element includes a first semiconductor layer provided on the semiconductor substrate, and the first semiconductor layer provided on the surface of the first semiconductor layer for transferring the optical signal charges. Is a second semiconductor layer having an opposite conductivity type and a second semiconductor layer having the same conductivity type as the first semiconductor layer provided in a region of the first semiconductor layer in contact with the bottom surface of the second semiconductor layer, and more than that. A third semiconductor layer having a high impurity concentration, and the impurity concentration in the third semiconductor layer has a peak value at a position away from the bottom surface of the second semiconductor layer. 3. The method for manufacturing a solid-state imaging device, wherein the semiconductor layer 3 is formed by an ion implantation technique using a focused ion beam.