JP2594923B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device having driving conditions suitable for reducing dark current.

[Conventional technology]

As described in Japanese Patent Application No. 59-146822, a conventional solid-state imaging device has a conventional LOCOS between photoelectric conversion elements (photodiodes) and between a photodiode and charge transfer means.
It is covered with a thick oxide film by the method. In this region, the charge of the opposite conductivity type to that of the signal charge was accumulated under the thick oxide film without depending on the voltage of the transfer electrode of the charge transfer means (it was in a so-called accumulation state). However, for the following reasons, a gate insulating film (thin oxide film) and a gate electrode are provided in the
The field plate method, which separates elements with simple MOS transistors, has been reviewed.

Due to the lateral spread of the thick oxide film (called bird beak), it is difficult to miniaturize the isolation region.

Due to the lateral diffusion of the high-concentration impurity layer provided under the thick oxide film, the effective channel width of the MOS transistor is narrowed (narrow channel effect).

As an example of this field plate type element, there is an element described on pages 444 to 447 of IEDM85 (IEDM85pp444 to pp447).
One of the problems of this element is as follows. That is, a depletion layer is generated on the substrate surface under the gate oxide film in the isolation region by the application of the gate voltage, thereby generating charges due to dark current. For this reason, this charge is mixed into the signal and becomes noise.

[Problems to be solved by the invention]

FIG. 2 shows a conventional solid-state imaging device using a field plate method.

Fig. 2 shows an illustration of IEM '86 (LEDM'86).
It corresponds to Fig. 4 of the paper shown in pp444 to pp447, and shows a pixel cross section of a field plate type solid-state imaging device. Numeral 31 denotes a photoelectric conversion element portion comprising a photodiode, 32 denotes a vertical charge transfer means (CCD), 3
3 is a gate for reading, and 34 is an element isolation region. 35
Is a high-concentration layer P ⁺ for element isolation (same conductivity type as P-well),
36 is a gate oxide film, 37 is a gate electrode (read gate,
Shared with the vertical CCD transfer gate). Thus, the element isolation region 34 is controlled by the transfer gate electrode 37. In such an element, when a high level voltage is applied to the transfer gate electrode, the surface of the high concentration layer 35 is also depleted. Due to this surface depletion, unnecessary noise charges due to dark current are generated on the surface (gate oxide film interface) of the high concentration layer 35. This point is not taken into consideration in the above-mentioned conventional device, and there is a problem that random noise increases due to dark current, white spot unevenness due to uneven dark current, fixed pattern noise, and the like.

An object of the present invention is to suppress generation of dark current in the element isolation region.

[Means for solving the problem]

The gate electrode on the isolation region is also used as a vertical CCD transfer electrode. A high or low level potential is applied during the horizontal blanking period, and only charges are accumulated in the vertical CCD during the horizontal scanning period. On the other hand, it is considered that the dark current mainly occurs during a long horizontal scanning period. In view of the above, it is an object of the present invention to set the gate electrode on the isolation region to a low-level potential during the horizontal scanning period and to accumulate the voltage under the gate (accumulation).
mlation) is achieved by maintaining it in a state.

[Action]

The vertical CCD is usually composed of first and second transfer electrodes, and these two electrodes are formed as wiring on a separation territory between the photodiodes. For this reason, the isolation region is controlled by the potential of the wiring of the first transfer electrode close to the semiconductor substrate,
It is not controlled by the potential of the second transfer electrode wiring provided on the first transfer electrode wiring. On the other hand, in order to accumulate charges in the vertical CCD, the potential of any of the first and second transfer electrodes may be increased. As a result, by setting the first transfer electrode to a low-level potential and the second transfer electrode to a high-level potential during the horizontal scanning period, the element isolation region is set in an accumulation state, and dark current is reduced. The signal can be stored in the vertical CCD.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIGS. 1 (a) and 1 (b) are a sectional view and a potential view taken along line BB 'of FIG. 3 (a). FIG. 3A is a plan view of a light receiving portion of the charge transfer type solid-state imaging device, where 1 is a photoelectric conversion device,
Reference numeral 2 denotes a vertical CCD shift register driven by four phases, 3 denotes an active area (areas other than element isolation areas, and 4, 5, 6, and 7 denote vertical CCD shift registers).
The first, second, third, and fourth transfer electrodes of the CD shift register are shown, and 8 is a gate region for reading signals. FIG. 3 (b) shows the clock timing, where 9 indicates a horizontal blanking period, and 10 indicates a horizontal scanning period. φ _V1 , φ _V2 , φ _V3
And φ _V4 are clock pulses applied to the transfer electrodes 4, 5, 6, and 7, respectively. FIG. 3 (c) is AA 'of FIG. 3 (a).
For example, 11 is an N-type substrate, and 12, 13 are photodiodes. a p-type well layer and an n-type layer. 14 is a gate oxide film, and 15 is a p-layer for element isolation. Third
Figure (d) shows is V _PD a Potenshiyaru view of t = t ₁ reset potential, V _W of the photodiode is a potential of the p-type well layer 12, shows how the signal charge Q _s is accumulated in the photodiode ing.

FIG. 1 is a sectional view taken along the line BB ′ of FIG.
Reference numeral 16 denotes a p-type well layer for a vertical CCD, reference numeral 17 denotes an N-type layer serving as a channel, and reference numerals 18 and 19 denote gate oxide films. _VH (V _L ) in FIG. 1B is the potential under the transfer gate when the clock φ _V1 is at a high (low) level, and the transfer charge Q _A (Q _A ′ + Q _A )
Are transferred for one stage.

The operation of the present invention will be described below. In the present invention, since φ _V1 and φ _V3 are at a low level during the horizontal scanning period 10 in FIG. 3B, the separation region between the photodiodes is formed on the substrate surface of the separation region as shown in FIG. 3D. since the electric charge of the signal electrodes Q _S and opposite type is accumulated, the potential is summer the same potential as the p-type well layer 12. Therefore, no depletion layer is formed in the isolation region, and generation of dark current can be suppressed. Meanwhile, vertical CCD
In, during a horizontal scanning period (t = t _1), the signal charge Q _A is 5,
It is accumulated under the electrode of 7. Enters the horizontal blanking period, t = t ₂ and sometimes the transfer gates 6 gate (phi _V3) goes high, stores signal charges Q _A at the transfer electrodes 5, 6, 7. Thereafter, during the period from t = t _{3 to} t ₁₀ , the same transfer as in a normal four-phase drive CCD is performed. Then at t = t _11, the next stage of the transfer gate 5 was the signal charge Q _A and the low level potential of the transfer gate 6 ', 7' after storing under moves to the scanning period. Thus, the vertical CCD transfer operation can be performed, and the generation of dark current in the element isolation region can be suppressed.

FIG. 4 shows another embodiment, in which the present invention is also applied to an isolation region between a photodiode and a vertical CCD. Reference numerals 20 and 21 denote first-layer gate electrodes, and reference numerals 4 and 5 denote second and second gate electrodes, respectively. This is the third-layer gate electrode. Reference numeral 21 denotes a separation gate electrode, which suppresses dark current generation from under the gate electrode 21 by setting the voltage to a low level and keeping the substrate surface under the gate electrode 21 in an accumulation state. I have. Also, the dark current of the isolation region other than the gate region 8 of the readout gate electrode 20 is low for most of the time because the potential of 20 is low level.
Can be suppressed. Dark current from the separation region between the photodiodes can be suppressed as in the embodiment of FIG.

FIG. 5 shows still another embodiment. The gate electrodes 20 and 21 in FIG. 4 are used as a common gate electrode 23, and the gate electrode 23 is also provided between the photodiodes.

In the above embodiment, the vertical CCD is described as being driven by four phases, but it is apparent that the present invention can be applied regardless of the vertical CCD system. Also, the photodiode is pnp
It is clear that the present invention can be implemented similarly with a well structure and a MOS diode structure, and the effect can be exhibited.

〔The invention's effect〕

According to the present invention, between the photoelectric conversion element, and between the photoelectric conversion element and the vertical CCD shift register to perform a gate electrode through a gate oxide film, at least in a field plate type charge transfer solid-state imaging device, During the scanning period, charges of the opposite conductivity type to the signal charges can be stored under the gate oxide film, so that there is an effect that generation of dark current in the element isolation region can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram showing a prior art, FIG. 3 is a diagram showing an embodiment of the present invention,
4 and 5 show another embodiment of the present invention.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Haruhisa Ando 1-280 Higashi Koigakubo, Kokubunji-shi Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-214172 (JP, A) JP-A-61-114663 (JP, A)

Claims (1)

(57) [Claims] 1. A solid-state imaging device in which a plurality of photoelectric conversion elements and vertical charge transfer means for transferring signal charges accumulated in the photoelectric conversion element group are integrated on the same semiconductor substrate.
A first gate electrode serving also as one transfer electrode of the vertical charge transfer means is provided on the semiconductor substrate in an element isolation region between the photoelectric conversion elements via a gate insulating film, and the first photoelectric conversion element and the charge A second gate electrode serving also as another transfer electrode of the vertical charge transfer means is provided on the semiconductor substrate in the element isolation region between the transfer means and the vertical charge transfer means via the gate insulating film, and during a horizontal scanning period, The first and second electric charges are accumulated at the interface between the gate insulating film and the semiconductor substrate so that the electric charge having the opposite conductivity to the signal electric charge is accumulated and the signal electric charge is accumulated in the vertical charge transfer means. A predetermined voltage is applied to the gate electrode of the solid-state imaging device.