JPH05145056A - Solid state image sensor - Google Patents
Solid state image sensorInfo
- Publication number
- JPH05145056A JPH05145056A JP3303065A JP30306591A JPH05145056A JP H05145056 A JPH05145056 A JP H05145056A JP 3303065 A JP3303065 A JP 3303065A JP 30306591 A JP30306591 A JP 30306591A JP H05145056 A JPH05145056 A JP H05145056A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- layer
- type layer
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007787 solid Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims 10
- 238000003384 imaging method Methods 0.000 claims 7
- 230000000694 effects Effects 0.000 abstract description 3
- 238000001444 catalytic combustion detection Methods 0.000 description 18
- 238000005468 ion implantation Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
- H01L27/14843—Interline transfer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電荷結合装置に係り、
特に、小型化に好適な電荷結合装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device,
In particular, the present invention relates to a charge coupled device suitable for miniaturization.
【０００２】[0002]
【従来の技術】図２は、従来例のＣＣＤ型固体撮像素子
の画素部の断面図を示したものである。なお、この素子
については、小野他、特開平3−16263号公報において述
べられている。従来のＣＣＤ型撮像素子の動作について
簡単に説明する。Ｎ型層３，９とＰ型ウェル層２及びＰ
型層５からなるホトダイオードにおいて光信号が信号電
荷に変換され蓄積される。ホトダイオードに蓄積された
信号電荷は図中矢印で示されるように読み出しチャンネ
ル部４０を経て垂直ＣＣＤのチャンネルとなるＮ型層１
３へ転送される。なお、Ｐ型層１２は垂直ＣＣＤのチャ
ンネルとなるＮ型層１３からの空乏層の伸びを抑えるこ
とによりスミア雑音を抑圧するために設けられている。
また、深くて不純物濃度の薄いＮ型層３はホトダイオー
ドからの空乏層を伸ばし基板内で発生した電荷が垂直Ｃ
ＣＤのＮ型層１３へ漏れ込むことによるスミア雑音を抑
圧するために設けられている。また、垂直ＣＣＤ部並び
に読み出し部には絶縁膜６を介してゲート電極１４が設
けられている。従来、素子では、Ｎ型層９からの信号電
荷読み出し時のチャンネルとなるＮ型層９の１部がＮ型
基板１表面４１に達しているため、多量の生成再結合中
心をもつＳｉ／ＳiＯ2界面で発生する暗電流がホトダイ
オードに流れ込んでしまうという問題については考慮さ
れていなかった。2. Description of the Related Art FIG. 2 is a sectional view of a pixel portion of a conventional CCD type solid-state image pickup device. This element is described in Ono et al., Japanese Patent Laid-Open No. 3-16263. The operation of the conventional CCD image pickup device will be briefly described. N-type layers 3 and 9 and P-type well layer 2 and P
In the photodiode composed of the mold layer 5, an optical signal is converted into a signal charge and stored. The signal charge accumulated in the photodiode passes through the read channel portion 40 as shown by the arrow in the figure, and becomes the channel of the vertical CCD N-type layer 1
3 is transferred. The P-type layer 12 is provided to suppress the smear noise by suppressing the extension of the depletion layer from the N-type layer 13 serving as the channel of the vertical CCD.
Further, the N-type layer 3 which is deep and has a low impurity concentration extends the depletion layer from the photodiode and the charges generated in the substrate are vertical C
It is provided to suppress smear noise due to leakage into the N-type layer 13 of the CD. Further, a gate electrode 14 is provided in the vertical CCD section and the reading section via the insulating film 6. Conventionally, in the device, since a part of the N-type layer 9 that serves as a channel at the time of reading signal charges from the N-type layer 9 reaches the surface 41 of the N-type substrate 1, Si / SiO 2 having a large number of generation / recombination centers. No consideration was given to the problem of dark current flowing at the two interfaces flowing into the photodiode.
【０００３】[0003]
【発明が解決しようとする課題】しかし、信号電荷読み
出しチャンネルとなるＮ型層９がＮ型基板１表面４１に
達しないようにＮ型層９をＰ型層５で完全に覆ってしま
うと、アイソレーション部４２と同じ構造となり、信号
電荷の読み出しが極めて困難である。However, if the N-type layer 9 is completely covered with the P-type layer 5 so that the N-type layer 9 serving as a signal charge read channel does not reach the surface 41 of the N-type substrate 1, Since it has the same structure as the isolation part 42, it is extremely difficult to read the signal charge.
【０００４】本発明の目的は、上記問題点を対策するこ
とにある。An object of the present invention is to solve the above problems.
【０００５】[0005]
【課題を解決するための手段】上記目的は、スミア雑音
抑圧のために設けられたＮ型層３よりも浅くて不純物濃
度の高いＮ型層を新たに設けることにより達成される。The above object can be achieved by newly providing an N-type layer having a higher impurity concentration and being shallower than the N-type layer 3 provided for suppressing smear noise.
【０００６】[0006]
【作用】新たに設けられたＮ型層３よりも浅くて不純物
濃度の高いＮ型層により、信号電荷読み出しチャンネル
となるＮ型領域が基板内部に形成されるので、信号電荷
の読み出しを行うことができる。Since the N-type layer, which is shallower than the newly provided N-type layer 3 and has a high impurity concentration, forms an N-type region serving as a signal charge read channel inside the substrate, the signal charge is read out. You can
【０００７】[0007]
【実施例】以下、本発明の実施例を図面を用いて説明す
る。本実施例の説明の前にＣＣＤ型撮像素子全体の中で
画素の占める位置について述べる。図３はインターライ
ンＣＣＤ型撮像素子の平面構成図をあらわしたものであ
る。画素１５は図中破線で囲まれた部分で、ホトダイオ
ード１６，読み出しゲート電極１７，垂直シフトレジス
タ１８からなっている。図中矢印で示したものが信号電
荷の転送方向である。ホトダイオード１６において光電
変換され、蓄積された信号電荷は、読み出しゲート電極
１７を経て垂直シフトレジスタ１８に転送され、さらに
水平シフトレジスタ１９，出力アンプ２０を経て外部回
路に出力される。なお、例えば垂直シフトレジスタ１
８，水平シフトレジスタ１９はそれぞれ４相（φＶ1〜
φＶ4），２相（φＨ1，φＨ2）パルスで駆動される。Embodiments of the present invention will be described below with reference to the drawings. Prior to the description of the present embodiment, the position occupied by pixels in the entire CCD image pickup device will be described. FIG. 3 is a plan view of an interline CCD type image pickup device. The pixel 15 is a portion surrounded by a broken line in the drawing and includes a photodiode 16, a read gate electrode 17, and a vertical shift register 18. The direction indicated by the arrow in the figure is the transfer direction of the signal charge. The signal charges photoelectrically converted and accumulated in the photodiode 16 are transferred to the vertical shift register 18 via the read gate electrode 17, and further output to the external circuit via the horizontal shift register 19 and the output amplifier 20. Note that, for example, the vertical shift register 1
8 and the horizontal shift register 19 have four phases (φV1 ~
φV4), two-phase (φH1, φH2) pulse drive.
【０００８】図４は本発明の一実施例の画素部断面図を
示したものである。本実施例が図２に示す従来例と異な
る二点の、一つは基板表面のＰ型層５によりホトダイオ
ードとなるＮ型層９を覆ったことである。これにより、
Ｎ型層９が基板表面に達していることにより発生する暗
電流をなくすることができる。他の一つはＮ型層３より
も浅くて不純物濃度の高いＮ型層３０を新たに設けたこ
とである。これにより、不純物濃度の薄くて深いＮ型層
３によりもたらされるスミアの抑圧効果を維持したまま
で図中矢印４３で示すような信号電荷読み出しチャンネ
ルが形成されるので、信号電荷の読み出しが可能とな
る。なお、Ｎ型層３の領域は空乏化する領域であり極め
て濃度の薄いＰ型層でもよい。FIG. 4 is a sectional view of a pixel portion according to an embodiment of the present invention. This embodiment is different from the conventional example shown in FIG. 2 in that one is that the P-type layer 5 on the surface of the substrate covers the N-type layer 9 to be a photodiode. This allows
The dark current generated by the N-type layer 9 reaching the substrate surface can be eliminated. The other is to newly provide an N-type layer 30 that is shallower than the N-type layer 3 and has a high impurity concentration. As a result, a signal charge read channel as shown by an arrow 43 in the drawing is formed while maintaining the smear suppression effect brought about by the N-type layer 3 having a low impurity concentration and a deep depth, so that the signal charge can be read. Become. The region of the N-type layer 3 is a depleted region and may be a P-type layer having an extremely low concentration.
【０００９】図５は本発明を実施した画素部の断面図を
示したものである。本実施例が図４に示す実施例と異な
る点は、ホトダイオード９と垂直ＣＣＤのＮ型層１３の
間に厚い絶縁膜４５と不純物濃度の高いＰ型層４４を設
けることにより、アイソレーション効果を向上している
ことである。FIG. 5 is a sectional view of a pixel portion embodying the present invention. This embodiment is different from the embodiment shown in FIG. 4 in that a thick insulating film 45 and a P-type layer 44 having a high impurity concentration are provided between the photodiode 9 and the N-type layer 13 of the vertical CCD to improve the isolation effect. That is improving.
【００１０】本発明の別の一実施例の画素部の断面図を
示したものを図１に示す。本実施例が図４に示す実施例
と異なるところは、一つにはアイソレーション部分にお
いてＮ型層３０のない、Ｎ型層２１としたところであ
る。これにより、Ｎ型層３０の追加により困難となって
いたアイソレーションを確実に行うことができる。第二
は、ホトダイオードのＰ型層５とＮ型層９間の位置ずれ
を同程度（Ｌｉｓｏ＝Ｌｒ）としたことである。これに
より、ホトダイオードとなるＮ型層９を有効に使うこと
ができるので蓄積電荷量を増やすことができる。第三
は、Ｐ型層７をＮ型層９よりも浅く形成したことであ
る。これにより、信号電荷の読み出しチャンネル２２を
Ｐ型層７より深くすることが可能となり垂直ＣＣＤ下部
の中央の部分を通して信号電荷を読み出すことができ、
各拡散層の合わせや加工ずれに対する影響を受けにくく
することができる。なお、Ｎ型層２１は不純物濃度や深
さの異なる複数の拡散層からなっていても全く同様の効
果がある。これにより、設計の裕度を増すことができ
る。FIG. 1 shows a sectional view of a pixel portion of another embodiment of the present invention. The present embodiment is different from the embodiment shown in FIG. 4 in that the N-type layer 21 without the N-type layer 30 in the isolation portion is used. As a result, the isolation, which has been difficult due to the addition of the N-type layer 30, can be reliably performed. Secondly, the positional displacement between the P-type layer 5 and the N-type layer 9 of the photodiode is set to the same level (Liso = Lr). As a result, the N-type layer 9 serving as a photodiode can be effectively used, and the amount of accumulated charge can be increased. Thirdly, the P-type layer 7 is formed shallower than the N-type layer 9. As a result, the signal charge read channel 22 can be made deeper than the P-type layer 7, and the signal charge can be read out through the central portion under the vertical CCD.
It is possible to reduce the influence of misalignment of each diffusion layer and processing deviation. Even if the N-type layer 21 is composed of a plurality of diffusion layers having different impurity concentrations and depths, the same effect can be obtained. This can increase the design latitude.
【００１１】図６は本発明を実施した画素部の断面図を
示したものである。本実施例が図１に示す実施例と異な
るところは、アイソレーション部分でＮ型層２１を除く
代わりに新たにＰ型層１０を設けたところである。これ
によっても同様にアイソレーションを確実に行うことが
できる。FIG. 6 is a sectional view of a pixel portion embodying the present invention. The present embodiment is different from the embodiment shown in FIG. 1 in that a P-type layer 10 is newly provided instead of removing the N-type layer 21 in the isolation portion. This also ensures reliable isolation.
【００１２】図７，図８は、図１に示す本発明の一実施
例のＣＣＤ型固体撮像素子の画素部の製造方法を示した
ものである。例えば、Ｎ型シリコン基板１からなる半導
体基板表面に、Ｐ型ウェル層２並びにＮ型層３を、イオ
ン打込み・熱拡散法により、順次、形成する。次にアイ
ソレーション部分だけをフォトレジスト２４で覆い、例
えば、イオン打込みによりＮ型不純物層２３を形成する
（図７（ａ））。次に、フォトレジスト２４を除去し、
熱拡散を行い、Ｎ型不純物層２１とする。次に、絶縁膜
６を介して、例えば、Ｓｉ3Ｎ4膜２５をデポした後、マ
スクを用いてエッチングを行い、ホトダイオードとなる
部分と垂直ＣＣＤとなる部分のＳｉ3Ｎ4膜を除去する。
まず、垂直ＣＣＤとなる部分をフォトレジスト２６で覆
い、イオン打込みによりホトダイオードとなるＮ型層５
１を形成する（図７（ｂ））。同様にして今度はホトダ
イオードとなる部分をフォトレジスト５０で覆い、イオ
ン打込みにより垂直ＣＣＤを構成するＰ型層２６を形成
する（図８（ａ））。その後、フォトレジスト除去，熱
拡散を行った後、同様にしてマスクを用いてイオン打込
みを行い、垂直ＣＣＤのチャンネルとなるＮ型層８を形
成する。さらにＮ型シリコン基板１上に絶縁膜６を介し
て垂直ＣＣＤの転送ゲート１１を形成した後、この転送
ゲート電極１１をマスクにしてイオン打込みによりホト
ダイオードを構成するＰ型層５を形成する（図８
（ｂ））。なお、拡散深さの深い拡散層２，３，２１に
ついては高エネルギイオン打込み法により形成してもよ
い。熱拡散工程が減り、プロセスを簡略化することがで
きる。7 and 8 show a method of manufacturing the pixel portion of the CCD type solid-state image pickup device of the embodiment of the present invention shown in FIG. For example, the P-type well layer 2 and the N-type layer 3 are sequentially formed on the surface of the semiconductor substrate made of the N-type silicon substrate 1 by the ion implantation / thermal diffusion method. Next, only the isolation portion is covered with the photoresist 24, and the N-type impurity layer 23 is formed by, for example, ion implantation (FIG. 7A). Next, the photoresist 24 is removed,
Thermal diffusion is performed to form the N-type impurity layer 21. Next, for example, after depositing the Si 3 N 4 film 25 through the insulating film 6, etching is performed using a mask to remove the Si 3 N 4 film in the portions that will be photodiodes and the vertical CCDs. ..
First, a portion to be a vertical CCD is covered with a photoresist 26, and an N-type layer 5 to be a photodiode by ion implantation is formed.
1 is formed (FIG. 7B). Similarly, this time, the portion to be the photodiode is covered with the photoresist 50, and the P-type layer 26 forming the vertical CCD is formed by ion implantation (FIG. 8A). Then, after removing the photoresist and performing thermal diffusion, ion implantation is similarly performed using a mask to form an N-type layer 8 that serves as a channel of the vertical CCD. Further, after the transfer gate 11 of the vertical CCD is formed on the N-type silicon substrate 1 via the insulating film 6, the transfer gate electrode 11 is used as a mask to form the P-type layer 5 constituting the photodiode by ion implantation (FIG. 8
(B)). The diffusion layers 2, 3, 21 having a large diffusion depth may be formed by the high energy ion implantation method. The heat diffusion step can be reduced and the process can be simplified.
【００１３】図２に示した従来の画素部にも、図１，図
６に示す本発明の実施例を全く同様に適用することがで
きる。The embodiment of the present invention shown in FIGS. 1 and 6 can be applied to the conventional pixel portion shown in FIG. 2 in exactly the same manner.
【００１４】なお、上述の実施例では、ＣＣＤ型撮像素
子を用いて説明を行ったが、本発明は、ＭＯＳ型撮像素
子や、また一次元や二次元の固体撮像素子にも適用可能
である。また、実施例では、接合型ホトダイオードを用
いて説明を行ったが、本発明は、ＭＯＳダイオードにも
適用できる。In the above embodiments, the CCD type image pickup device was used for explanation, but the present invention can be applied to a MOS type image pickup device and also a one-dimensional or two-dimensional solid-state image pickup device. .. Further, in the embodiments, the description has been given by using the junction type photodiode, but the present invention can be applied to the MOS diode.
【００１５】[0015]
【発明の効果】本発明によれば、従来スミア抑圧のため
設けられたＮ型層を残したまま、より浅くて不純物濃度
の高いＮ型層を追加することにより、ホトダイオードと
なるＮ型層がＮ型基板表面に達しないようにＰ型層で完
全に覆っても信号電荷の読み出しを行うことができるの
で、スミアや読み出し特性を維持したままでホトダイオ
ード部の暗電流を低減することができる。According to the present invention, an N-type layer which becomes a photodiode can be formed by adding a shallower N-type layer having a high impurity concentration while leaving the N-type layer conventionally provided for suppressing smear. Since the signal charge can be read out even when the signal charge is completely covered with the P-type layer so as not to reach the surface of the N-type substrate, it is possible to reduce the dark current in the photodiode portion while maintaining the smear and the read characteristics.
【図１】本発明の第一の実施例の画素部の断面図。FIG. 1 is a sectional view of a pixel portion according to a first embodiment of the present invention.
【図２】従来例の画素部の断面図。FIG. 2 is a sectional view of a pixel portion of a conventional example.
【図３】ＣＣＤ型撮像素子の回路の説明図。FIG. 3 is an explanatory diagram of a circuit of a CCD type image pickup device.
【図４】本発明の第二の実施例の画素部の断面図。FIG. 4 is a sectional view of a pixel portion according to a second embodiment of the present invention.
【図５】本発明の第三の実施例の画素部の断面図。FIG. 5 is a sectional view of a pixel portion of a third embodiment of the present invention.
【図６】本発明の第四の実施例の画素部の断面図。FIG. 6 is a sectional view of a pixel portion according to a fourth embodiment of the present invention.
【図７】本発明の第一の実施例の画素部の製造方法の説
明図。FIG. 7 is an explanatory diagram of the manufacturing method of the pixel portion according to the first embodiment of the present invention.
【図８】本発明の第一の実施例の画素部の製造方法の説
明図。FIG. 8 is an explanatory diagram of the manufacturing method of the pixel portion according to the first embodiment of the present invention.
９，５１…ホトダイオードとなるＮ型層、１３，８…垂
直ＣＣＤとなるＮ型層、３，４，２１，３０…Ｎ型層。9, 51 ... N-type layers to be photodiodes, 13, 8 ... N-type layers to be vertical CCDs, 3, 4, 21, 30 ... N-type layers.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 尾崎 俊文 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 田中 治彦 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toshifumi Ozaki, Toshifumi Ozaki, 1-280, Higashi Koikekubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi Ltd. (72) Haruhiko Tanaka, 1-280, Higashi Koikekubo, Kokubunji, Tokyo Hitachi, Ltd. Central research institute
Claims (6)
逆導電形のウェル層内に形成した光電変換素子及びスイ
ッチ素子からなる画素のアレーと、前記画素のアレーを
走査する水平及び垂直走査素子と、前記垂直走査素子を
覆うように形成された前記ウェル層と同導電型の第一拡
散層をもった固体撮像素子において、前記画素のアレー
及び垂直走査素子領域の前記ウェル層上に前記ウェル層
と逆導電型の複数の不純物層群を設けたことを特徴とす
る固体撮像素子。1. An array of pixels formed of a photoelectric conversion element and a switch element formed in a well layer of a conductivity type opposite to that of the semiconductor substrate provided on the semiconductor substrate, and horizontal and vertical scanning for scanning the array of the pixels. A solid-state imaging device having an element and a first diffusion layer of the same conductivity type as the well layer formed so as to cover the vertical scanning element, the array of the pixels and the well layer in the vertical scanning element region A solid-state imaging device comprising a plurality of impurity layer groups having a conductivity type opposite to that of a well layer.
導体基体と同導電型の第二拡散層をもち、前記垂直走査
素子は半導体基体と同導電型の第三拡散層をもち、前記
第二拡散層と前記第三拡散層間の二領域の距離が少なく
とも一部で等しい固体撮像素子。2. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element has a second diffusion layer of the same conductivity type as the semiconductor substrate, and the vertical scanning element has a third diffusion layer of the same conductivity type as the semiconductor substrate. A solid-state imaging device in which a distance between two regions between the second diffusion layer and the third diffusion layer is at least partially equal.
記半導体基体と同導電型の第二拡散層をもち、前記垂直
走査素子は半導体基体と同導電型の第三拡散層をもち、
前記第二拡散層と第三拡散層間の二つの領域において、
前記ウェル層と同導電型層の不純物濃度が少なくとも一
部で異なる固体撮像素子。3. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element has a second diffusion layer of the same conductivity type as the semiconductor substrate, and the vertical scanning element has a third diffusion layer of the same conductivity type as the semiconductor substrate.
In the two regions between the second diffusion layer and the third diffusion layer,
A solid-state imaging device, wherein the well layer and the same conductivity type layer have different impurity concentrations at least in part.
導体基体と同導電型の第二拡散層をもち、前記垂直走査
素子は半導体基体と同導電型の第三拡散層をもち、前記
複数の不純物層群の少なくとも一つの不純物層は、前記
第二拡散層と第三拡散層間の二領域の少なくとも１部に
導入されていない固体撮像素子。4. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element has a second diffusion layer of the same conductivity type as the semiconductor substrate, and the vertical scanning element has a third diffusion layer of the same conductivity type as the semiconductor substrate. In the solid-state imaging device, at least one impurity layer of the impurity layer group is not introduced into at least a part of the two regions between the second diffusion layer and the third diffusion layer.
導体基体と同導電型の第二拡散層をもち、この第二拡散
層の深さは前記第一拡散層の深さより深い固体撮像素
子。5. The solid-state imaging device according to claim 1, wherein the photoelectric conversion element has a second diffusion layer of the same conductivity type as the semiconductor substrate, and the depth of the second diffusion layer is deeper than the depth of the first diffusion layer. ..
導体基体と同導電型の第二拡散層をもち、前記垂直走査
素子は半導体基体と同導電型の第三拡散層をもち、前記
第二拡散層と前記第三拡散層並びに前記第一拡散層を同
一マスク層により自己整合的に形成する固体撮像素子。6. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element has a second diffusion layer of the same conductivity type as the semiconductor substrate, and the vertical scanning element has a third diffusion layer of the same conductivity type as the semiconductor substrate. A solid-state imaging device, comprising: a second diffusion layer, the third diffusion layer, and the first diffusion layer formed in the same mask layer in a self-aligned manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3303065A JPH05145056A (en) | 1991-11-19 | 1991-11-19 | Solid state image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3303065A JPH05145056A (en) | 1991-11-19 | 1991-11-19 | Solid state image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05145056A true JPH05145056A (en) | 1993-06-11 |
Family
ID=17916484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3303065A Pending JPH05145056A (en) | 1991-11-19 | 1991-11-19 | Solid state image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05145056A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299453A (en) * | 1999-02-09 | 2000-10-24 | Sony Corp | Solid-state image pickup device and its manufacture |
| EP1143522A2 (en) * | 2000-04-06 | 2001-10-10 | Nec Corporation | Charge coupled device and method for fabricating same |
| JP2010028143A (en) * | 1999-02-09 | 2010-02-04 | Sony Corp | Solid-state image sensing device and method for producing the same |
-
1991
- 1991-11-19 JP JP3303065A patent/JPH05145056A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000299453A (en) * | 1999-02-09 | 2000-10-24 | Sony Corp | Solid-state image pickup device and its manufacture |
| JP2010028143A (en) * | 1999-02-09 | 2010-02-04 | Sony Corp | Solid-state image sensing device and method for producing the same |
| EP1143522A2 (en) * | 2000-04-06 | 2001-10-10 | Nec Corporation | Charge coupled device and method for fabricating same |
| EP1143522A3 (en) * | 2000-04-06 | 2008-03-26 | Nec Corporation | Charge coupled device and method for fabricating same |
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