JPH11274461A - Solid image pickup device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increasing of a reading voltage applied to an insulating gate transistor and to prevent the incomplete reading of signal charges at a sensor section when a MOS type solid image pickup device is constructed in such a manner that a highly concentrated impurity layer is formed on the surface of the sensor section. SOLUTION: A plurality of unit pixel sections are arrayed on a semiconductor substrate, each unit pixel section has a sensor section S in which a photoelectric conversion element is formed, and an insulating gate transistor for reading charges. In the section S, the photoelectric conversion element is formed by comprising a first conductive type semiconductor region 1, a second conductive type first semiconductor region 2 formed on the region 1, and a first conductive type highly concentrated impurity layer 6 formed on the region 2. In the insulating gate transistor, an insulating gate section is formed between the section S and a second conductive type second semiconductor region 3 that is formed a predetermined distance apart from the section S. The layer 6 in the section S is formed on the surface of the region 2 so as to be limited to a surface portion excluding the surface portion in which the region 2 is adjacent to the insulating gate section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a MOS type solid-state image pickup device having a MOS transistor (MOS is a generic term for a conductive layer / insulating film / semiconductor structure). The present invention relates to an apparatus and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 4 shows a so-called FD (Floating Diffu).
FIG. 1 is a configuration diagram of a main part of a MOS type solid-state imaging device having a sion type configuration. In this solid-state imaging device, a plurality of unit pixels 101 (only one unit pixel is shown in FIG. 4) are respectively arranged in a plurality of rows and columns, that is, in the horizontal and vertical directions. The signal charge obtained by the photodiode 102 as a photoelectric conversion element of the unit and the sensor unit is read by the FD read MOS transistor 103, and the signal charge is converted into a signal voltage or a signal current by the FD amplification MOS transistor 104 in each unit pixel. It is configured to amplify.

In the configuration shown in FIG. 4, each unit pixel 101
FIG. 5 shows a configuration diagram of a main part of the solid-state imaging device, for example, a so-called column amplifier type solid-state imaging device in which an amplifier is arranged for each common column. it can.

Also in this column amplifier type solid-state imaging device, a plurality of unit pixels 201 (only one unit pixel is shown in FIG. 5) are arranged in rows and columns, that is, in the horizontal and vertical directions. The unit pixel 201 has a photodiode 202 as a photoelectric conversion element in its sensor unit.
A MOS transistor 203 for reading out the signal charges stored in the memory cell 02 and a selecting MOS transistor 204 for reading out the signal charges to the vertical signal line 208 are formed, and a column amplifier 205 is arranged for each vertical signal line 208.

In each of the unit pixels 101 and 201 of the MOS type solid-state imaging device, the photoelectric conversion element of the sensor section, that is, the photodiode, and the MOS transistor for reading out charges from the sensor are one of the semiconductors constituting the photodiode. Region, for example, the cathode region
It has a composite structure that also serves as the source region of the S transistor.

In each unit pixel of these MOS type solid-state imaging devices, a photoelectric conversion element of a sensor section, that is, a photodiode, and an M for reading charges therefrom are provided.
The OS transistor has a composite structure in which one semiconductor region, for example, a cathode region of a photodiode also functions as a source region of a MOS transistor.

FIG. 8 is a schematic cross-sectional view of the sensor section S and a MOS transistor forming section for reading signal charges from the sensor section S. In this case, for example, a p-type semiconductor region 1 is provided, and an n-type first semiconductor region 2 is formed in a formation portion of the sensor portion S, and a required interval from the first semiconductor region 2, that is, a MOS transistor Similarly, an n-type second semiconductor region 2 is formed while maintaining an interval corresponding to the channel length. Then, a gate electrode 5 is formed between the first and second semiconductor regions 2 and 3 via a gate insulating film 4. Thus, a photodiode is formed in the sensor unit S, the first semiconductor region 2 is used as a source region,
A MOS transistor (MOS) having the second semiconductor region 3 as a drain region is configured.

In this case, if a reverse bias is applied to the photodiode simply as a pn junction photodiode, the Si—SiO ₂ interface (the interface between the semiconductor and the insulating film on the surface) is depleted. A dark current is generated from the generation / recombination center existing at the interface, and this causes so-called fixed pattern noise in an image captured by the imaging apparatus. Therefore, as shown in FIG. 8, a so-called HAD (Hole Accumulum) for forming a p-type high impurity concentration layer 6 constituting a conductivity type different from that of the first semiconductor region 2, in this example, a hole accumulation layer in this example.
ated Diode) type structure, and the high impurity concentration layer 6 at the interface is
The dark current is reduced by fixing the voltage to V so that the interface of the photodiode is not depleted.

By forming a high impurity concentration layer 7 of the same conductivity type on the surface of the second semiconductor region 3, the parasitic resistance can be reduced.

Although not shown, a light-shielding film having a light receiving window formed on the sensor section S is formed on the entire surface of the semiconductor substrate, and the sensor section S is irradiated with light through the light receiving window.

[0011]

However, as described above, in various MOS type solid-state imaging devices, a structure in which a high impurity concentration layer is formed on the surface of a sensor portion (that is, a so-called HAD structure when signal charges are electrons). In the case where the signal charge is read from the sensor unit by the MOS transistor, the voltage applied to the MOS transistor for reading is increased, and the signal charge is not completely read.

According to the present invention, the signal charges in the sensor section can be almost completely read by a low read voltage.

[0013]

In a solid-state imaging device according to the present invention, a plurality of unit pixels each having a sensor section having a photoelectric conversion element and a MOS transistor (insulated gate transistor) for reading charges are arranged on a semiconductor substrate. It is a formed configuration. The sensor unit includes a first conductivity type semiconductor region, a second conductivity type first semiconductor region formed thereon, and a first conductivity type high impurity concentration layer formed on a surface of the semiconductor region. The insulated gate transistor has an insulated gate portion formed between the sensor portion and a second semiconductor region of the second conductivity type formed at a required distance. Become. Then, the high impurity concentration layer in the sensor portion is formed on the surface of the first semiconductor region of the second conductivity type in a limited manner except for a portion adjacent to the insulated gate portion.

Further, according to the method of manufacturing a solid-state imaging device according to the present invention, a step of forming a gate insulating film in a semiconductor region of a first conductivity type; a step of forming a conductive layer on the insulating film; A step of forming a resist layer on the gate electrode forming portion of the conductive layer, a step of pattern-etching the conductive layer using the resist layer as a mask to form a gate electrode, and a step of forming a resist layer on the first conductive type semiconductor region. Leave it,
Using the resist and the gate electrode as a mask, introducing a second conductivity type impurity on both sides of the gate electrode to form first and second semiconductor regions of the second conductivity type; Forming a sidewall with an insulating layer on at least a side surface adjacent to the first semiconductor region; and using the sidewall and the gate electrode as a mask, forming a high impurity concentration on the surface of the first semiconductor region by separating from the gate electrode. Forming a layer in a limited manner.

The solid-state imaging device according to the present invention has a configuration in which a high impurity concentration layer is eliminated in a portion adjacent to a gate portion of a MOS transistor in a sensor portion, that is, in a portion adjacent to a channel of a MOS transistor. The potential barrier against signal charges generated by the presence of the high impurity concentration layer can be reduced in the read section of the MOS transistor, and the signal charges can be read completely from the sensor section by applying a low voltage. Things.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state imaging device having a MOS transistor according to the present invention has a configuration in which a plurality of unit pixels are arranged in a plurality of rows and columns, that is, in a horizontal and a vertical direction, respectively. And a MOS type solid-state imaging device having various configurations including a sensor unit having a photoelectric conversion element and a MOS transistor for reading out a signal charge according to the amount of incident light generated by the sensor unit.

One embodiment of the MOS solid-state imaging device according to the present invention can be the FD MOS solid-state imaging device shown in FIG. As described above, in the solid-state imaging device, a plurality of rows and columns, that is, a plurality of unit pixels 101 are arranged in the horizontal and vertical directions, respectively, and each unit pixel 101 is a sensor unit that performs photoelectric conversion.
The signal charge obtained by this sensor unit is
03, and the signal charge is amplified to a signal voltage or a signal current by the MOS transistor 104 in each unit pixel, so-called an amplification type imaging device.

The unit pixel 101 of the solid-state imaging device has a photodiode 102 as a photoelectric conversion element in a sensor portion thereof, and an FD read MOS transistor 103 for reading out signal charges accumulated in the photodiode 102; MOS transistor 104 and FD
Reset MOS transistor 105 and vertical selection MOS
And a transistor 106.

The gate electrode of the FD read MOS transistor 103 is connected to the vertical read line 107,
The gate electrode of the reset MOS transistor 105 is connected to the vertical reset line 108, the gate electrode of the vertical select MOS transistor 106 is connected to the vertical select line,
The sources of the vertical selection MOS transistors 106 are connected to the vertical signal lines 110, respectively.

Reference numeral 111 denotes a horizontal signal line. A horizontal selection MOS transistor 112 is connected between the horizontal signal line 111 and the vertical signal line 110.
A horizontal scanning pulse φ _Hm from the horizontal scanning circuit 113 is applied to the twelve gate electrodes. Then, vertical scanning pulses φv _Sn , φ from a vertical scanning circuit 114 for selecting a row
The signal charges accumulated in the photodiodes 102 in each unit pixel 101 for each row are represented by v _tn and φv _Rn ,
Read by the read MOS transistor 103 and amplified by the amplification MOS transistor 104,
The selection is made by the vertical selection MOS transistor 106. Each pixel signal is output to a horizontal line 111 through a horizontal selection MOS transistor 112 controlled by a horizontal scanning pulse φ _Hm from a horizontal scanning circuit 113 for selecting a column. On the other hand, each unit pixel 101 is reset by the reset MOS transistor 105.

In another embodiment of the MOS transistor type solid state imaging device according to the present invention, a so-called column amplifier type MOS type solid state imaging device shown in FIG. 5 can be constructed. Also in this solid-state imaging device, an amplifier is arranged for each common column as described above. Also in this solid-state imaging device, a plurality of unit pixels 20 are respectively provided in a plurality of rows and columns, that is, in the horizontal and vertical directions.
1, each unit pixel 201 has a photodiode 202 as a photoelectric conversion element in its sensor unit,
A horizontal readout MO having a selection MOS transistor 203 for reading out signal charges accumulated in the photodiode 202 and reading out the signal charges to a vertical signal line 208 is provided.
It has an S transistor 204.

The MOS transistor 203 has a so-called switch function of charge reading which is turned on by application of a vertical scanning pulse from the vertical scanning circuit 214 to its gate electrode, and the MOS transistor 204 has a horizontal scanning circuit The signal charge is read out to the vertical signal line 208 by applying the horizontal scanning pulse from 213. Then, the signal charge read out to the vertical signal line 208 is amplified by the amplifier 205, and an output based on the signal charge from the unit pixel on the selected column is output to the horizontal signal line 207 by the horizontal selection MOS transistor 206. It is done as follows.

However, the solid-state imaging device according to the present invention is not limited to the configuration of the solid-state imaging device shown in FIGS. For example, although the solid-state imaging device shown in FIGS. 4 and 5 has a basic configuration, the present invention can be applied to, for example, various MOS-type solid-state imaging devices designed to reduce fixed pattern noise.

That is, the solid-state imaging device according to the present invention comprises:
A plurality of unit pixels are arranged on rows and columns, respectively, and a photoelectric conversion element of the sensor unit, that is, a photodiode, and a MOS transistor for reading out electric charges from the photoelectric conversion element are one of semiconductor regions such as a cathode region, for example, a cathode region. Solid-state image pickup device having a composite structure in which a high impurity concentration layer formed on the surface of the sensor section is formed by MO.
It is formed in a limited manner except for the side adjacent to the S transistor.

FIG. 1 is a schematic sectional view of a sensor section S and a MOS transistor (MOS) forming section for reading signal charges from the sensor section S in a solid-state imaging device according to the present invention. A semiconductor substrate 21 made of, for example, a Si semiconductor substrate, which constitutes an intended solid-state imaging device, is formed of a part thereof, or has a low impurity concentration first conductivity type formed on the semiconductor substrate 21, ie, a p-type semiconductor region in this example. 1
In addition, the first semiconductor region 2 of the second conductivity type, in this example, the n-type
To form Further, an n-type second semiconductor region 3 of the same conductivity type as the first semiconductor region 2 is formed while maintaining a predetermined interval from the first semiconductor region 2, that is, an interval corresponding to the channel length of the MOS transistor.

On the surface of the semiconductor substrate 21, at least on the surface between the first and second semiconductor regions 2 and 3, a gate insulating film 4 of, for example, SiO ₂ is formed, and a gate electrode 5 is formed thereon to form a MOS. It constitutes the gate of the transistor. Except for a portion of the surface of the first semiconductor region 2 adjacent to the above-described gate portion, the entire surface is of the first conductivity type, in this example, p-type, and has charges (major carriers, holes in this example).
A high impurity concentration layer 6 serving as an accumulation layer is formed, and a high impurity concentration layer 7 of the same conductivity type as the second semiconductor region 3, in this example, an n-type in this example, is formed on the surface of the second semiconductor region 3.

Thus, in the sensor section S,
Photodiode of p ⁺⁺ / n / p ^- structure, ie FIG.
And photodiodes 102 and 20 in FIG.
A MOS transistor (MOS) having the first semiconductor region 2 as a source region and the second semiconductor region 3 as a drain region is formed.

Next, an example of a method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. First,
As shown in FIG. 2A, a semiconductor substrate 21 made of, for example, a Si semiconductor substrate constituting a target solid-state imaging device is prepared, and a portion of the semiconductor substrate 21 where charge transfer should be avoided, for example, between formation units of each unit pixel, a sensor unit A thick isolation insulating layer 22 is formed by a well-known local thermal oxidation, so-called LOCOS (Local Oxidation of Silicon) method, on the periphery except for the charge readout side, and between circuit elements such as MOS transistors. In addition, a high-concentration p-type channel stop region 23 is formed under the portion where the isolation insulating layer 22 is formed by ion implantation. Then, the mask layer in the above-described LOCOS and ion implantation is removed, and the gate insulating film 4 made of SiO ₂ is formed on the surface of the semiconductor substrate 21, that is, on the formation portion of the sensor portion and the MOS transistor by surface thermal oxidation.
To form

Next, as shown in FIG. 2B, a conductive layer 24 constituting the entire gate electrode, for example, a semiconductor layer made of polycrystalline silicon having a low resistivity is formed by CVD (Chemical Vapor Deposition).
(r Deposition) method or the like to a thickness of, for example, about 0.2 μm. Then, a resist layer 25 is formed on a portion of the conductive layer 24 where a gate electrode is to be formed. The resist layer 25 is formed by applying a photoresist, exposing a pattern,
It can be formed by a development process.

As shown in FIG. 3A, the resist layer 25 is
The gate electrode 5 is formed by pattern-etching the conductive layer 24 as an etching mask. In forming the gate electrode 5, not only a wiring portion related thereto but also other electrodes and a wiring portion can be formed simultaneously. Next, using the resist layer 25, the gate electrode 5, and the insulating separation layer 22 as masks, the second conductivity type, in this example, n-type impurities such as A
s ⁺ is ion-implanted with a high energy of several hundred keV to form a first semiconductor region 2 having a depth sufficient to efficiently perform photoelectric conversion in a finally formed photodiode, and at the same time, to form a second semiconductor region 3. Form.
Since the ion implantation is performed with relatively high energy as described above, when the ion implantation is performed using only the gate electrode 5 made of a polycrystalline semiconductor layer or the like as a mask, the ion implantation is performed through the gate electrode 5. Therefore, the resist layer 25 used as an etching mask for the gate electrode 5 is left, and this is used as a mask for ion implantation. By doing so, the first and second semiconductor regions 2 and 3 can be reliably formed on both sides of the gate electrode 5 with certainty.

Next, as shown in FIG.
5 is removed, and sidewalls 26 are formed on the side surfaces of the gate electrode 5 adjacent to the first semiconductor region 2, actually, on both side surfaces of the gate electrode 5 as shown in FIG. The sidewall 26 is formed by a known method. For example, the SiO ₂ layer can be formed to a required thickness including the side surface of the gate electrode 5 by a CVD method and then etched back. After that, one of the first semiconductor region 2 and the second semiconductor region 2 is covered with a resist layer 27. In the figure, the first semiconductor region 2
This is the case where the top is covered with the resist layer 27. Then, using the resist layer 27, the sidewalls 26, and the isolation insulating layer 22 as a mask, a high impurity concentration layer 7 of the same conductivity type as the second semiconductor region 3 is formed on the surface of the second semiconductor region 3 by ion implantation.

Thereafter, as shown in FIG. 3C, the resist layer 27 is removed, and the other semiconductor region, ie, the second semiconductor region in the illustrated example, is removed.
The semiconductor region 3 is covered with a resist layer 28, and a high impurity concentration layer 6 of the same conductivity type as that of the first semiconductor region 2 is ion-implanted into the surface of the first semiconductor region 2 using the resist layer 27, the sidewall 26, and the isolation insulating layer 22 as a mask. Formed by

After that, the resist layer 28 is removed. Then, heat treatment is performed to activate the impurities in each ion implantation region.

Thus, in the sensor section S shown in FIG. 1, the photodiode having the p ⁺⁺ / n / p ^- structure
That is, the photodiode 10 shown in FIGS.
2 and 202, and a MOS transistor (MOS) having the first semiconductor region 2 as a source region and the second semiconductor region 3 as a drain region is formed.

As described above, in the structure of the present invention,
The photodiode of the photoelectric conversion element of the sensor unit S is p
⁺⁺ / n / p ⁻ structure, the dark current is reduced, and despite the high impurity concentration layer 6 formed on the surface as described above, the portion adjacent to the MOS gate portion is formed. Is that the structure in which the high impurity concentration layer 6 is not formed, that is, the notch 29 is formed,
Reading of signal charges by the transistor can be completely performed at a low voltage. The width d of the notch 29 is
For example, the thickness is selected from 0.05 μm to 0.2 μm.

Next, it will be considered that the signal charge can be completely read out by the MOS transistor at a low voltage in the structure of the present invention. Now, in the structure shown in FIG. 1, the potential in the depth direction at the position shown by the chain line a in FIG.
The first high impurity concentration layer 6 on the surface and the semiconductor region 1
Signal charges e are accumulated in the semiconductor region 2. However, as shown by a curve b in FIG. 6, the potential distribution in the cutout portion 29 of the high impurity concentration layer 6 indicated by the dashed line b in FIG. The indicated signal charge flow can occur. Therefore, a required voltage is applied to the gate electrode 5 to form a potential distribution in the gate portion, that is, the channel portion of the chain line c in FIG. 1 at a portion relatively shallow from the surface as shown by the curve c in FIG. The signal charge can be formed by a relatively low applied voltage, whereby the flow of the signal charge indicated by the arrow g, that is, the reading can be performed, and the signal charge can be almost completely read.

On the other hand, when the structure in which the high impurity concentration layer is formed on the entire surface of the first semiconductor region 2 without forming the above-described notched portion 29, the potential distribution is shown in FIG. As shown in FIG. 6, since the curve b in FIG. 6 does not exist, it is necessary to apply a large applied voltage to the gate portion of the MOS transistor to form a deep potential as shown in the curve c in FIG. As apparent from FIG. 7, a phenomenon occurs in which the signal charges remain without being completely read.

Further, the manufacturing method of the present invention for obtaining the device of the present invention has the above-mentioned p ⁺⁺ / n / p ⁻ structure by a simple method of forming the side wall 26, and has a portion adjacent to the gate portion. The p ⁺⁺ layer, that is, the lacking portion 29 of the high impurity concentration layer 6 is
It can be easily formed.

In FIGS. 1 to 6, the sensor section S and the MOS transistor 10 in one unit pixel are shown.
Although only one MOS transistor part constituting 2 or 202 is shown, it is needless to say that a plurality of MOS transistors 101 or 202 are formed in parallel, and the sensor unit S and the MOS transistor Simultaneously with the formation, other semiconductor elements, for example, other MOS transistors in the same unit pixel, and semiconductor elements such as MOS transistors in other unit pixels can be simultaneously formed in parallel. .

Further, in the above-described example, each MOS transistor is constituted by a SiO ₂ gate insulating film. However, this gate insulating film is not limited to an oxide film, but may have various insulated gate transistor structures. can do.

In general, the signal charge in the solid-state imaging device is an electron, but when the signal charge is a hole, the first conductivity type is n-type and the second conductivity type is
The present invention is not limited to the above-described example, and can be variously modified, for example, the conductivity type can be selected to be p-type.

[0042]

As described above, according to the solid-state imaging device of the present invention, the photodiode of the photoelectric conversion element of the sensor section is formed on the surface thereof with a charge storage layer formed by the high impurity concentration layer 6, that is, for example, the signal charges are formed of electrons. In some cases, the formation of a hole accumulation layer enhances the accumulation of signal charges and prevents dark current. The signal charges can be read with a low read voltage, and the signal charges can be read almost completely. Therefore, noise of the fixed pattern can be improved by taking measures against dark current in the MOS solid-state imaging device, and the image quality can be improved in combination with efficient reading.

Further, the feature of reducing the power consumption in the MOS type solid-state imaging device can be further promoted by reducing the read driving voltage.

Further, according to the manufacturing method of the present invention, the solid-state imaging device having the above-described structure of the present invention can be easily performed by adding a sidewall process.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a main part of an example of a solid-state imaging device according to the present invention.

FIGS. 2A and 2B are process diagrams of an example of the production method of the present invention.

3A to 3C are process diagrams of an example of the production method of the present invention.

FIG. 4 is a configuration diagram of an example of a solid-state imaging device to which the present invention is applied.

FIG. 5 is a configuration diagram of another example of the solid-state imaging device to which the present invention is applied.

FIG. 6 is a potential distribution diagram in the solid-state imaging device of the present invention.

FIG. 7 is a potential distribution diagram in a solid-state imaging device compared with the present invention.

FIG. 8 is a schematic sectional view of a main part of a conventional solid-state imaging device.

[Explanation of symbols]

S: sensor unit, MOS: MOS transistor, 1: semiconductor region, 2: first semiconductor region, 3
... 2nd semiconductor region, 4 ... gate insulating film, 5 ...
・ Gate electrode, 6 ・ ・ ・ High impurity concentration layer, 7 ・ ・ ・ High impurity concentration layer, 21 ・ ・ ・ Semiconductor substrate, 22 ・ ・ ・ Insulation separation layer, 23 ・ ・ ・ Channel stop region, 24 ・ ・ ・ Conduction Layer, 25: resist layer, 26: sidewall, 27, 28: resist layer, 29: missing part,
101, 201 ... unit pixel, 102, 202 ...
Photodiode, 103, 203 ... readout MO
S transistor

Claims (3)

[Claims] 1. A semiconductor substrate, comprising: a plurality of unit pixels having a sensor unit on which a photoelectric conversion element is formed and an insulated gate transistor for reading out electric charges from the sensor unit, the sensor unit having a first conductivity type A photoelectric conversion element comprising: a semiconductor region of the type described above; a first semiconductor region of the second conductivity type formed thereon; and a high impurity concentration layer of the first conductivity type formed on the surface of the semiconductor region. The insulated gate transistor is formed of a first conductive type of the first type.
An insulated gate portion is formed between the semiconductor region and a second conductivity type second semiconductor region formed at a predetermined distance, and the high impurity concentration layer of the sensor portion is formed of the second conductivity type. A solid-state imaging device, which is formed only on a portion of the surface of the first semiconductor region other than a portion adjacent to the insulated gate portion. 2. A step of forming a gate insulating film in a semiconductor region of a first conductivity type; a step of forming a conductive layer on the insulating film; and forming a resist layer in a gate electrode forming portion of the conductive layer. Forming a gate electrode by pattern-etching the conductive layer using the resist layer as a mask; and forming the gate and the resist in the semiconductor region of the first conductivity type while leaving the resist layer. A step of introducing a second conductivity type impurity to form first and second semiconductor regions of a second conductivity type on both sides of the gate electrode using the electrode as a mask, and forming at least the first and second semiconductor regions of the gate electrode; Forming a sidewall by an insulating layer on a side surface adjacent to one semiconductor region; and using the sidewall and the gate electrode as a mask,
Forming a high impurity concentration layer on the surface of the first semiconductor region so as to be separated from the gate electrode. 3. After or before the step of forming the high impurity concentration layer, using the side wall and the gate electrode as a mask, a surface of the second semiconductor region is separated from the gate electrode by a second step. 3. The method according to claim 2, further comprising the step of forming a conductive type high impurity concentration region.