JP2004039832A - Photoelectric converter and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric converter having an element isolating structure for isolating photodiodes from each other which hardly causes the deterioration of the sensitivity of a photodiode and does not have an adverse influence on peripheral semiconductor elements, and to provide its manufacturing method. <P>SOLUTION: The element isolating structure for isolating the photodiodes from each other, such as an STI structure 7b, is formed by a method not using the thermal oxidation of a substrate, and a second conductive type channel stopper layer 6 is formed so as to have contact with and surround the element isolating structure 7b in the first conductive type semiconductor substrate 1. Then, a first conductive type semiconductor layer 18 is formed as a signal charge storage region of the photodiode, and the layer 18 is surrounded by second conductive type wells 8, 10 and 11 so as to be isorated from other regions of the substrate 1. The channel stopper layer 6 is terminated at a specified position around a light receiving region between the receiving region and a semiconductor circuit element 41. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a photoelectric conversion device in which a photodiode is formed in each light receiving region, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the rapid spread of digital cameras and the Internet, opportunities for converting optical image information into electric signals, capturing, processing, and using digital data have been increasing. For this reason, there is an increasing demand for compact, low-cost, high-definition, high-sensitivity, wide dynamic range, and other high-performance photoelectric conversion devices such as solid-state imaging devices. It is expected that miniaturization and higher integration of solid-state imaging devices will be advanced.
[0003]
9A and 9B are an example of a schematic cross-sectional view (a) and an example of a schematic plan view (b) of a main part centering on a photodiode (PD: Photo @ Diode) of a conventional image sensor or the like. On the substrate surface, an element isolation structure 107 having a LOCOS (Local Oxidation of Silicon) structure that electrically insulates the light receiving region 114 of each photodiode is formed in order to isolate elements between the photodiodes.
[0004]
In the example of FIG. 9, an N-type silicon substrate 101 is used as the substrate, and an N-type silicon layer 118 formed on the surface of the substrate and a P-type silicon layer 118 thereunder are formed.⁻A photodiode is formed by a PN junction at the interface with the shaped silicon layer 112. Hereinafter, a portion surrounded by the element isolation structure 107 is referred to as a light receiving region 114, and a portion in which a PN junction is formed is referred to as a sensor opening 115, so that the two are distinguished from each other.
[0005]
When the light incident on the sensor opening 115 reaches the PN junction, it is converted into holes and electrons there, and signal charges (electrons) corresponding to the amount of incident light are converted into N-type silicon layers 118 and N-type layers. P⁻It is accumulated in the shaped silicon layer 112. In addition, P of the outermost surface⁺The type silicon layer 119 is for preventing charge leakage from the surface.
[0006]
The above-described signal charge accumulation region including the N-type silicon layer 118 and the like includes a P-type surface well 111 formed below and around the element isolation structure 107, a P-type deep well 108 formed at a deep position in the substrate, A P-type plug (Plug) well 110 formed vertically below the element isolation structure 107 so as to electrically connect the P-type surface well 111 and the P-type deep well 108 to form side and bottom surfaces. Surrounded by As a result, the signal charge storage region is electrically separated from the peripheral elements even in the substrate, and the signal charge does not leak.
[0007]
Next, the points of a method for manufacturing the photodiode of FIG. 9 will be described.
[0008]
First, an element isolation structure 107 having a LOCOS structure is formed around the light receiving region 114 of the N-type silicon substrate 101 by thermal oxidation of the substrate 101.
[0009]
Next, B⁺Thermal diffusion / annealing treatment by ion implantation and heating of the P type deep well 108 at a deep position of the substrate, a P type plug well 110 below the element isolation structure 107, and a P type A front side well 111 is formed. The P-type surface-side well 111 is formed so as to cover the edge of the element isolation structure 107 having a LOCOS structure with a width of about 0.1 μm (protrude to the light receiving region 114 side) for a reason to be described later. At this time, the N-type layer located below the N-type silicon layer 118 becomes P-type by thermal diffusion from the surrounding P-type region.⁻P, surrounded by P-type wells⁻A patterned silicon layer 112 is formed.
[0010]
Next, As is placed in the sensor opening 115.⁺Is performed, and an N-type silicon layer 118 is formed. This gives P⁻A PN junction (photodiode) is formed at the interface between the shaped silicon layer 112 and the N-type silicon layer 118. Finally, BF is added to the sensor opening 115.₂ ⁺Ion implantation and heat annealing treatment to obtain P on the outermost surface.⁺A mold silicon layer 119 is formed.
[0011]
[Procedure leading to the invention]
The problem of the photodiode shown in FIG. 9 from the standpoint of miniaturization and high integration is that the P-type surface formed with a width of about 0.1 μm from the end of the LOCOS element isolation structure 107 to the light receiving region 114 side. The protruding portion 116 of the well 111 is present (FIG. 9B).
[0012]
When the element isolation structure 107 is formed by thermal oxidation of the substrate, a bird's beak forms a boundary region 120 with large distortion around the periphery. In such a boundary region 120, charge leakage easily occurs due to crystal lattice defects or interface states. In order to prevent the leakage of the charges, in the photodiode of FIG. 9, the P-type surface side well 111 is formed so as to protrude toward the light receiving region 114 so as to surround the boundary region 120, and the boundary region 120 is formed in the signal charge storage region. 118.
[0013]
With such a protruding portion 116, the sensor opening 115 is smaller than the light receiving region 114 by that amount, so that the sensor aperture ratio, which is the area ratio of the sensor opening 115 in the unit pixel, is reduced, and the photodiode This causes a drop in sensitivity. The reduction in the sensor aperture ratio due to the protruding portion 116 becomes relatively large as the area of the unit pixel is reduced due to the high definition, which is a major obstacle in miniaturizing the photodiode.
[0014]
As a method for solving the above problems, the present inventor has proposed a photoelectric conversion device having a structure in which formation of an element isolation structure for isolating elements between photodiodes does not easily lead to a decrease in sensitivity of the photodiode, and a method of manufacturing the same (Japanese Patent Application No. 2002-118746).
[0015]
That is, the invention according to Japanese Patent Application No. 2002-118746 (hereinafter referred to as the prior application invention) is a photoelectric conversion device in which a photodiode is formed in each light receiving region.
A semiconductor substrate of a first conductivity type;
Formed on a semiconductor substrate and formed to isolate elements between photodiodes
An element isolation structure in which an insulating film is embedded in the recessed portion,
A second formed in the semiconductor substrate so as to be in contact with and surround the element isolation structure.
A conductive type channel stopper layer;
The first conductive type half of the photodiode, which is formed on the surface of the light receiving region and constitutes the photodiode.
A conductor layer,
A second conductivity type semiconductor layer formed under and in contact with the first conductivity type semiconductor layer
When,
The light receiving area is located outside the light receiving area with respect to the end of the element isolation structure on the light receiving area side.
A first well of a second conductivity type formed so as to surround the first well;
A second well of a second conductivity type formed at the bottom of the light receiving region;
And a method for manufacturing the same.
[0016]
FIGS. 2A and 2B are a schematic cross-sectional view and a schematic plan view, respectively, of a photodiode unit such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor according to a preferred embodiment of the invention of the prior application. On the surface of the substrate, an element isolation structure 7b having an STI (Shallow Trench Isolation) structure for electrically insulating the light receiving region 14 of each photodiode is formed in order to isolate elements between the photodiodes.
[0017]
In this example, an N-type silicon substrate 1 is used as a substrate, and an N-type silicon layer 18 formed on the surface of the substrate and a P⁻A photodiode (PD) is formed by a PN junction at the interface with the shaped silicon layer 12. Hereinafter, a portion surrounded by the element isolation structure 7b is referred to as a light receiving region 14, and a portion in which a PN junction is formed is referred to as a sensor opening 15, and the two are distinguished from each other.
[0018]
When the light incident on the sensor opening 15 reaches the PN junction, it is converted into holes and electrons there, and signal charges (electrons) corresponding to the amount of incident light are converted into N-type silicon layers 18 and N-type layers. P⁻It is accumulated in the shaped silicon layer 12. In addition, P of the outermost surface⁺The type silicon layer 19 is for preventing charge leakage from the surface.
[0019]
The above-described signal charge storage region made of the N-type silicon layer 18 and the like is formed by a P⁺Type channel stopper layer 6, a P-type surface well 11 formed below element isolation structure 7b, a P-type deep well 8 formed deep in the substrate, and a P-type surface well 11 and a P-type deep well 8 Are vertically surrounded by a P-type plug well 10 formed below the element isolation structure 7b so as to be electrically connected to each other. As a result, the signal charge storage region is electrically separated from the peripheral elements even in the substrate, and the signal charge does not leak.
[0020]
P-type surface side well 11 and P-type plug well 10 and P⁻The boundary with the patterned layer 12 is formed at a position recessed by 0.2 μm from the light receiving region 14 below the area immediately below the end of the STI. This is to increase the storage capacity of the signal charges.
[0021]
By comparing FIG. 2B with FIG. 9B, the difference between the photodiode according to the preferred embodiment of the prior application and the conventional photodiode can be clearly understood. In FIG. 2B, the PTI is in contact with the STI element isolation structure 7b.⁺Since the mold channel stopper layer 6 is formed, the P-type layer 116 protruding from the light receiving region 114 shown in FIG. 9B is unnecessary.
[0022]
Also in the STI element isolation structure 7b, a boundary region with large distortion is formed around the periphery, but in the STI structure, after the concave portion is formed, the boundary region is formed by ion implantation from the wall surface of the concave portion.⁺Since the channel stopper layer 6 can be formed, the P-type⁺The mold channel stopper layer 6 can be made thin, and its thickness is 0.1 μm or less, for example, about 30 nm.
[0023]
As described above, since almost the entire light receiving region 14 surrounded by the element isolation structure 7b can be used as the sensor opening 15, the size of the sensor opening is smaller than that of the related art because there is no size shrink by the protruding portion 116 of the P-type surface side well. The area of the portion 15 is increased, and the sensitivity of the photodiode is improved.
[0024]
In addition, in the STI structure 7b, the width of the insulating material for element isolation can be considerably reduced as compared with the LOCOS structure 107 and the like, so that the area of the element isolation structure itself can be reduced.
[0025]
From the above, it is possible to increase the sensor aperture ratio, which is the area ratio of the sensor opening 15 in the unit pixel, and improve the sensitivity of the photodiode.
[0026]
Further, the P extending to a position outside the light receiving region 14 just below the end of the element isolation structure 7b.⁻Since the shaped silicon layer 12 is used as a part of the signal charge storage region, even if a large amount of signal charge is generated at a large light quantity, the signal charge can be stored without being saturated, thereby realizing a large dynamic range. Can be.
[0027]
Next, the points of a method of manufacturing the photodiode portion of the image sensor of FIG. 2 will be described.
[0028]
First, a concave portion is formed around the light receiving region 14 by selective etching. Next, the inner wall of the recess is thermally oxidized to form a thin silicon oxide film on the inner wall of the recess.
[0029]
Next, before filling the concave portion with silicon oxide, an acceleration voltage of 100 keV and an implantation amount (area density) of 2 × 10 are set at an angle of 30 degrees from the inner wall of the concave portion with respect to the direction perpendicular to the substrate.¹³/ Cm²In BF₂ ⁺Ions are implanted. As a result, in the substrate in contact with the side and bottom surfaces of the recess, P⁺A mold channel stopper layer 6 is formed.
[0030]
Next, after burying silicon oxide in the concave portion, excess silicon oxide and the like are removed to form the STI element isolation structure 7b.
[0031]
Next, the entire pixel region including the light receiving region 14 is charged with B at an acceleration voltage of 2 MeV.⁺Thermal diffusion / annealing treatment is performed by ion implantation and heating to form a P-type deep well 8 at a deep position in the substrate. Further, while masking a part of the light receiving region 14 and a part of the STI element isolation structure 7b, the pixel region is exposed to B by accelerating voltages of 1.5 MeV and 1.0 MeV.⁺A thermal diffusion / annealing process is performed by ion implantation and heating to form a P-type plug well 10.
[0032]
Next, in the same manner as described above, while masking the light receiving region 14 and a part of the STI element isolation structure 7b, B at accelerating voltages of 600 keV, 380 keV and 190 keV is used.⁺Thermal diffusion / annealing treatment is performed by ion implantation and heating to form a P-type surface side well 11.
[0033]
The formation of the P-type surface side well 11 means that the signal charge accumulation region of the photodiode such as the N-type silicon layer 18 is separated from other N-type silicon regions in the substrate. Usually, the P-type surface side well 11 is also formed as a P-type well of a semiconductor circuit element of a peripheral circuit in a peripheral circuit portion outside the pixel region.
[0034]
Due to the thermal diffusion during the above-described series of P-type well formation steps, the N-type layer located below the N-type silicon layer 18 becomes P-type.⁻P, surrounded by P-type wells⁻A patterned silicon layer 12 is formed.
[0035]
Subsequently, As with an acceleration voltage of 300 keV is applied to the sensor opening 15.⁺Is performed and a heat annealing process is performed to form an N-type silicon layer 18. This gives P⁻A PN junction (photodiode) is formed at the interface between the shaped silicon layer 12 and the N-type silicon layer 18.
[0036]
Finally, a BF with an acceleration voltage of 50 keV is₂ ⁺Ion implantation and heat annealing to prevent leakage of signal charges from the surface⁺A mold silicon layer 19 is formed.
[0037]
[Problems to be solved by the invention]
FIG. 1B is a conceptual schematic cross-sectional view of the completed CMOS image sensor. In the upper part of the figure, the BF is inserted into the substrate from the inner wall of the recess 4 in the above-described photodiode manufacturing process.₂ ⁺Implant ions and⁺A schematic cross-sectional view showing the state of the step of forming the channel stopper layer 6 has been added.
[0038]
As can be seen from this figure, in this example, ion implantation into the inner wall of the recess 4 is performed on all the recesses 4 on the substrate 1 without selecting the photodiode portion. For this reason, the same concentration of P⁺A channel stopper layer 6 is formed.
[0039]
However, the PTI is usually provided on the STI side wall of the peripheral circuit section.⁺No layer is formed. Even if it is formed, the optimum dopant concentration is the P concentration in the channel stopper layer of the photodiode portion.⁺Much smaller than the optimum dopant concentration of the layer. Since the optimal conditions for both are different, P⁺When the channel stopper layer 6 is formed, the characteristics of the transistors in the peripheral circuit and other elements, or the characteristics of the transistor in the pixel are changed, which may adversely affect the driving of the sensor.
[0040]
Thus, the P formed based on the prior invention is⁺Although the channel stopper layer 6 and the method of forming the channel stopper layer are effective for improving the sensitivity of the photodiode, it has become clear that there is room for improvement in relation to the semiconductor elements around the photodiode.
[0041]
The present invention has been made in view of the above circumstances, and an object of the present invention is to form an element isolation structure for isolating elements between photodiodes, which is unlikely to lead to a decrease in the sensitivity of the photodiode, and to reduce the surrounding area. An object of the present invention is to provide a photoelectric conversion device having a structure that does not adversely affect a semiconductor circuit element and a method for manufacturing the same.
[0042]
[Means for Solving the Problems]
That is, the present invention includes a photodiode formed in each light receiving region on a semiconductor substrate of the first conductivity type, and a semiconductor circuit element formed in a region outside the light receiving region on the semiconductor substrate,
A device formed on the semiconductor substrate and having an insulating film embedded in a concave portion formed to isolate the photodiode and the semiconductor circuit element from each other;
Child separation structure,
A second conductivity type channel stopper layer formed in the semiconductor substrate so as to contact and surround the element isolation structure for isolating the photodiode.
When,
A first part of the photodiode, which is formed on the surface side of the light receiving region and constitutes the photodiode
A conductive semiconductor layer;
A first well of the second conductivity type formed to surround the light receiving region at a position outside the light receiving region with respect to an end of the element isolation structure on the light receiving region side;
A second well of a second conductivity type formed at the bottom of the light receiving region;
A third well of a second conductivity type connecting the first and second wells;
A photoelectric conversion device having:
In the first well in contact with and surrounding the element isolation structure, the channel is located at a position around the light receiving region and between the semiconductor circuit element and the first well.
The stopper layer is over
The present invention relates to a photoelectric conversion device.
[0043]
The present invention also provides a method of manufacturing a photoelectric conversion device, wherein a photodiode is formed in each light receiving region on a semiconductor substrate of a first conductivity type, and a semiconductor circuit element is formed in a region outside the light receiving region on the semiconductor substrate. So,
On the semiconductor substrate, a concave portion for separating the photodiode and the semiconductor circuit element is formed, and an insulating film is buried in the concave portion to separate the element.
Forming a structure;
Forming a channel stopper layer of a second conductivity type in the semiconductor body so as to contact and surround the element isolation structure for element isolation of the photodiode;
A half of the first conductivity type constituting the photodiode is provided on the surface side of the light receiving region.
Forming a conductor layer;
Forming a first well of a second conductivity type with respect to an end of the element isolation structure on the light receiving region side so as to surround the light receiving region at a position outside the light receiving region;
About
Forming a second well of a second conductivity type at the bottom of the light receiving region;
Forming a third well of a second conductivity type connecting the first and second wells;
Process and
A method for manufacturing a photoelectric conversion device having
In the first well in contact with and surrounding the element isolation structure, the first well ends at a position around the light receiving region and between the semiconductor circuit element.
Forming the channel stopper layer
The present invention relates to a method for manufacturing a photoelectric conversion device.
[0044]
According to the present invention, even in the element isolation structure, a boundary region with large distortion is formed around the periphery, but after the formation of the concave portion, the second conductive type channel stopper is formed in the boundary region by impurity doping from the concave portion. Since the layer can be formed, the channel stopper layer can be made thinner as compared with the LOCOS structure, and the sensor aperture ratio, which is the area ratio of the sensor aperture in the unit pixel, is increased, thereby improving the sensitivity of the photodiode. be able to.
[0045]
In addition, since the channel stopper layer ends at a position around the light receiving region and between the semiconductor circuit element, the formation of the channel stopper layer adversely affects the semiconductor circuit element. There is nothing.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, it is preferable that the element isolation structure is provided at least around the light receiving region.
[0047]
The device isolation structure is preferably an STI (Shallow Trench Isolation) structure. In the STI structure, the width of the insulating material for element isolation can be considerably reduced as compared with the LOCOS structure or the like, so that the area of the element isolation structure itself can be reduced.
[0048]
In the present invention, after the concave portion is formed and before the insulating film is embedded in the concave portion, ions are removed from the wall surface of the concave portion of the photodiode portion while masking portions other than the photodiode portion around the photodiode portion. It is preferable that the channel stopper layer of the photodiode portion is formed by implantation.
[0049]
Further, the element isolation structure may be provided between the photodiode in the light receiving region and the semiconductor circuit element in the non-light receiving portion around the photodiode, and / or the semi-conductor circuit element in the non-light receiving portion and the peripheral circuit portion. It may also be provided between the semiconductor circuit element.
[0050]
In that case, the first well is also formed in a formation region of the semiconductor circuit element of the non-light receiving portion and / or the semiconductor circuit element of the peripheral circuit portion, and the first well is formed in the element isolation structure around the semiconductor circuit element. It is preferable that a channel stopper layer is formed at a lower concentration than the channel stopper layer of the photodiode portion also in the first well surrounding and surrounding the first well.
[0051]
By forming the channel stopper layer of the semiconductor circuit element portion separately from the channel stopper layer of the photodiode portion, a channel stopper layer having an optimum impurity concentration can be formed.
[0052]
In the present invention, after the concave portion is formed and before the concave portion is filled with the insulating film, the photodiode portion and the semiconductor circuit element portion of the non-light receiving portion and / or the semiconductor circuit element portion of the peripheral circuit portion It is preferable that the channel stopper layer of the semiconductor circuit element portion is formed by ion-implanting from the wall surface of the concave portion while masking.
[0053]
In forming the element isolation structure, it is preferable that an insulating material for element isolation be buried in the recess by a vapor phase growth method.
[0054]
Preferably, the first, second and third wells are formed by ion implantation. According to the ion implantation method, a predetermined concentration of a dopant can be accurately doped at a predetermined position. Therefore, for example, a well can be formed in a deep portion of the semiconductor substrate, which cannot be achieved by the thermal diffusion method.
[0055]
A solid-state imaging device may be manufactured according to the present invention.
[0056]
Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.
[0057]
Embodiment 1: CMOS image sensor (1)
FIG. 2 is a schematic sectional view (a) and a schematic plan view (b) of a photodiode section of a CMOS (Complementary Metal Oxide Semiconductor) image sensor according to a preferred embodiment of the present invention. On the surface of the substrate, an element isolation structure 7b having an STI (Shallow Trench Isolation) structure for electrically insulating the light receiving region 14 of each photodiode is formed in order to isolate elements between the photodiodes.
[0058]
In this example, an N-type silicon substrate 1 is used as a substrate, and an N-type silicon layer 18 above the substrate and a P-type silicon layer 18 thereunder are used.⁻The shaped silicon layer 12 forms a PN junction photodiode at the interface.
[0059]
When the light incident on the sensor opening 15 of the light receiving region 14 reaches the PN junction, the light is converted into holes and electrons there, and signal charges (electrons) corresponding to the amount of incident light are converted into N-type silicon layers 18 and further. N-type layer is P⁻It is accumulated in the shaped silicon layer 12. In addition, P of the outermost surface⁺The type silicon layer 19 prevents leakage of electric charge from the surface.
[0060]
The signal charge storage region formed of the N-type silicon layer 18 is formed by a P⁺Type channel stopper layer 6, a P-type surface well 11 formed below element isolation structure 7b, a P-type deep well 8 formed deep in the substrate, and a P-type surface well 11 and a P-type deep well 8 Are vertically surrounded by a P-type plug well 10 formed below the element isolation structure 7b so as to be electrically connected to each other. As a result, the N-type signal charge storage region 18 is electrically separated from the peripheral elements even in the substrate, and the signal charge does not leak.
[0061]
P-type surface side well 11 and P-type plug well 10 and P⁻The boundary with the patterned layer 12 is formed at a position recessed by 0.2 μm from the light receiving region 14 below the area immediately below the end of the STI. This is to increase the storage capacity of the signal charges.
[0062]
Since the structure of the above-described photodiode is the same as the photodiode according to the invention of the prior application, it goes without saying that the same effect is obtained.
[0063]
That is, P is in contact with the STI element isolation structure 7b.⁺Since the mold channel stopper layer 6 is formed, the P-type layer 116 protruding from the light receiving region 114 shown in FIG. 9B is unnecessary.
[0064]
Also in the STI element isolation structure 7b, a boundary region with large distortion is formed around the periphery, but in the STI structure, after the concave portion is formed, the boundary region is formed by ion implantation from the wall surface of the concave portion.⁺Since the channel stopper layer 6 can be formed, the P-type⁺The mold channel stopper layer 6 can be made thin, and its thickness is 0.1 μm or less, for example, about 30 nm.
[0065]
As described above, since almost the entire light receiving region 14 surrounded by the element isolation structure 7b can be used as the sensor opening 15, the area of the sensor opening 15 becomes larger than before, and the sensitivity of the photodiode is improved.
[0066]
In addition, in the STI structure 7b, the width of the insulating material for element isolation can be considerably reduced as compared with the LOCOS structure 107 and the like, so that the area of the element isolation structure itself can be reduced.
[0067]
As described above, it is possible to increase the sensor aperture ratio, which is the area ratio of the sensor aperture in the unit pixel, and improve the sensitivity of the photodiode.
[0068]
Further, the P extending to a position outside the light receiving region 14 just below the end of the element isolation structure 7b.⁻Since the shaped silicon layer 12 is used as a part of the signal charge storage region, even if a large amount of signal charge is generated at a large light quantity, the signal charge can be stored without being saturated, thereby realizing a large dynamic range. Can be.
[0069]
FIG. 3 is a schematic configuration diagram showing a configuration of a CMOS image sensor in which the photodiodes are arranged in a two-dimensional matrix on a substrate. In this device, rows and columns are selected by the vertical scanner 32 and the horizontal scanner 34, respectively, and signal charges of the photodiodes of the pixels 31 at the intersections are read.
[0070]
That is, the read transistor 33 of a certain row is selected by the control signal from the vertical scanner 32 to be turned on, and at the same time, the read signal is sequentially applied to each column by the horizontal scanner 34. Is output to the input part of the current-voltage conversion circuit 35, and is converted into a voltage by the current-voltage conversion circuit 35 and the output buffer circuit 36 and output.
[0071]
During one cycle of the vertical scanner 32, all the pixels 31 are sequentially scanned once, and the output corresponding to the signal charge stored in the photodiode of each pixel 31 during one cycle is read out. Thereafter, the photodiode is erased from the charge and reset to the initial state. Thus, the video signal photoelectrically converted by the photodiodes arranged in a two-dimensional matrix is output in a time-division manner.
[0072]
Each pixel 31 in FIG. 3 is formed in a pixel area 37 on the substrate, and peripheral circuits such as a vertical scanner 32, a readout transistor 33, a horizontal scanner 34, a current-voltage conversion circuit 35, and an output buffer circuit 36 are formed in a pixel area 37. Is formed in the peripheral circuit section 38 adjacent to the.
[0073]
FIG. 4 is a plan view showing an arrangement in the pixel region 37. FIG. 4A is an overall view showing a state in which a number of pixels 31 are arranged in a two-dimensional matrix, and FIG. 4B is a plan view showing an arrangement in one pixel 31. . FIG. 4 shows only the N-type diffusion layers 18 and 43 formed above the P-type silicon layer, the gate layers 42, 45 and 48, the contacts 41, 44, 47 and 49, and the upper layer wiring is not shown. are doing. The gate layer is formed of polycrystalline silicon, and the lower portion is a P-type layer.
[0074]
As shown in FIG. 2, the N-type silicon layer 18 shown in FIG.⁻A photodiode is formed by a PN junction at the interface with the shaped silicon layer 12 and generates signal charges (electrons) according to the amount of incident light. The signal charges (electrons) are stored in the signal charge storage region mainly including the N-type region 18 for one cycle.
[0075]
The read signal from the horizontal scanner 34 in FIG. 3 is applied to the transfer gate 42 through the contact 41 in FIG. When the channel layer below the transfer gate 42 becomes conductive due to the operation of the read signal, the signal charges (electrons) accumulated in the signal charge accumulation region such as the N-type silicon layer 18 are formed in the non-light receiving portion in the pixel. Is transferred to the N-type buffer layer 43 and generates a signal voltage corresponding to the signal charge amount.
[0076]
This signal voltage is applied to the gate 45 of the amplifying transistor through the contact 44, and is read as a change in the current flowing through the amplifying transistor 46. The output current of the amplifying transistor 46 is guided to the read transistor 33 of FIG. 3, and is converted into a voltage and output as described above.
[0077]
When the reading is completed, a reset signal is applied to the reset gate 48 through the contact 47, the signal charge stored in the N-type buffer layer 43 is erased through the contact 49, and the photodiode is reset to the initial state.
[0078]
As described above, one pixel includes the photodiode formed in the light receiving portion and the various semiconductor circuit elements formed in the non-light receiving portion. Therefore, it is necessary to separate the elements from each other.
[0079]
The extension of the N-type silicon layer 18 in FIG. 4 corresponds to the sensor opening 15 (FIG. 2). Therefore, the P formed in contact with the STI element isolation structure of the photodiode portion⁺The end 50A of the channel stopper layer 6 on the light receiving region side is located at the outer peripheral portion (solid line) of the N-type silicon layer 18. The other end 50B is located at the position indicated by the broken line and ends between the non-light receiving portion and the region where the amplification transistor 46 is formed.
[0080]
FIG. 1A illustrates a CMOS image sensor in which a peripheral circuit portion is cut first, then a non-light receiving portion (for example, AB in FIG. 4B) of the pixel is cut, and then a light receiving portion of the pixel is cut. FIG. 5 is a conceptual schematic cross-sectional view obtained by joining cross-sectional views obtained by cutting (for example, B-C in FIG. 4B).
[0081]
In the upper part of FIG. 1A, in a CMOS image sensor manufacturing process to be described later, BF₂ ⁺Implant ions and⁺A schematic cross-sectional view showing the state of the step of forming the channel stopper layer 6 has been added.
[0082]
As can be seen in FIG.₂ ⁺When implanting ions, since the semiconductor circuit element portion of the non-light receiving portion and the semiconductor circuit element portion of the peripheral circuit portion are covered with the mask 30, P⁺The channel stopper layer 6 is formed only under the STI element isolation structure of the photodiode part, ends at an intermediate position 50B of the STI element isolation structure with the semiconductor circuit element part of the pixel region non-light receiving part, and extends to the semiconductor circuit element part. Is not growing. Therefore, there is no fear that the transistor 51 in the pixel (eg, the transistor 46 for amplification) or the transistor 52 of the peripheral circuit section 38 and other elements are adversely affected.
[0083]
Although the P-type deep well 8 and the P-type plug well 10 can be formed only in the light receiving portion, it is usually desirable to form the P-type deep well 8 and the P-type plug well 10 in the entire pixel region from the light receiving portion to the non-light receiving portion. This is to prevent the leakage of signal charges more effectively.
[0084]
Although the P-type surface side well 11 can be formed only in the light receiving portion, it is usually formed simultaneously with the P-type well of the semiconductor circuit element formed in the peripheral circuit portion and the non-light receiving portion. This is to prevent the leakage of signal charges more effectively and to efficiently form an image sensor.
[0085]
The transistors 51 and 52 formed in the peripheral circuit portion and the non-light receiving portion preferably have an LDD (Lightly Doped Drain-source) structure. This alleviates the drain electric field and improves the withstand voltage.
[0086]
Embodiment 2: Fabrication of CMOS image sensor (1)
5 to 7 are schematic cross-sectional views showing steps of manufacturing the CMOS image sensor (1) shown in Embodiment 1 by a method of manufacturing a photoelectric conversion device according to a preferred embodiment of the present invention in the order of steps.
[0087]
Step 1
First, as shown in FIG. 5A, a silicon oxide film 2 and a silicon nitride film 3 are formed on the surface of an N-type semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method or the like, and then the STI structure 7b is formed. These films 2 and 3 are patterned into a shape corresponding to the pattern of the recess 4.
[0088]
Step 2
Next, as shown in FIG. 5B, using the silicon oxide film 2 and the silicon nitride film 3 as a mask, the silicon is removed by dry etching (reactive ion etching) or the like, thereby forming the concave portion 4.
[0089]
Step 3
Next, as shown in FIG. 5C, the inner wall of the recess 4 is thermally oxidized to form a thin silicon oxide film 5 on the inner wall of the recess 4.
[0090]
Step 4
Next, before filling the concave portion 4 with silicon oxide, the peripheral circuit portion and the non-light receiving portion are covered with the mask 30 as shown in FIG. Quantity (area density) 2 × 10¹³/ Cm²In BF₂ ⁺Ions are implanted from the inner wall of the recess 4 so that P⁺A mold channel stopper layer 6 is formed.
[0091]
At this time, as described with reference to FIG.⁺The mold channel stopper layer 6 is formed only in the light receiving portion, and does not adversely affect the peripheral circuit portion 38 and the semiconductor circuit elements formed in the non-light receiving portion.
[0092]
Step 5
Next, as shown in FIG. 6E, silicon oxide 7a is deposited by a CVD (Chemical Vapor Deposition) method or the like, and the silicon oxide 7a is buried in the trench 4.
[0093]
Step 6
Next, as shown in FIG. 6 (f), the surface is polished by a CMP (Chemical Mechanical Polishing) method or the like, and the extra silicon oxide, silicon nitride film 3, and silicon oxide film 2 are sequentially removed to remove the STI element. The structure 7b is completed.
[0094]
Step 7
Next, as shown in FIG. 6G, while covering the peripheral circuit portion 38 with the mask 21, the acceleration voltage 2 MeV and the implantation amount (area density) 5 × 10 are applied to the entire pixel region 37 including the light receiving region 14.¹¹/ Cm²And B⁺Ions are implanted, followed by thermal diffusion and annealing by heating to form a P-type deep well 8 at a deep position in the substrate.
[0095]
Step 8
Next, as shown in FIG. 6H, an acceleration voltage of 1.5 MeV is implanted below the STI structure 7b while covering the peripheral circuit portion 38, the light receiving region 14, and a part of the STI element isolation structure 7b with the mask 9. Quantity (area density) 8 × 10¹¹/ Cm², And an acceleration voltage of 1.0 MeV, an areal density of 3 × 10¹²/ Cm²And B⁺Ions are implanted, followed by thermal diffusion and annealing by heating to form a P-type plug well 10.
[0096]
Although the P-type deep well 8 and the P-type plug well 10 can be formed only in the light receiving portion, it is generally preferable that the P-type deep well 8 and the P-type plug well 10 are formed in the entire pixel region 37 from the light receiving portion to the non-light receiving portion. This is to prevent the leakage of signal charges more effectively.
[0097]
Step 9
Next, as shown in FIG. 7 (i), while covering the light receiving region 14 and a part of the STI element isolation structure 7b with a mask 32, an acceleration voltage of 600 keV and an implantation amount (area density) of 3 × 10¹²/ Cm²An acceleration voltage of 380 keV and an area density of 3 × 10¹²/ Cm²; And an acceleration voltage of 190 keV and an injection amount (area density) of 6 × 10¹²/ Cm²And B⁺Ions are implanted, followed by thermal diffusion and annealing by heating to form a P-type surface-side well 11.
[0098]
This means that the N-type silicon layer of the light receiving region 14 is separated from other N-type silicon regions by the P-type surface side well 11. The P-type surface side well 11 can be formed only in the light receiving section, but is usually formed simultaneously with the P-type well of the semiconductor circuit element formed in the peripheral circuit section 38 and the non-light receiving section. This is to prevent the leakage of signal charges more effectively and to efficiently form an image sensor.
[0099]
Also, due to thermal diffusion during the well formation, the N-type silicon layer becomes P-type.⁻P, surrounded by P-type wells⁻A shaped silicon layer 12 is formed.
[0100]
Step 10
Next, as shown in FIG. 7J, an acceleration voltage of 300 keV and an injection amount (area density) of 2 × 10 are applied to the sensor opening 15 while masking a portion other than the sensor opening 15.¹²/ Cm²In As⁺Ions are implanted, followed by heat annealing to form an N-type silicon layer 18. Thus, a PN junction (photodiode) is formed at the interface between the P-type silicon layer 12 and the N-type silicon layer 18. Therefore, as shown in FIG.⁺The region surrounded by the mold channel stopper layer 6 becomes the sensor opening 15.
[0101]
Step 11
Next, as shown in FIG. 4 (k), while masking portions other than the light receiving portion 14, an acceleration voltage of 50 keV and an area density of 1 × 10¹³/ Cm²In BF₂ ⁺Ions are implanted, followed by heat annealing,⁺A mold silicon layer 19 is formed.
[0102]
Step 12
Finally, after an oxide film is formed on the substrate surface in a desired region of the peripheral circuit portion and the non-light receiving portion by thermal oxidation, semiconductor circuit elements such as the non-light receiving portion transistor 51 and the peripheral circuit portion transistor 52 are formed by a known method. I do.
[0103]
Embodiment 3: CMOS image sensor (2) and fabrication thereof
FIG. 8A is a conceptual schematic cross-sectional view of a CMOS image sensor (2) which is a modification of the first embodiment. In the upper part of the figure, a fabrication process 4a is added, and BF₂ ⁺Implant ions and⁺A schematic cross-sectional view showing the state of the step of forming the channel stopper layer 6a has been added.
[0104]
In this modification, the manufacturing process described in the second embodiment is performed in the same manner as in step 4 (while covering the peripheral circuit portion 38 and the non-light receiving portion with the mask 30, the acceleration voltage is 100 keV and the injection amount is (Area density) 2 × 10¹³/ Cm²In BF₂ ⁺Ions are implanted from the inner wall of the recess 4 so that P⁺After the step of forming the mold channel stopper layer 6), the following step 4a is additionally performed.
[0105]
Step 4a
As shown in FIG. 8A, while covering the light receiving portion with the mask 30a, the acceleration voltage is 100 keV and the injection amount (area density) is 1 × 10 at an angle of 30 degrees from the vertical direction of the substrate.¹³/ Cm²In BF₂ ⁺Ions are implanted from the inner wall of the recess 4 into the peripheral circuit portion 38 and the non-light receiving portion.⁺A mold channel stopper layer 6a is formed.
[0106]
Thus, the peripheral circuit section 38 and the non-light receiving section have the P⁺Having a lower concentration than the channel stopper layer 6⁺A mold channel stopper layer 6a is formed. This concentration can be an optimum concentration that does not adversely affect the semiconductor circuit elements formed in this region.
[0107]
P⁺Except for the addition of the mold channel stopper layer 6a, there is no difference from the first embodiment. Needless to say, the effects described in the first embodiment can also be obtained in the third embodiment.
[0108]
Embodiment 4: CMOS image sensor (3) and fabrication thereof
FIG. 8B is a conceptual schematic cross-sectional view of a CMOS image sensor (3) which is also a modification of the first embodiment. In the upper part of the figure, as a manufacturing step 4b, a BF₂ ⁺Implant ions and⁺A schematic cross-sectional view showing the state of the step of forming the channel stopper layer 6b has been added.
[0109]
In this modification, the manufacturing process described in the second embodiment is performed in the same manner as in Step 4 (while the peripheral circuit portion 38 and the light receiving portion are covered with the mask 30, the acceleration voltage is 100 keV and the injection amount ( Area density) 2 × 10¹³/ Cm²In BF₂ ⁺Ions are implanted from the inner wall of the recess 4 so that P⁺After the step of forming the mold channel stopper layer 6), the following step 4b is additionally performed.
[0110]
Step 4b
As shown in FIG. 8B, while the peripheral circuit portion 38 and the light receiving portion are covered with the mask 30b, the acceleration voltage is 100 keV and the implantation amount (area density) is 1 × 10 at an angle of 30 degrees from the vertical direction of the substrate.¹³/ Cm²In BF₂ ⁺Ions are implanted from the inner wall of the recess 4 and P⁺A mold channel stopper layer 6b is formed.
[0111]
As a result, only the non-light-receiving portion has a P⁺Having a lower concentration than the channel stopper layer 6⁺A mold channel stopper layer 6b is formed. This concentration can be an optimum concentration that does not adversely affect the semiconductor circuit elements formed in this region.
[0112]
Normally, since the element isolation structure of the non-light receiving portion is in contact with the P-type well, leakage of electric charge is likely to occur.⁺The effect of providing the mold channel stopper layer 6b is high. In addition, the threshold voltage V_THAnd current characteristics I_DHas an effect that can be adjusted to a preferable value.
[0113]
P⁺Except for the addition of the mold channel stopper layer 6b, there is no difference from the first embodiment. Needless to say, the effects described in the first embodiment can also be obtained in the fourth embodiment.
[0114]
As described above, the present invention has been described based on the embodiments. However, it is needless to say that the present invention is not limited to these examples, and can be appropriately changed without departing from the gist of the invention.
[0115]
For example, the above-described ion implantation for forming a well may be performed before forming an element isolation structure by STI. Further, the conductivity type of each of the above-described semiconductor regions may be reversed. The element isolation of the peripheral circuit section 38 may be performed by a method other than the STI structure.
[0116]
Operation and Effect of the Invention
According to the present invention, even if a boundary region with large distortion is formed around the element isolation structure, the channel stopper layer of the second conductivity type can be formed in the boundary region by doping impurities from the concave portion after the concave portion is formed. As compared with the structure, the channel stopper layer can be made thinner, and the sensor aperture ratio, which is the area ratio of the sensor opening in a unit pixel, can be increased, and the sensitivity of the photodiode can be improved.
[0117]
Particularly, in the STI structure, the width of the insulating material for element isolation can be considerably reduced as compared with the LOCOS structure or the like, so that the area of the element isolation structure itself can be reduced.
[0118]
As described above, it is possible to increase the sensor aperture ratio, which is the area ratio of the sensor aperture in the unit pixel, and improve the sensitivity of the photodiode.
[0119]
In addition, since the channel stopper layer ends at a position around the light receiving region and between the semiconductor circuit element, the formation of the channel stopper layer does not adversely affect the semiconductor circuit element.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a CMOS image sensor according to a preferred embodiment of the present invention and the prior application.
FIG. 2 is a schematic sectional view (a) and a schematic plan view (b) of a photodiode portion of a CMOS image sensor according to a preferred embodiment of the present invention and a preferred embodiment of the present invention.
FIG. 3 is a configuration diagram of a CMOS image sensor based on an embodiment of the present invention.
FIG. 4 is a plan view showing the arrangement of the pixel regions.
FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the CMOS image sensor.
FIG. 6 is a schematic sectional view showing a manufacturing process of the CMOS image sensor.
FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the CMOS image sensor.
FIG. 8 is a schematic sectional view of a CMOS image sensor according to another preferred embodiment of the present invention.
9A and 9B are a schematic cross-sectional view and a schematic plan view of a photodiode section of a conventional image sensor.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... N-type semiconductor substrate, 2 ... silicon oxide film, 3 ... silicon nitride film, 4 ... concave part,
5: silicon oxide film, 6: P⁺Mold channel stopper layer, 7a: silicon oxide,
7b: element isolation structure (STI structure), 8: P-type deep well, 9: mask,
10 ... P-type plug well, 11 ... P-type surface side well,
12 ... P⁻Molded silicon layer, 13 mask, 14 light receiving area,
15: Sensor opening, 18: N-type silicon layer, 19: P⁺Mold silicon layer,
20, 21, 30, 30a, 30b ... mask, 31 ... pixel,
32: vertical direction scanner, 33: readout transistor,
34 ... horizontal direction scanner, 35 ... current-voltage conversion circuit, 36 ... output buffer circuit,
37: pixel area, 38: peripheral circuit section, 41: contact, 42: transfer gate,
43 ... N-type buffer layer, 44 ... Contact,
45: gate of a transistor for amplification, 46: transistor for amplification,
47 ... contact, 48 ... reset gate, 49 ... contact,
50A ... P⁺End of the mold channel stopper layer on the light receiving region side,
50B ... P⁺The other end of the mold channel stopper layer,
51: non-light receiving transistor, 52: peripheral circuit transistor,
101: N-type semiconductor substrate, 102: silicon oxide film,
107: element isolation structure (LOCOS structure), 108: P-type deep well,
110: P-type plug well, 111: P-type surface side well,
112 ... P⁻Molded silicon layer, 114: light receiving area, 115: sensor opening,
116 ... P-type surface side well protruding portion, 118 ... N-type silicon layer,
119 ... P⁺Type silicon layer, 120 ... boundary region with large distortion

Claims (16)

A photodiode formed in each light receiving region on the semiconductor substrate of the first conductivity type, and a semiconductor circuit element formed in a region outside the light receiving region on the semiconductor substrate;
An element isolation structure formed on the semiconductor substrate and having an insulating film embedded in a recess formed for isolating the photodiode and the semiconductor circuit element;
A second conductivity-type channel stopper layer formed in the semiconductor substrate so as to be in contact with and surround the element isolation structure for isolating the photodiode,
A first part of the photodiode, which is formed on the surface side of the light receiving region and constitutes the photodiode.
A conductive semiconductor layer;
A first well of the second conductivity type formed to surround the light receiving region at a position outside the light receiving region with respect to an end of the element isolation structure on the light receiving region side;
A second well of a second conductivity type formed at the bottom of the light receiving region;
A photoelectric conversion device having a third well of a second conductivity type connecting the first and second wells,
In the photoelectric conversion device, the channel stopper layer ends at a position around the light receiving region and between the semiconductor circuit element and the first well in contact with and surrounding the element isolation structure. The photoelectric conversion device according to claim 1, wherein the element isolation structure is provided at least around the light receiving region. The element isolation structure may be provided between the photodiode in the light receiving region and the semiconductor circuit element in a non-light receiving portion around the photodiode and / or the semiconductor circuit element in the non-light receiving portion and the semiconductor circuit in a peripheral circuit portion The photoelectric conversion device according to claim 2, wherein the photoelectric conversion device is provided between the photoelectric conversion device and the element. The first well is also formed in a formation region of the semiconductor circuit element of the non-light receiving portion and / or the semiconductor circuit element of the peripheral circuit portion, and the first well is formed in contact with the element isolation structure around the semiconductor circuit element. 4. The photoelectric conversion device according to claim 3, wherein a channel stopper layer is formed also in the first well surrounding the channel stopper layer at a lower concentration than the channel stopper layer. 5. The photoelectric conversion device according to claim 1, wherein the element isolation structure is an STI (Shallow Trench Isolation) structure. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is a solid-state imaging device. A method of manufacturing a photoelectric conversion device, comprising: forming a photodiode in each light receiving region on a semiconductor substrate of a first conductivity type; and forming a semiconductor circuit element in a region outside the light receiving region on the semiconductor substrate.
Forming, on the semiconductor substrate, a concave portion for element isolation between the photodiode and the semiconductor circuit element, and forming an element isolation structure by embedding an insulating film in the concave portion;
Forming a channel stopper layer of a second conductivity type in the semiconductor body so as to contact and surround the element isolation structure for element isolation of the photodiode;
Forming a first conductive type semiconductor layer constituting the photodiode on the surface side of the light receiving region;
Forming a first well of the second conductivity type with respect to an end of the element isolation structure on the light receiving region side so as to surround the light receiving region at a position outside the light receiving region;
A photoelectric conversion device having a step of forming a second well of a second conductivity type at the bottom of the light receiving region and a step of forming a third well of a second conductivity type connecting the first and second wells; The method of manufacturing
A photoelectric conversion device that forms the channel stopper layer so as to end at a position between the semiconductor circuit element and the periphery of the light receiving region in the first well in contact with and surrounding the element isolation structure; Manufacturing method. The photoelectric conversion device according to claim 7, wherein the element isolation structure is provided at least around the light receiving region. The element isolation structure may be provided between the photodiode in the light receiving region and the semiconductor circuit element in a non-light receiving portion around the photodiode and / or the semiconductor circuit element in the non-light receiving portion and the semiconductor circuit element in a peripheral circuit portion. The photoelectric conversion device according to claim 8, wherein the photoelectric conversion device is provided also between the photoelectric conversion device. The first well is also formed in a formation region of the semiconductor circuit element of the non-light receiving portion and / or the semiconductor circuit element of the peripheral circuit portion, and the first well is formed in contact with the element isolation structure around the semiconductor circuit element. The method for manufacturing a photoelectric conversion device according to claim 9, wherein a channel stopper layer is formed at a lower concentration than the channel stopper layer also in the first well surrounding the first well. The method according to claim 7, wherein the element isolation structure is an STI (Shallow Trench Isolation) structure. After the recess is formed, before the insulating film is buried in the recess, ion implantation is performed from the wall surface of the recess of the photodiode while masking portions other than the photodiode around the photodiode. The method for manufacturing a photoelectric conversion device according to claim 7, wherein a channel stopper layer is formed. After forming the concave portion and before embedding the insulating film in the concave portion, the photodiode portion and the semiconductor circuit element portion of the non-light receiving portion and / or the semiconductor circuit element portion of the peripheral circuit portion are masked while being masked. The method for manufacturing a photoelectric conversion device according to claim 10, wherein the channel stopper layer of the semiconductor circuit element portion is formed by implanting ions from a wall surface of the concave portion. The method for manufacturing a photoelectric conversion device according to claim 7, wherein after forming the concave portion, an insulating material for element isolation is embedded in the concave portion by a vapor deposition method. The method according to claim 7, wherein the first, second, and third wells are formed by ion implantation. The method for manufacturing a photoelectric conversion device according to claim 7, wherein the solid-state imaging device is manufactured.

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