JP4725673B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device, in particular, a MOS type or C-MOS type solid-state imaging device and a method for manufacturing the same.

  As a solid-state imaging device, each unit pixel is configured to have a sensor unit and a switching element by a photodiode, read out the signal charge accumulated in the sensor unit by photoelectric conversion, converts it into voltage or current, and outputs it A so-called MOS type or C-MOS type solid-state imaging device is known. In these MOS-type or C-MOS-type solid-state imaging devices, for example, a MOS transistor or a C-MOS transistor is used as a switching element for selecting a pixel or a switching element for reading a signal charge. In addition, MOS transistors or C-MOS transistors are used in peripheral circuits such as a horizontal scanning circuit and a vertical scanning circuit, and there is an advantage that manufacturing can be performed with a series of configurations with switching elements.

  Conventionally, in a MOS-type or C-MOS-type solid-state imaging device using a pn junction transistor as a photodiode constituting a sensor unit, the sensor unit of each pixel has an element isolation layer by selective oxidation, a so-called LOCOS (local oxidation). of silicon) layer, the pixels are separated into an XY matrix.

As shown in FIG. 22, in the photodiode 1 serving as a sensor unit, for example, a p-type semiconductor well region 3 is formed on an n-type silicon semiconductor substrate 2 and then an element isolation layer (LOCOS layer) 4 is formed by selective oxidation. Then, n-type impurities 6 such as arsenic (As) or phosphorus (P) are ion-implanted into the surface of the p-type semiconductor well region 3 through a thin insulating film (for example, SiO ₂ film) 5 to form an n-type semiconductor layer. 7 is formed.

JP-A-10-98176 JP-A-10-308507

  By the way, when forming the photodiode 1 serving as the sensor portion, in order to dope the n-type impurity 6, as shown in FIG. 22 described above, other regions are protected by the photoresist layer 8 aligned on the element isolation layer 4. In order to perform ion implantation, a pn junction appears at the end A of the element isolation layer 4. It is known that crystal defects such as dislocation are generated due to stress at the end A of the element isolation layer 4. Accordingly, when the depletion layer generated by applying a reverse bias to the pn junction j comes to the region of the element isolation layer end having the crystal defect, the leakage current increases due to the electric field. When the leak current increases in the sensor unit (photodiode) 1, signal charges are generated even in a state where no light is incident, and a dark current is generated. Since this dark current is generated due to crystal defects, the amount of generation varies depending on each sensor unit 1 and appears uneven in image quality.

  On the other hand, in such a sensor unit (photodiode) 1, in order to further improve the photoelectric conversion efficiency, it is desired to widen the depletion layer so that signal charges photoelectrically converted at a deep position can be used. Yes.

  In view of the above, the present invention provides a solid-state imaging device and a method for manufacturing the same, in which at least dark current due to leakage current is reduced.

A solid-state imaging device according to the present invention includes a first conductivity type first semiconductor well region formed in a second conductivity type semiconductor region, and a high resistance semiconductor region formed on the first semiconductor well region. And a sensor portion having a second resistance type charge storage region formed on the surface of the high resistance semiconductor region, wherein the high resistance semiconductor region has a specific resistance higher than a specific resistance of the charge storage region, and the sensor portion is separated into pixels. an element isolation layer by selective oxidation, a first semiconductor region end and the lower the reached first semiconductor well region I covered, and the first conductivity type in contact with the charge storage region and the high-resistance semiconductor region of the element isolation layer to have a.

In the solid-state imaging device of the present invention, the first conductive type first semiconductor region that covers the end portion and the lower portion of the element isolation layer by selective oxidation and is in contact with the second conductive type charge storage region of the sensor unit is formed. The sensor part is separated from the end of the element isolation layer, and the generation of leak current at the end of the element isolation layer is suppressed, that is, depletion at the interface with the element isolation layer is prevented, and the generation of leak current from this region is suppressed. Dark current is reduced.

The first conductivity type first semiconductor region reaches the first conductivity type first semiconductor well region constituting a part of the sensor portion, and the second conductivity type charge storage region constituting the sensor portion and the high resistance Since it is formed in contact with the semiconductor region, the spread depth of the depletion layer is increased.

The method for manufacturing a solid-state imaging device according to the present invention includes a step of forming an element isolation layer by selective oxidation to separate pixels in a second conductivity type semiconductor region, and an end of the element isolation layer by ion implantation after the element isolation layer is formed. parts and lower have covered, forming a first semiconductor region of a first conductivity type to reach the region for forming a first semiconductor well region of a first conductivity type lower, first of the first conductivity type A semiconductor well region is formed, a first semiconductor well region is formed in the second conductivity type semiconductor region separated by pixels in the element isolation layer, and the first conductivity type first is formed on the first semiconductor well region. A high resistance semiconductor region in contact with one semiconductor region, and a second conductivity type charge storage region in contact with the first conductivity type first semiconductor region formed on the surface of the high resistance semiconductor region. A specific resistance higher than that of the storage region And a step of forming a sensor portion for.

In the method for manufacturing a solid-state imaging device according to the present invention, since the semiconductor region is formed by ion implantation after the element isolation layer is formed, the heat treatment at the time of forming the element isolation layer is performed first, and the re-diffusion of the first semiconductor region is performed. Thus, it is possible to accurately set the pn junction position between the charge storage region of the sensor unit and the semiconductor region. Since the first semiconductor region is formed so as to cover the end portion and the lower portion of the element isolation layer, the pn junction of the sensor portion can be separated from the end of the element isolation layer where a cause of leakage current such as dislocation exists. The current can be reduced. The first semiconductor region is formed so as to reach the first semiconductor well region of the first conductivity type, and is formed in contact with the second conductivity type charge storage region and the high resistance semiconductor region constituting the sensor portion. Increase the spreading depth of the layer.

  According to the solid-state imaging device of the present invention, the first conductive type first semiconductor region in contact with the second conductive type charge storage region of the sensor unit is formed to cover the end portion and the lower portion of the element isolation layer by selective oxidation. By doing so, the pn junction of the sensor portion can be separated from the end of the element isolation layer where the cause of leakage current such as dislocation exists, and the generation of leakage current can be suppressed and dark current can be reduced.

In the solid-state imaging device, the sensor unit includes a first conductivity type first semiconductor well region formed in the second conductivity type semiconductor region, and a high resistance semiconductor region formed on the first semiconductor well region. And the second conductivity type charge storage region formed on the surface of the high resistance semiconductor region, wherein the first conductivity type first semiconductor region is the first conductivity type first semiconductor well region. Therefore , it is possible to increase the spread depth of the depletion layer and improve the photoelectric conversion efficiency in the sensor unit. Therefore, both reduction of dark current and improvement of photoelectric conversion efficiency can be achieved.

  In the solid-state imaging device, the second semiconductor well of the first conductivity type formed so that the end portion exists inside the end portion of the element isolation layer between the first semiconductor region and the first semiconductor well region. When the region is included, the area of the high resistance semiconductor region is larger than the area of the charge storage region. As the area of the high-resistance semiconductor region is increased, the photoelectric conversion efficiency is further improved, and it is possible to improve both the photoelectric conversion efficiency and the dark current.

In the solid-state imaging device, the first conductivity type first semiconductor well region is formed at a required depth position of the second conductivity type semiconductor region, and the second conductivity type separated by the first semiconductor well region. When a charge accumulation region is formed on the surface of the semiconductor region surface side, a high resistance semiconductor region is formed by the separated surface side region, and the sensor portion is formed, the depletion layer has a large spreading depth. can do. Therefore, dark current can be reduced and photoelectric conversion efficiency can be improved.

  According to the method for manufacturing a solid-state imaging device according to the present invention, the first semiconductor region of the first conductivity type is formed without being affected by the heat treatment during the formation of the element isolation layer, and the charge storage region of the sensor unit is the element isolation end. Therefore, it is possible to manufacture a solid-state imaging device in which the dark current at the end of the element isolation layer is reduced.

Since the first semiconductor region is formed so that the lower portion thereof reaches the first semiconductor well region, the spread depth of the depletion layer can be increased. Therefore, a solid-state imaging device with reduced dark current and improved photoelectric conversion efficiency can be manufactured.

  In the method of manufacturing the solid-state imaging device, a second semiconductor well region is formed which is in contact with the lower portion of the first semiconductor region and has an end portion located inward from the end portion of the element isolation layer and reaches the first semiconductor well region. In some cases, the area of the high-resistance semiconductor region can be made larger than the area of the charge storage region. As the area of the high-resistance semiconductor region is increased, the photoelectric conversion efficiency is further improved, and a solid-state imaging device that improves both the photoelectric conversion efficiency and the dark current can be manufactured.

In the method of manufacturing the solid-state imaging device, the first conductivity type first semiconductor well region is formed at a required depth position of the second conductivity type semiconductor region, and the second conductivity separated by the first semiconductor well region is formed. When the charge storage region is formed on the surface of the region on the surface side of the mold semiconductor region, the high resistance semiconductor region is formed by the separated surface region, and the sensor part is formed, the depletion layer spread depth Can be increased. Therefore, a solid-state imaging device with reduced dark current and improved photoelectric conversion efficiency can be manufactured.

It is a block diagram which shows one Embodiment of the solid-state imaging device which concerns on this invention. It is a block diagram which shows the other example of the unit pixel applied to the solid-state imaging device of this invention. It is a block diagram which shows the other example of the unit pixel applied to the solid-state imaging device of this invention. It is sectional drawing of the principal part which shows one Embodiment of the sensor part of the solid-state imaging device which concerns on this invention. It is sectional drawing which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. It is sectional drawing which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. FIGS. 7A to 7D are manufacturing process diagrams of the sensor unit of FIGS. It is sectional drawing of the principal part which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. FIGS. 9A to 9C are manufacturing process diagrams of the sensor unit of FIG. D to E are manufacturing process diagrams of the sensor unit of FIG. It is a top view of the principal part which shows an example of the solid-state imaging device provided with the sensor part which concerns on A this invention. B is an equivalent circuit diagram of the unit pixel. It is sectional drawing on the BB line of FIG. 11 in the case of having the sensor part which concerns on FIG. 8 with which it uses for description of this invention. It is sectional drawing on the BB line of FIG. 11 in the case of having the sensor part which concerns on FIG. 6 with which it uses for description of this invention. FIGS. 8A to 8C are manufacturing process diagrams of a C-MOS transistor constituting a peripheral circuit of the solid-state imaging device. FIGS. It is sectional drawing of the principal part which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. It is sectional drawing which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. It is sectional drawing which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. It is sectional drawing which shows other embodiment of the sensor part of the solid-state imaging device which concerns on this invention. FIGS. 8A to 8B are manufacturing process diagrams of an example of a method for manufacturing a sensor part with trench elements separated according to the present invention. FIGS. FIGS. 8A to 8C are manufacturing process diagrams of another example of a method for manufacturing a sensor unit with trench elements separated according to the present invention. FIGS. FIGS. 8A to 8C are manufacturing process diagrams of another example of a method for manufacturing a sensor unit with trench elements separated according to the present invention. FIGS. It is sectional drawing of the principal part of the sensor part of the solid-state imaging device which concerns on a prior art example.

  FIG. 1 shows an example of the configuration of, for example, a C-MOS type solid-state imaging device according to an embodiment of the present invention.

The solid-state imaging device 10 includes a photodiode (that is, a pn junction type sensor unit) 11 that performs photoelectric conversion, a vertical selection switch element (for example, a MOS transistor) 13 that selects pixels, and a readout switch element (for example, a MOS transistor) 12. And an imaging region in which a plurality of unit pixels 14 are arranged in a matrix and a vertical selection line 15 to which a control electrode (so-called gate electrode) of a vertical selection switch element 13 is commonly connected for each row. A vertical scanning circuit 16 that outputs a scanning pulse φV [φV ₁ ,... ΦV _m ,... ΦV _{m + k} ,...], And a vertical line in which the main electrode of the read switch element 12 is connected in common to each column A signal line 17, a readout pulse line 18 connected to the main electrode of the vertical selection switch element 13 for each column, a vertical signal line 17, and a horizontal signal line 19 Connected to a horizontal switch element (for example, a MOS transistor) 20 to which the main electrode is connected, a control electrode (so-called gate electrode) of the horizontal switch element 20, a horizontal scanning circuit 21 connected to the readout pulse line 18, and a horizontal signal line 19. The amplifier 22 is configured.

  In each unit pixel 14, one main electrode of the readout switch element 12 is connected to the photodiode 11, and the other main electrode is connected to the vertical signal line 17. Also, one main electrode of the vertical selection switch element 13 is connected to a control electrode (so-called gate electrode) of the read switch element 12, and the other main electrode is connected to the read pulse line 18, and the control electrode (so-called so-called gate electrode). Gate electrode) is connected to the vertical selection line 15.

A horizontal scanning pulse φH [φH ₁ ,... ΦH _n , φH _{n + 1} ,...] Is supplied from the horizontal scanning circuit 21 to the control electrode (so-called gate electrode) of each horizontal switching element 20, and each readout pulse line 18 is supplied with horizontal readout pulses φH ^R [φH ^R ₁ ,... ΦH ^R _n , φH ^R _{n + 1} ,.

The basic operation of the solid-state imaging device 10 is as follows. The vertical selection switch element 13 that has received the vertical scanning pulse φV _m from the vertical scanning circuit 16 and the readout pulse φH ^R _n from the horizontal scanning circuit 21 generates a product pulse of these pulses φV _m and φH ^R _n. The control electrode of the read switch element 12 is controlled by the pulse of this product, and the signal charge photoelectrically converted by the photodiode 11 is read out to the vertical signal line 17. This signal charge is output to the horizontal signal line 19 through the horizontal switch element 20 controlled by the horizontal scanning pulse φH _n from the horizontal scanning circuit 21 during the horizontal video period, and is converted to a signal voltage by the amplifier 22 connected thereto. It is converted and output.

  Note that the configuration of the unit pixel 14 is not limited to the above example, and various configurations such as FIGS. In FIG. 2, the unit pixel 14 is composed of a readout MOS transistor 12 connected to the photodiode 11, and the other main electrode of the readout MOS transistor 12 is connected to the vertical signal line 17 and its gate. An electrode is connected to the vertical selection line.

  In FIG. 3, the unit pixel 14 includes a photodiode 11, a readout MOS transistor 21, an FD (floating diffusion) amplifier MOS transistor 22, an FD reset MOS transistor 23, and a vertical selection MOS transistor 24. . Then, one main electrode of the read MOS transistor 21 is connected to the photodiode 11 and the other main electrode is connected to one main electrode of the FD reset MOS transistor 23, and the other main electrode of the FD reset MOS transistor 23 is connected. The FD amplifier MOS transistor 22 is connected between the electrode and one main electrode of the vertical selection MOS transistor 24, and the gate electrode of the FD amplifier MOS transistor 22 is at the midpoint of connection between the read MOS transistor 21 and the FD reset MOS transistor 23. It is connected to a certain FD (floating diffusion) part. The gate electrode of the read MOS transistor 21 is connected to the vertical read line 25, the other main electrode of the FD reset MOS transistor 23 is connected to the power supply VDD, and its gate electrode is connected to the horizontal reset line 28 for vertical selection. The other main electrode of the MOS transistor 24 is connected to the vertical signal line 26, and its gate electrode is connected to the vertical selection line 27.

  FIG. 4 shows an embodiment of the sensor unit 11 in the solid-state imaging device 10. The sensor unit (photodiode) 111 according to the present embodiment forms a first semiconductor well region 32 of a first conductivity type, for example, a p-type, on a second conductivity type, for example, an n-type silicon semiconductor substrate 31, and this A high-resistance semiconductor region, for example, a low-concentration n-type semiconductor region 33 is formed on the first p-type semiconductor well region 32, and an element isolation layer (that is, a LOCOS layer) by selective oxidation formed so as to separate the sensor unit 111 from each other. ) 34, a second p-type semiconductor well region 35 reaching the first p-type semiconductor well region 32 is formed, and a high concentration is formed on the surface of the low-concentration n-type semiconductor region 33 partitioned by the element isolation layer 34. N-type semiconductor region 36 is formed, and a pn junction j is formed between the low-concentration n-type semiconductor region 33 and the first p-type semiconductor well region 32. During operation, the depletion layer of the sensor unit is the first depletion layer. p-type semiconductor well Configured to extend to pass 32.

Here, the first p-type semiconductor well region 32 is formed at a predetermined depth position of the substrate 31, and is divided into two by the first p-type semiconductor well region 32. An n-type semiconductor region 33 is formed. Further, the high-concentration n-type semiconductor region 36 becomes a substantial charge storage region. Note that a sensor structure in which a high-concentration p-type semiconductor region 38 is formed at the interface between the n-type semiconductor region 36 of the sensor unit 111 and the insulating film (for example, SiO ₂ film) 37 may be employed. The pn junction j of the sensor unit 111 is formed between the high-concentration n-type semiconductor region 36 and the high-concentration p-type semiconductor region 38, and between the low-concentration n-type semiconductor region 33 and the second p-type semiconductor well region 35. Also formed between.

  The second p-type semiconductor well region 35 can be formed simultaneously with the p-type semiconductor well in the C-MOS transistor of the peripheral circuit, for example. As shown in FIG. 14, in the C-MOS transistor, after forming a field insulating layer (so-called element isolation layer) 52 by selective oxidation on the upper surface of an n-type semiconductor substrate 51, one element is formed using the photoresist layer 53 as a mask. A p-type semiconductor well region 55 is formed by ion-implanting a p-type impurity 54 such as boron into the region (see FIG. 3A).

  Next, a gate electrode 57 made of, for example, polycrystalline silicon is formed on the p-type semiconductor well region 55 and the n-type semiconductor substrate 51, which is another element formation region, via a gate insulating film 56, respectively (see B in the same figure). . Next, n-type impurities are ion-implanted into the p-type semiconductor well region 55 by self-alignment using each gate electrode 57 as a mask to form an n-type source region 58S and a drain region 58D. Then, p-type impurities are ion-implanted into the n-type semiconductor substrate 51 to form a p-type source region 61S and a drain region 61D to form a p-channel MOS transistor 62, thereby obtaining a C-MOS transistor. A process in which the p-type semiconductor well region 55 is formed after the field insulating layer 52 is formed is called a retrograte p-well process.

  The second p-type semiconductor well region 35 in FIG. 4 described above can be formed simultaneously with the p-type semiconductor well region 55 in FIG. 14, and the depletion layer described later is deepened without increasing the number of manufacturing steps. Thus, the sensor unit 111 with improved photoelectric conversion efficiency can be formed. Also, as shown in FIG. 14, since the second p-type semiconductor well region 35 is formed after the element isolation layer 34 is formed, the second p-type semiconductor well is formed under the element isolation layer 34 except for the sensor formation region. The region 35 can be selectively formed without being affected by the diffusion caused by the heat treatment when forming the element isolation layer.

  According to the solid-state imaging device 10 having the sensor unit 111 according to the present embodiment, the second p-type semiconductor that selectively reaches the first p-type semiconductor well region 32 only under the element isolation layer 34 excluding the sensor region. A well region 35 is formed, and a high-concentration n-type semiconductor region 36, a low-concentration n-type semiconductor region 33, and a first p-type semiconductor well region 32 form a pn junction to form a photodiode, that is, a sensor unit 111. In the operation, the spreading depth of the depletion layer in the sensor unit 111 is increased, and the signal charge photoelectrically converted at a deep position can be stored in the n-type semiconductor region 36 serving as the charge storage region. . Therefore, the photoelectric conversion efficiency increases and a more sensitive solid-state imaging device can be obtained.

  FIG. 5 shows another embodiment of the sensor unit 11 (see FIG. 1) according to the present invention. The sensor unit (photodiode) 112 according to the present embodiment is intended to improve photoelectric conversion efficiency and reduce dark current due to leakage current. In the same manner as described above, the sensor unit 112 forms the first semiconductor well region 32 of the first conductivity type, for example, the p-type, on the semiconductor substrate 31 of the second conductivity type, for example, the n-type. A low-concentration n-type semiconductor region 33 is formed on the semiconductor well region 32, and a high-concentration n-type semiconductor region 36 is formed on the surface of the low-concentration n-type semiconductor region 33 separated by the element isolation layer 34 by selective oxidation. And a pn junction j is formed between the low-concentration n-type semiconductor region 33 and the first p-type semiconductor well region 32 so that the depletion layer of the sensor portion extends to the first semiconductor well region 32 during operation. Configured.

  In this embodiment, the second p-type semiconductor well region 351 reaching the first p-type semiconductor well region 32 is formed at the same time as the second p-type semiconductor well region 321 under the element isolation layer 34 for pixel separation. A part 351a of the p-type semiconductor well region 351 is formed to extend between the n-type semiconductor region 36 which becomes a substantial charge storage region of the sensor portion and the element isolation layer 34. That is, the p-type semiconductor well region 351 is formed so as to cover the end portion and the lower portion of the element isolation region 36 and to extend to the pixel region side, that is, the sensor portion side.

That is, the end of the second p-type semiconductor well region 351 is formed so as to exist on the sensor side away from the end of the element isolation layer 34, and the end of the n-type semiconductor region 36 that is the charge storage region of the sensor unit 112. The portion is in contact with the extension 351a of the second p-type semiconductor well region. The pn junction j of the sensor portion 112 is also formed between both the n-type semiconductor regions 33 and 36 and the extension portion 351a of the second p-type semiconductor well region.
Since the other configuration is the same as that described with reference to FIG. 4, the same reference numerals are given to the portions corresponding to FIG. 4 in FIG.

  7A to 7C show a method for manufacturing the sensor unit 112. First, as shown in FIG. 7A, after an element isolation layer 34 to be selectively oxidized is formed on the surface of an n-type semiconductor substrate 31, the edge of the element isolation layer 34 is covered so as to cover a region where the sensor portion of the substrate 31 is to be formed. A photoresist layer 41 having a predetermined pattern is formed on the side of the sensor part (on the active region of the photodiode) away from the part, and a p-type impurity 42 is ion-implanted using the photoresist layer 41 as a mask. Thus, a second p-type semiconductor well region 351 is formed. The second p-type semiconductor well region 351 is formed on the side of the region where the sensor portion where the end, that is, the end of the extended portion 351a is separated from the end of the element isolation layer 34 is to be formed.

  Next, as shown in FIG. 7B, after the photoresist layer 41 is peeled off, a p-type impurity 43 is ion-implanted over the entire surface of the region where the sensor portion is to be formed, including under the element isolation layer 34. A first p-type semiconductor well region 32 that is in contact with the lower portion of the second p-type semiconductor well region 351 is formed at a predetermined depth. By forming the first p-type semiconductor well region 32, the region surrounded by the first p-type semiconductor well region 32 and the second p-type semiconductor well region 351 is constituted by a separated part of the substrate 31. A low concentration n-type semiconductor region 33 is formed.

  Next, as shown in FIG. 7C, a photoresist layer 44 is formed on other portions other than the sensor portion formation region, n-type impurities 45 are ion-implanted, and charge is accumulated on the surface of the low-concentration n-type semiconductor region 33. A high-concentration n-type semiconductor region 36 to be a region is formed. A pn junction j is formed between the n-type semiconductor region 33 and the first semiconductor well region 32, and between the n-type semiconductor regions 36 and 33 and the extension 351a of the second p-type semiconductor well region. The target photodiode thus formed, that is, the sensor unit 112 is formed.

  Here, the impurity concentration of each region is as follows. Second semiconductor well region 351> n-type semiconductor region 36. n-type semiconductor region 36> n-type semiconductor region 33.

  According to the solid-state imaging device according to the present embodiment including the sensor unit 112 described above, the second p-type semiconductor well region (so-called channel stop region) 351 is disposed closer to the sensor unit than the end of the element isolation layer 34. By extending the structure, the pn junction of the photodiode forming the sensor portion 112 can be separated from the end of the element isolation layer 34 where crystal defects such as dislocations exist, that is, the semiconductor region near the end of the element isolation layer 34. In addition, when a reverse bias is applied to the pn junction, the depletion layer can be generated at a position away from the end of the element isolation layer 34. Therefore, the generation of leakage current near the end of the element isolation layer 34 is suppressed, and the dark current is reduced.

  Further, in the sensor unit 112, as in the above-described FIG. 4, one of the n-type semiconductor regions constituting the photodiode is formed by the regions 36 and 33 by the second semiconductor well region 351, and the depletion layer expands. The depth is increased and the photoelectric conversion efficiency can be increased. Therefore, a dark current is reduced and a highly sensitive solid-state imaging device can be obtained.

  7A to 7C, since the second p-type semiconductor well region 351 is formed by ion implantation after the element isolation layer 34 is formed, the influence of the heat treatment at the time of forming the element isolation layer 34 is affected. In other words, the second p-type semiconductor well region 351 can be formed with high positional accuracy without being re-diffused. Further, when forming the second p-type semiconductor well region 351 having the extension 351a on the sensor part side away from the end of the element isolation layer 34, alignment with the element isolation layer 34 is facilitated, and the second The p-type semiconductor well region 351 can be formed easily and accurately. In the present embodiment, the second p-type semiconductor well region 351 can be formed simultaneously with the p-type well region 55 in manufacturing the C-MOS transistor of the peripheral circuit shown in FIG. The number does not increase.

  FIG. 6 shows another embodiment of the sensor unit 11 (see FIG. 1) according to the present invention. The sensor unit (photodiode) 113 according to the present embodiment is similar to the sensor structure of FIG. 5 described above, and further includes a second portion between the n-type semiconductor region 36 serving as the charge storage region and the insulating film 37 on the surface. A high-concentration p-type semiconductor region 38 is formed so as to be in contact with the p-type semiconductor well region 351. Since other configurations are the same as those in FIG. 5, the corresponding portions are denoted by the same reference numerals, and redundant description is omitted.

  In the sensor unit 113, after the n-type semiconductor region 36 of FIG. 7C is formed by ion implantation, as shown in FIG. 7D, p-type impurities 46 are further ion-implanted to form p on the surface of the n-type semiconductor region 36. It can be manufactured by forming the type semiconductor region 38.

According to the solid-state imaging device including the sensor unit 113 according to the present embodiment, the sensor structure further includes the p-type semiconductor region 38 on the surface of the n-type semiconductor region 36. All pn junctions other than the gate end of the transistor can be provided in the bulk. That is, in this sensor unit 113, in addition to the effect of the sensor unit 112 of FIG. 5, the depletion layer is further away from the interface with the insulating film 37 on the surface of the sensor unit, and hence from the Si-SiO ₂ interface. The dark current can be further reduced.

  FIG. 8 shows another embodiment of the sensor unit 11 (see FIG. 1) according to the present invention. In the sensor unit (photodiode) 114 according to the present embodiment, the first conductivity type, for example, the p-type first semiconductor well region 32 is formed on the second conductivity type, for example, the n-type semiconductor substrate 31, in the same manner as described above. Then, a low-concentration n-type semiconductor region 33 is formed on the first p-type semiconductor well region 32, and is formed on the surface of the low-concentration n-type semiconductor region 33 separated by the element isolation layer 34 by selective oxidation. A high-concentration n-type semiconductor region 36 is formed, and a pn junction j is formed between the low-concentration n-type semiconductor region 33 and the first p-type semiconductor well region 32. 1 p-type semiconductor well region 32.

  In this embodiment, in particular, the first p-type semiconductor well region 32 is reached by having an end 352a inward from the end of the element isolation layer 34 under the element isolation layer 34 for pixel isolation. A second p-type semiconductor well region 352 is formed, and a p-type semiconductor region, a so-called p-type plug, is formed between the end of the element isolation layer 34 and the n-type semiconductor region 36 serving as a charge storage region of the sensor unit 114. A region 39 is formed and configured. The p-type plug region 39 is formed so as to be connected to the second p-type semiconductor well region 352. Further, in FIG. 8, a high-concentration p-type semiconductor region 38 is formed on the surface of the n-type semiconductor region 36 so that a part thereof is in contact with the p-type plug region 39. The pn junction j of the sensor unit 114 is also formed between the n-type semiconductor regions 36 and 33, the p-type semiconductor region 38, the second p-type semiconductor well region 352, and the p-type plug region 39.

  9 and 10 show a method for manufacturing the sensor unit 114. First, as shown in FIG. 9A, after an element isolation layer 34 is formed by selective oxidation on the surface of an n-type semiconductor substrate 31, an end portion 64a is formed on the element isolation layer 34 so as to cover a region where a sensor portion is to be formed. A second p-type semiconductor well region 352 is formed by ion-implanting p-type impurities 42 using the photoresist layer 64 as a mask. The second p-type region well region 352 is formed such that the end portion 352a is located inward from the end portion of the element isolation layer. The second p-type semiconductor well region 352 is formed at the same time as the p-type semiconductor well region 55 of the C-MOS transistor in the peripheral circuit, as described above.

  Next, as shown in FIG. 9B, after the photoresist layer 64 is peeled off, a p-type impurity 43 is ion-implanted into the entire surface of the region where the sensor portion is to be formed, including under the element isolation layer 34, so that the substrate 31 has a predetermined depth. A first p-type semiconductor well region 32 that is in contact with the lower portion of the second p-type semiconductor well region 352 is formed at this position. By the formation of the first p-type semiconductor well region 32, a region surrounded by the first p-type semiconductor well region 32 and the second p-type semiconductor well region 352 is constituted by a separated part of the substrate 31. A low concentration n-type semiconductor region 33 is formed.

  Next, as shown in FIG. 9C, the end portion 65a covers the region where the sensor portion is to be formed, and the end portion 65a is on the sensor portion side (on the active region of the photodiode) away from the end portion of the element isolation layer 34. A photoresist layer 65 having a predetermined pattern is formed, and the p-type plug region 39 is formed by ion-implanting p-type impurities 66 using the photoresist layer 65 as a mask. The p-type plug region 39 is formed so that the end thereof exists on the sensor portion forming region side away from the end portion of the element isolation layer 34, that is, protrudes from the end of the element isolation layer 34 toward the sensor portion forming region side.

  Next, as shown in FIG. 10D, a photoresist layer 44 is formed on the other part than the sensor part formation region, and n-type impurity 45 is ion-implanted to charge the surface of the low-concentration n-type semiconductor region 33. A high-concentration n-type semiconductor region 36 serving as a storage region is formed.

  Subsequently, as shown in FIG. 10E, a p-type impurity 46 is ion-implanted to form a high-concentration p-type semiconductor region 38 in contact with the p-type plug region 39 on the surface of the n-type semiconductor region 36. In this manner, the target photodiode, that is, the sensor unit 114, in which the main pn junction j is formed by the n-type semiconductor regions 36 and 33 and the first p-type semiconductor well region 32, is obtained.

  Here, the impurity concentration of each region is as follows. p-type semiconductor region 38> n-type semiconductor region 36. p-type semiconductor well region 352> n-type semiconductor region 33. p-type plug region 39> n-type semiconductor region 36.

  According to the solid-state imaging device including the sensor unit 114 according to the present embodiment, the p-type is provided between the end portion of the element isolation layer 34 by selective oxidation and the n-type semiconductor region 36 serving as the charge accumulation region of the sensor unit 114. By forming the plug region (which becomes a channel stop region) 39, the pn junction of the photodiode constituting the sensor unit 114 is connected to the end of the element isolation layer 34 where crystal defects such as dislocation exist, that is, near the end of the element isolation layer 34. The depletion layer can be generated at a position away from the element isolation layer 34 when a reverse bias is applied to the pn junction. Further, as shown in FIG. 8, since the p-type semiconductor well region 352 is formed inside the end portion of the element isolation layer 34, the width of the high-resistance semiconductor region 33 is substantially larger than the width of the charge storage region 36. As a result, the area of the high-resistance semiconductor region 33 is larger than the area of the charge storage region 36, whereby the photoelectric conversion efficiency in the sensor unit 114 is further improved. Therefore, it is possible to suppress the occurrence of a leak current near the end of the element isolation layer 34 and reduce the dark current. At the same time, the spreading depth of the depletion layer is increased at the same time as described above, and the photoelectric conversion efficiency can be increased.

  A second p-type semiconductor well region 352 is formed inward of the element isolation layer 34, and a p-type plug region 39 is formed between the end of the element isolation layer 34 and the n-type semiconductor region 36 of the sensor unit 114. When the formed configuration is used, the distance between the gate end of the read MOS transistor and the end of the p-type plug region 39 can be set more accurately.

  That is, the sensor structure of FIG. 8 is compared with the sensor structure of FIG. When the cross-sectional structure of the sensor unit 114 in FIG. 8 and the cross-sectional structure of the sensor unit 113 in FIG. 6 are respectively the cross-sectional structures on the AA line of the plan view showing the main part of the imaging region in FIG. The cross-sectional structure on the BB line passing over the gate electrode 71 of the MOS transistor is as shown in FIG. 12 in the case of the sensor unit 114 and as shown in FIG. 13 in the case of the sensor unit 113. FIG. 11B shows an equivalent circuit of the unit pixel in FIG. 11A. In the plan view of FIG. 11A, the hatched portion indicates the element isolation layer 34 by selective oxidation, and 34a indicates the end of the element isolation layer. The reversely hatched portion indicates the extension 351 a or the p-type plug region 39 of the second p-type semiconductor well region 351. Reference numeral 12 denotes a read MOS transistor, and 71 denotes a read gate electrode formed in an L shape. A vertical selection MOS transistor 13 has a gate electrode connected to the vertical selection line 15. Reference numerals 171 to 174 denote contact portions. The vertical signal line 17 and one source / drain region 73 constituting the readout MOS transistor 12 are connected by a contact portion 171, and a gate electrode 71 is connected to a wiring (for example, Al wiring) and contact portions 172 and 173 not shown. And is connected to one source / drain region of the vertical selection MOS transistor 13. The other source / drain region of the vertical selection MOS transistor 13 is connected to the read pulse line 18 via the contact portion 174.

In the cross-sectional structures of FIGS. 12 and 13, a low-concentration p-type impurity is introduced into the channel region 72 immediately below the gate electrode 71 constituting the read MOS transistor 12. 77 denotes a gate insulating film by SiO ₂ or the like, 74 denotes a side wall by SiO ₂ or the like.

  In the case of the configuration of the sensor unit 112, as shown in FIG. 13, since the ion implantation process in which the shape does not remain, that is, the ion implantation process of the second p-type semiconductor well region 351 is performed first, Then, the second p-type semiconductor well region 351 is aligned with the mask, and the gate electrode 71 is aligned with the element isolation layer 34 to form the second p-type semiconductor well region 351 and the gate electrode 71, respectively. For this reason, the second semiconductor well region 351 and the gate electrode 71 cannot be directly aligned.

That is, as shown in FIG. 13, the mask alignment in forming the second p-type semiconductor well region 351 and the gate electrode 71 is performed with the end portion of the element isolation layer 34 remaining in the shape as the reference point p. In addition, variations due to misalignment occur in the respective distances d ₁ and d ₂ , and the accuracy of the distance D ₁ between the gate electrode 71 and the second p-type semiconductor well region 351 requiring accuracy decreases, and the characteristics between lots are reduced. There is a possibility that the variation becomes large.

On the other hand, in the case of the configuration of the sensor unit 114, as shown in FIG. 12, after the read gate electrode 71 is formed, the p-type plug region 39 is formed by ion implantation with reference to the end Q of the gate electrode 71. The mask alignment accuracy between the gate electrode 71 and the p-type plug region 39 is improved, and the accuracy of the distance D ₂ between the gate electrode 71 and the p-type plug region 39 is improved. Thereby, an alignment margin can be reduced and the opening area of a sensor part can be expanded. In addition, variation in characteristics between lots can be reduced.

  8 and 12, the p-type semiconductor region 38 is formed on the surface of the n-type semiconductor region 36, and all the pn junctions other than the gate end are provided in the bulk. Although further reduction is intended, in addition, the p-type semiconductor region 38 may be omitted.

  FIG. 15 shows still another embodiment of the sensor 11 (see FIG. 1) according to the present invention. In the sensor unit 115 according to the present embodiment, the first conductivity type, for example, the p-type semiconductor well region 81 is formed on the second conductivity type, for example, the n-type semiconductor substrate 31, and then the element isolation layer 34 is formed by selective oxidation. Then, an n-type semiconductor region 82 serving as a charge storage region is formed in the device-isolated region, and a pn junction is formed between the n-type semiconductor region 82 and the p-type semiconductor well region 81 to form a photodiode. The p-type plug region 39 is formed between the n-type semiconductor region 82 and the end of the element isolation layer 34 so as to cover the end and lower portion of the element isolation layer 34. The sensor unit 115 has a configuration in which a p-type plug region 39 is added to the configuration shown in FIG.

  Also in the solid-state imaging device including the sensor unit 115, the leak current at the end of the element isolation layer 34 is suppressed by forming the p-type plug region 39 between the n-type semiconductor region 82 and the element isolation layer 34. The dark current can be reduced.

  Each of the above-described embodiments is a case where the insulating layer 34 by selective oxidation is used as the element isolation layer of the solid-state imaging device.

  The present invention can also be applied to a solid-state imaging device using an element isolation layer by trench isolation, so-called STI (Shallow Trench Isolation), as the element isolation layer. In the trench element isolation, pixels can be miniaturized and highly integrated compared to element isolation by selective oxidation.

  Next, an embodiment applied to a solid-state imaging device using trench element isolation will be described with reference to FIGS.

FIG. 16 shows another embodiment of the sensor unit 11 in the solid-state imaging device 10 described above. The sensor unit (photodiode) 116 according to the present embodiment includes a second conductive type, for example, an n-type semiconductor substrate 31, and a trench 91 for isolation of pixels and an insulating layer such as a SiO ₂ film embedded in the trench 91. In the same manner as described above, the first p-type semiconductor well region 32 and the low-concentration n-type semiconductor region 33 are formed in the pixel region of the n-type semiconductor substrate 31. Then, an n-type semiconductor region 36 serving as a charge storage region thereon and a high-concentration p-type semiconductor region 38 between the surface and the insulating film 37 are sequentially formed.

  In the present embodiment, in particular, the second p-type semiconductor well region 94 reaching the first p-type semiconductor well region 32 is formed so as to exclude the sensor unit 116 side, and the second p-type semiconductor is formed. A part of the well region 94 is formed so as to extend toward the sensor portion 116 side of the pixel region so as to surround the interface of the groove 91 of the trench element isolation region 93 for pixel separation.

  In this example, the trench 91 is formed to a depth that reaches the low-concentration n-type semiconductor region 33. The first p-type semiconductor well region 32 is formed so as to terminate at a portion corresponding to the second p-type semiconductor well region 94 below the trench element isolation layer 93. The second p-type semiconductor well region 94 is formed with a uniform depth in each part with the groove 93 formed.

FIG. 17 shows another embodiment of the sensor unit 11 (see FIG. 1) according to the present invention. Similar to the above, the sensor unit (photodiode) 117 according to the present embodiment has a second conductive type, for example, an n-type semiconductor substrate 31 and a groove 91 for pixel separation, for example, SiO embedded in the groove 91. A trench element isolation layer 93 is formed by an insulating layer 92 such as ₂ , and a first p-type semiconductor well region 32 and a low-concentration n-type semiconductor region above the pixel region of the n-type semiconductor substrate 31 are formed. 33, an n-type semiconductor region 36 serving as a charge storage region thereon, and a high-concentration p-type semiconductor region 38 between the surface and the insulating film 37 are sequentially formed.

  In the present embodiment, in particular, the second p-type semiconductor well region 94 reaching the first p-type semiconductor well region 32 is formed so as to exclude the sensor portion 117 side, and this second p-type is formed. A part of the semiconductor well region 94 is formed so as to extend to the sensor portion 117 side of the pixel region so as to surround the interface of the groove 91 of the trench element isolation layer 93. In this example, the first p-type semiconductor well region 32 is formed over the entire region, and the trench 91 of the trench element isolation layer 93 is formed so as to reach the first p-type semiconductor well region 32. The bottom and sides of the trench 91 are surrounded by the first and second p-type semiconductor well regions 32 and 94.

FIG. 18 shows another embodiment of the sensor unit 11 (see FIG. 1) according to the present invention. As described above, the sensor unit (photodiode) 118 according to the present embodiment has a second conductive type, for example, an n-type semiconductor substrate 31 and a groove 91 for pixel separation, for example, SiO embedded in the groove 91. A trench element isolation layer 93 is formed by the insulating layer 92 such as ₂ , a high-concentration p-type plug region 95 is formed at the interface of the groove 91, and the first p-type is formed in the pixel region of the n-type semiconductor substrate 31. A semiconductor well region 32, a low-concentration n-type semiconductor region 33 thereon, a charge storage region 36 thereon, and a high-concentration p-type semiconductor region 38 between the surface and the insulating film 37 are sequentially formed. Configured. The high-concentration p-type plug region 95 surrounds all of the insulating layer 92 in the trench portion and the silicon (Si) interface.

  In the present embodiment, in particular, the second p-type semiconductor well region 94 reaching the first p-type semiconductor well region 32 is formed so as to exclude the sensor 118 side, and this second p-type semiconductor is formed. A part of the region 94 is formed so as to extend to the sensor portion 118 side of the pixel region so as to surround the interface of the groove 91 of the trench element isolation layer 93. In this example, the trench 91 is formed so as to reach the n-type semiconductor substrate 31, and the first p-type semiconductor well region 32 is formed over the entire area. The entire periphery of the side portion of the trench 91 is surrounded by the first and second p-type semiconductor well regions 32 and 94.

  19 to 21 show a manufacturing method for realizing the above-described sensor units 116, 117, and 118, respectively.

A manufacturing example of FIG. 19 will be described. First, as shown in FIG. 19A, an insulating film 37 made of, for example, SiO ₂ or the like is formed on the surface of an n-type semiconductor substrate 31, and a trench separating groove 91 is formed in the semiconductor substrate 31 together with the insulating film 37. . Next, a resist mask 97 is formed in the active region, that is, the pixel region separated by the groove 91 so as to be separated from the edge of the groove 91 by a predetermined distance d ₁ , and p-type impurities are ionized through the resist mask 97. A second p-type semiconductor region 94 is formed in the semiconductor substrate 31 so as to be implanted and project from the partial groove 91 to the pixel region side.

  At this time, the second p-type semiconductor region 94 is formed with a sufficient width and depth over the side and bottom of the groove 91 and is formed so as to surround all the interfaces of the side and bottom of the groove 91.

Next, as shown in FIG. 19B, an insulating film, for example, a SiO ₂ film 92 is buried in the trench 91 by, for example, a CVD (chemical vapor deposition) method, and is planarized, so that trench elements are separated by the trench 91 and the buried insulating film 92. Layer 93 is formed. Thereafter, a resist mask 99 is formed so that the termination is on the trench element isolation layer 93 except for the pixel region, and p-type and n-type impurities are selectively implanted into the pixel region via the resist mask 99, respectively. Then, the first p-type semiconductor well region 32 connected to the second p-type semiconductor well region 94 is formed at a deep position of the substrate 31, and the n-type semiconductor region 36 serving as a charge storage region is formed on the surface side of the substrate 31. Further, a high-concentration p-type semiconductor region 38 is formed at the interface between the n-type semiconductor region 36 and the insulating film 37 so as to be connected to the second p-type semiconductor well region 94. A portion of the substrate 31 between the n-type semiconductor region 36 on the front side and the first p-type semiconductor well region 32 becomes a low-concentration n-type semiconductor region 33.

  Here, the ion implantation of the first p-type semiconductor well region 32, the n-type semiconductor region 36, and the high-concentration p-type semiconductor region 38 is shown in one figure, but this is for the convenience of forming other parts. In some cases, it is a separate process.

  In this way, a target sensor unit is formed. This sensor portion is configured as a so-called HAD (Hole Accumulation Diode) sensor by the high-concentration p-type semiconductor region 38, the n-semiconductor regions 36 and 33, and the first p-type semiconductor well region 32.

A manufacturing example of FIG. 20 will be described. First, as shown in FIG. 20A, an insulating film 37 made of, for example, SiO ₂ is formed on the surface of an n-type semiconductor substrate 31, and a trench isolation trench 91 is formed in the semiconductor substrate 31 together with the insulating film 37. . Next, a resist mask 101 is formed on the entire surface of the other part except for the groove 91 and a region part away from the edge of the groove 91 by a required distance d ₂ , and p-type impurities are ion-implanted through the resist mask 101. Then, a high-concentration p-type semiconductor layer, that is, a so-called p-type semiconductor plug layer 95 is formed to succeed the first p-type semiconductor well region 32 and the second p-type semiconductor well region 32 to be formed later. The p-type semiconductor plug layer 95 is formed over the side and bottom of the groove 91 so as to surround the groove 91.

Next, as shown in FIG. 20B, an insulating film, for example, a SiO ₂ film 92 is buried in the trench 91 by, for example, a CVD (chemical vapor deposition) method, and planarized, and trench elements are separated by the trench 91 and the buried insulating film 92. Layer 93 is formed. Thereafter, a resist mask 103 is formed so that the termination is present on the trench isolation layer 93 except for the pixel region, and p-type and n-type impurities are selectively implanted into the pixel region through the resist mask 103, respectively. Then, the first p-type semiconductor well region 32 connected to the p-type semiconductor plug layer 95 is formed at a deep position of the substrate 31, and the n-type semiconductor region 36 serving as a charge storage region is formed on the surface side of the substrate 31. Further, a high-concentration p-type semiconductor region 38 connected to the p-type plug region 95 is formed at the interface between the n-type semiconductor region 36 and the insulating film 37. A portion of the substrate 31 between the n-type semiconductor region 36 on the front side and the first p-type semiconductor well region 32 becomes a low-concentration n-type semiconductor region 33.

  Here, the ion implantation of the first p-type semiconductor well region 32, the n-type semiconductor region 36, and the high-concentration p-type semiconductor region 38 is shown in one figure, but this is for the convenience of forming other parts. In some cases, it is a separate process.

Next, as shown in FIG. 20C, a resist mask 104 is formed in the pixel region so as to be separated from the edge of the groove 91 of the trench isolation layer 93 by a predetermined distance d ₁ beyond the p-type flag region 95. P-type impurities are ion-implanted through the resist mask 104 to form a second p-type semiconductor region 94 so as to protrude partially from the trench element isolation layer 93 to the pixel region side. The first p-type semiconductor well region 32 and the second p-type semiconductor well region 94 are connected to each other through a p-type plug region 95. In this way, a target sensor unit is formed.

A manufacturing example of FIG. 21 will be described. First, as shown in FIG. 21A, an insulating film 37 made of, for example, SiO ₂ is formed on the surface of the n-type semiconductor substrate 31, and a trench isolation trench 91 is formed in the semiconductor substrate 31 together with the insulating film 37. . Next, an insulating film, for example, a SiO ₂ film 92 is embedded in the trench 91 by, for example, a CVD (chemical vapor deposition) method, and planarized to form a trench element isolation layer 93 by the trench 91 and the embedded insulating film 92. Thereafter, a resist mask 105 is formed except for the pixel region separated by the trench element isolation layer 93, and ions are selectively implanted into the pixel region via the resist mask 105 to accumulate charges on the surface side of the substrate 31. An n-type semiconductor region 38 to be a region is formed, and a high-concentration p-type semiconductor region 38 is formed on the surface of the n-type semiconductor region 38.

  Here, although the ion implantation of the n-type semiconductor region 36 and the high-concentration p-type semiconductor region 38 is shown in one drawing, this may be a separate process for the convenience of forming other parts.

Next, as shown in FIG. 21B, a resist mask 106 is formed in the pixel region so as to be separated from the edge of the groove 91 of the trench isolation layer 93 by a predetermined distance d ₁ , and the p-type is formed through the resist mask 106. Impurities are ion-implanted to form a second p-type semiconductor region well region 94 so as to partially protrude from the trench element isolation layer 93 to the pixel region side.

  Next, as shown in FIG. 21C, the first p-type semiconductor well region 32 connected to the lower portion of the second p-type semiconductor well region 94 is implanted deeply into the substrate 31 by ion implantation of p-type impurities throughout the region. Form. The portion of the substrate 31 between the n-type semiconductor region 36 on the front side and the first p-type semiconductor well region 32 becomes a low-concentration n-type semiconductor region 33. In this way, a target sensor unit is formed.

The above-described sensor unit 116 in FIG. 16 can be manufactured by, for example, the manufacturing example in FIG. 19 and the manufacturing example in FIG. That is, when the bottom of the second p-type semiconductor well region 94 is shallower than the first p-type semiconductor well region 32 and the n ^- semiconductor region 33 is formed between the first and second p-type semiconductor well regions 94, In order to connect 32 and 94, it can be fabricated using ion implantation in FIG. 19 and plug ion implantation in FIG. The above-described sensor unit 117 of FIG. 17 can be manufactured by the manufacturing example of FIG. The above-described sensor unit 118 in FIG. 18 can be manufactured, for example, by the manufacturing example in FIG.

  According to the above-described solid-state imaging device including the sensor units 116, 117, and 118, the p-type semiconductor region 94 or 94 extends from the trench element isolation layer 93 to the n-type semiconductor regions 33, 36 side of the sensor unit. 95 is formed. That is, the semiconductor interface with the trench element isolation layer 93 that isolates the sensor portion (photodiode) 116, 117, or 118 is a p-type semiconductor region, for example, the second semiconductor well region 94, or the first and second semiconductor well regions. 32 or 94, or a p-type plug region 95, a second semiconductor well region 94, and the like.

  Crystal defects such as dislocations are present at the semiconductor interface with the trench element isolation layer 93. The interface where the crystal defects exist is a p-type having a conductivity type opposite to that of the n-type semiconductor region 36 which is the charge storage region of the sensor unit. It will be taken into the type semiconductor region.

  With such a configuration, the pn junction of the photodiode constituting the sensor unit 116, 117, or 118 can be separated from the interface of the trench element isolation layer 93 where crystal defects such as dislocations that cause leakage current are present. When the reverse bias is applied to the pn junction, the interface of the trench element isolation layer 93 and its vicinity can be prevented from being depleted. Therefore, the generation of leakage current from this interface and its vicinity can be suppressed, and dark current can be reduced.

  When the sensor unit is a so-called HAD sensor in which the p-type semiconductor region 38 is formed on the surface of the n-type semiconductor region 36, all the pn junctions other than the gate end are provided in the bulk, and the dark current is further reduced. be able to.

  In the above-described embodiment, the case where the present invention is applied to a C-MOS type solid-state imaging device has been described. However, the present invention can also be applied to a MOS-type solid-state imaging device.

  DESCRIPTION OF SYMBOLS 10 ... C-MOS type solid-state imaging device, 11, 111, 112, 113, 114, 115 ... Sensor part (photodiode), 12 ... Read-out switch element (MOS transistor), 13 ... Vertical selection switch Element (MOS transistor), 14... Unit pixel, 31... N-type semiconductor substrate, 32... First p-type semiconductor well region, 33. LOCOS layer) 35, 351, 352... Second p-type semiconductor well region, 36... N-type semiconductor region serving as a charge storage region, 38... P-type semiconductor region, 39. ...... Reading MOS transistor gate electrode, 91, groove, 92, insulating film, 93, trench element isolation layer, 94, second p-type semiconductor well region, 95, p-type plug Pass

Claims (8)

A first conductivity type first semiconductor well region formed in the second conductivity type semiconductor region;
A high resistance semiconductor region formed on the first semiconductor well region;
A sensor unit having a second conductivity type charge storage region formed on a surface of the high resistance semiconductor region, wherein the high resistance semiconductor region has a specific resistance higher than a specific resistance of the charge storage region ;
An element isolation layer by selective oxidation for pixel separation of the sensor unit;
A solid-state imaging having said element isolation layer end and reaches the first semiconductor well region I covering the bottom of, and the charge storage region and the first semiconductor region of a first conductivity type in contact with the high resistance semiconductor region apparatus. A first semiconductor region of the first conductivity type;
A semiconductor region portion of a first conductivity type that covers an end portion and a lower portion of the element isolation layer and is in contact with the charge storage region;
The first conductive type region and the first semiconductor well region are formed between the first semiconductor well region and in contact with the high-resistance semiconductor region so that the end portion is located inside the end portion of the element isolation layer. The solid-state imaging device according to claim 1, further comprising a second semiconductor well region of one conductivity type. The solid-state imaging device according to claim 1, wherein the first conductive type first semiconductor region is formed of a first conductive type second semiconductor well region . The first semiconductor well region is formed at a required depth position of the second conductivity type semiconductor region;
The high-resistance semiconductor region is formed by a region on the surface side separated by the first semiconductor well region of the semiconductor region of the second conductivity type.
The solid-state imaging device according to claim 2 or 3. Forming a device isolation layer by selective oxidation for pixel separation in a semiconductor region of the second conductivity type;
After formation of the isolation layer, the ion implantation by not covering the ends and bottom of the device isolation layer, a first conductivity type to reach the region for forming a first semiconductor well region of a first conductivity type lower 1 forming a semiconductor region;
Forming a first semiconductor well region of a first conductivity type;
The first conductivity type semiconductor region formed on the first semiconductor well region and the first conductivity type semiconductor region in the second conductivity type semiconductor region separated by the element isolation layer. A high-resistance semiconductor region in contact with the first conductive type and a second conductive type charge storage region formed on the surface of the high-resistance semiconductor region and in contact with the first conductive type first semiconductor region. Forming a sensor unit having a specific resistance higher than that of the accumulation region . A first semiconductor region of the first conductivity type;
A first conductivity type region portion covering an end portion and a lower portion of the element isolation layer and in contact with the charge accumulation region;
A first conductive layer formed between the first conductive type region and the first semiconductor well region, in contact with the high-resistance semiconductor region , with an end located inside an end of the element isolation layer ; 6. The method of manufacturing a solid-state imaging device according to claim 5, wherein the method is formed by a second semiconductor well region of a mold . 6. The method of manufacturing a solid-state imaging device according to claim 5, wherein the first conductive type first semiconductor region is formed by a first conductive type second semiconductor well region . Forming a first conductivity type first semiconductor well region at a required depth position of the second conductivity type semiconductor region;
Wherein the said second conductivity type the first of said charge storage region of the second conductivity type in the surface region of the separated surface side in the semiconductor well region of the semiconductor region is formed of, the separated surface region The method for manufacturing a solid-state imaging device according to claim 6 , further comprising: forming a high-resistance semiconductor region.

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