JP4303246B2 - Semiconductor photo detector - Google Patents

Description

  The present invention relates to a semiconductor light receiving device, and in particular, a semiconductor in which a MISFET (metal / insulator / semiconductor field effect transistor) is connected to one terminal of a photodiode, and the photodiode can be initialized by conducting the MISFET. The present invention relates to a light receiving device.

  In addition to the conventional CCD solid-state imaging device, a CMOS solid-state imaging device has been proposed. Features of the CMOS type solid-state imaging device include a single power source, low voltage driving, and low power consumption. In general, a CMOS solid-state imaging device includes a three-transistor type in which one pixel (pixel) includes three transistors and one photodiode, and one pixel includes four transistors and one photodiode. And 4-transistor type.

  In the three-transistor solid-state imaging device, one pixel includes a reset transistor, a source follower transistor, and a select transistor. The reset transistor initializes the photodiode to a reset voltage. The source follower transistor has a gate electrode connected to the photodiode, and is controlled by a voltage generated in the photodiode. The select transistor is connected in series with the source follower transistor, and performs switching of signal readout of the pixel. In the 4-transistor solid-state imaging device, a transfer transistor is inserted between the photodiode of each pixel of the 3-transistor solid-state imaging device and the gate electrode of the source follower transistor.

  In any solid-state imaging device, at the time of imaging, the reset transistor is first turned on, and the N-type layer of the photodiode is initially set to a reference voltage (reset voltage). Thereafter, light is received by the photodiode for a certain period. By receiving light, electrons are accumulated in the N-type layer of the photodiode, and the voltage of the N-type layer decreases. This voltage change is detected by the source follower transistor and output through the select transistor.

  The voltage change of the N-type layer of the photodiode depends on the junction capacitance of the photodiode, and the voltage change is larger as the junction capacitance is smaller. Therefore, the light receiving sensitivity can be improved by reducing the junction capacitance of the photodiode.

FIG. 15A shows a cross-sectional view of a photodiode and a reset transistor of a conventional CMOS solid-state imaging device using an N ⁺ P type photodiode. A field oxide film 201 is formed on the surface of the P-type silicon substrate 200 to define an active region. The field oxide film 201 is disposed in the P-type well 205. An N-type layer 202 is formed on a part of the surface layer of the active region. The outer periphery of a part of the N-type layer 202 is in contact with the field oxide film 201. A P-type well 203 is formed in a region of the active region where the N-type layer 202 is not formed. An N-channel reset transistor 204 is formed in the P-type well 203.

  The reset transistor 204 includes a source region 204S and a drain region 204D disposed on both sides of the channel region, and a gate electrode 204G formed on the channel region via a gate insulating film. The source region 204S is in contact with the N-type layer 202. A reset voltage VR is applied to the drain region 204D of the reset transistor 204. The source region 204S is connected to the gate electrode of the source follower transistor.

  A depletion layer spreads under the N-type layer 202. When light enters from the upper surface of the silicon substrate 200 through the N-type layer 202 to the depletion layer, electron-hole pairs are generated in the depletion layer, and electrons are accumulated in the N-type layer 202. Thus, photoelectric conversion is performed by the light transmitted through the N-type layer 202. Since short-wavelength light is easily absorbed by the N-type layer 202, sensitivity to short-wavelength light is lower than sensitivity to long-wavelength light.

  As shown in FIG. 15B, when the N-type layer 202 is thin, absorption of light having a short wavelength is reduced, and sensitivity can be increased. However, when the N-type layer 202 is thinned, the depletion layer formed thereunder is likely to come into contact with the shallow portion of the bottom surface of the field oxide film 201 at the boundary P between the active region and the surrounding field oxide film 201. . The shallow portion of the bottom surface of the field oxide film 201 is a portion where stress is concentrated during local oxidation of the silicon substrate. Since the depletion layer comes into contact with this portion, the leakage current increases.

FIG. 16A shows a cross-sectional view of a photodiode and a reset transistor of a conventional CMOS solid-state imaging device using a P ⁺ NP type photodiode, and FIG. 16B shows a plan view thereof. A cross-sectional view along dashed-dotted line A14-A14 in FIG. 16B corresponds to FIG. Hereinafter, differences from the solid-state imaging device illustrated in FIG.

A P ⁺ -type layer 210 is formed on a part of the surface layer portion of the active region surrounded by the field oxide film 201, and an N-type layer 211 is formed thereunder. The N-type layer 211 is in contact with the source region 204S of the reset transistor 204. A depletion layer is formed at the interface between the N-type layer 211 and the P ⁺ -type layer 210 and below the N-type layer 211. Since the N-type layer 211 is not exposed on the surface of the silicon substrate 200 and is embedded inside, the depletion layer does not contact the field oxide film 201. For this reason, leakage current can be reduced.

In the CMOS solid-state imaging device shown in FIG. 16, the depletion layer formed at the interface between the N-type layer 211 and the P ⁺ -type layer 210 is thinner than the depletion layer formed below the N-type layer 211. Therefore, the capacitance between the N-type layer 211 and the P ⁺ -type layer 210 occupies most of the junction capacitance. As described above, the junction capacitance is increased, so that the light receiving sensitivity is lowered. Further, since the depletion layer above the N-type layer 211 is thin, photoelectric conversion is performed mainly in the depletion layer formed below the N-type layer 211. Since short-wavelength light attenuates when passing through the P ⁺ -type layer 210 and the N-type layer 211, the sensitivity in the short-wavelength region is particularly lowered.

As shown in FIG. 16B, the outer periphery of the N-type layer 211 is separated from the boundary line between the field oxide film 201 and the active region to the active region side by a predetermined width, for example, 0.1 to 0.2 μm. Yes. Thereby, it is possible to prevent a depletion layer formed at the interface between N-type layer 211 and P ⁺ -type layer 210 from contacting field oxide film 201. However, with such a structure, the effective light receiving area of the photodiode is reduced. In particular, when the pixels are miniaturized, the ratio of the frame portion between the N-type layer 211 and the field oxide film 201 increases.

  An object of the present invention is to provide a semiconductor light receiving device applied to a solid-state imaging device with high sensitivity and low leakage current.

According to one aspect of the invention,
An element isolation insulating region formed in a surface layer portion of the semiconductor substrate and defining an active region including a photodiode inside ;
A first layer of a first conductivity type formed in a part of a surface layer portion of the active region and serving as a cathode of the photodiode, and defining a depletion layer below the first layer When,
The first layer and the element isolation insulating region are disposed along a boundary between the active region and the element isolation insulating region, and when viewed from above the surface of the semiconductor substrate, the first layer A first conductivity type first region having a layer and a portion overlapping with the element isolation insulating region and reaching a region deeper than the first layer;
A MISFET formed in a region of the active region where the first layer is not disposed, the MISFET having a second conductivity type disposed on a surface layer portion of the semiconductor substrate with a channel region interposed therebetween. First and second impurity diffusion regions and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, and the first impurity diffusion region is electrically connected to the first layer A semiconductor light-receiving device having the MISFET is provided.

  When light enters the depletion layer formed below the first layer, electron-hole pairs are generated, carriers are accumulated in the first layer, and the potential changes. The amount of change in potential of the first layer depends on the amount of received light. Since the first region is disposed between the first layer and the element isolation insulating region, the depletion layer does not contact the element isolation insulating film. For this reason, an increase in leakage current can be prevented.

  FIG. 1 shows a schematic equivalent circuit diagram of a CMOS type solid-state imaging device. A plurality of pixels PXL are arranged in a matrix. A select line SEL and a reset line RST are arranged corresponding to each row of the pixels PXL, and a signal line SIG is arranged corresponding to each column. The select line SEL and the reset line RST are connected to the drive circuit DRV, and the signal line SIG is connected to the readout circuit SNS.

FIG. 2A shows an equivalent circuit diagram of one pixel of a three-transistor solid-state imaging device. The cathode of the photodiode PD is connected to the reset voltage line VR via the reset transistor _TRS . A reset voltage is applied to the reset voltage line VR. The anode of the photodiode PD is grounded.

The source follower transistor _{T SF} and a select transistor _{T SL} are connected in series. The drain terminal of the source follower transistor T _SF is connected to the reset voltage line VR, and the source terminal of the select transistor T _SL is connected to the signal line SIG. The gate electrode of the source follower transistor T _SF is connected to the cathode of the photodiode PD, and the gate electrode of the select transistor T _SL is connected to the select line SEL. Note that the reset transistor T _RS , the source follower transistor T _SF , and the select transistor T _SL are all N-channel MOSFETs.

  Note that all the transistors in the pixel are N-channel MOSFETs, but their peripheral circuits are composed of CMOS. For this reason, the solid-state imaging device shown in FIG. 2A is called a CMOS solid-state imaging device.

Hereinafter, an operation of the three-transistor solid-state imaging device illustrated in FIG. First, by conducting the reset transistor T _RS, a reverse bias is applied to the photodiode PD, it initializes the cathode to a reset voltage. The reset transistor _TRS is turned off and light reception is started. When light enters the photodiode PD, electrons are accumulated on the cathode, and the potential of the cathode is lowered.

In response to a decrease in the cathode potential, the potential of the gate electrode of the source follower transistor T _SF is reduced. When to conduct the select transistor T _SL, the cathode of the voltage signal voltage corresponding to the drop in the photodiode PD is output to the signal line SIG. The signal voltage appearing on the signal line SIG is detected by the readout circuit SNS shown in FIG. Then, by conducting the reset transistor T _RS, the reset voltage is applied to the gate electrode of the source follower transistor T _SF. In this state, the voltage appearing on the signal line SIG is detected by the readout circuit SNS.

The difference between the two voltages detected by the readout circuit SNS is obtained. This difference becomes a value depending on the amount of light received by the photodiode PD. By obtaining a difference between two voltages, it is possible to avoid the influence of variation of the signal voltage due to fluctuation of each pixel in the threshold voltage of the source follower transistor T _SF and select transistor T _SL.

  FIG. 2B is a plan view of one pixel of the three-transistor solid-state imaging device according to the first reference example. The active region 1 is connected to the quadrangular portion 1A, the portion 1B projecting rightward from the vicinity of the upper end of the right side of the quadrangular portion 1A, the tip of the projecting portion 1B, and spaced from the right side of the quadrangular portion 1A. A portion 1C that extends in the column direction and a portion 1D that continues to the lower end of the portion 1C that extends in the column direction and extends in the row direction with a certain interval from the lower side of the quadrangular portion 1A. A photodiode PD is arranged in the rectangular portion 1A.

Gate electrode of the reset transistor T _RS is, crosses the portion 1C extending in the column direction of the active region 1, in yet lower than the crossing point, in the column direction the gate electrode of the source follower transistor T _SF is the active region 1 It intersects with the extended portion 1C. The gate electrode of the select transistor T _SL crosses the portion 1D extending in the row direction of the active region 1. Gate electrode of the select transistor T _SL branches from the select line SEL extending in the row direction.

Of the active region 1, and the portion 1A of the arranged rectangular photodiode PD, a region (the drain region of the reset transistor T _RS) between the placement portion of the gate electrode of the reset transistor T _RS, a contact hole H _SF is arranged. A source region of the reset transistor T _RS, a contact hole H _SF, and via the upper wiring, and is connected to the gate electrode of the source follower transistor T _SF.

Of the active region 1, over the portion 1A of the arranged rectangular photodiode PD until disposed region of the contact hole H _SF, N-type buried layer 5 is disposed slightly deeper from the substrate surface. The arrangement area of the contact hole H _SF, buried layer connection region 8 extending from the upper surface of the N-type buried layer 5 to the substrate surface is disposed. The outer periphery of the N-type buried layer 5 enters the field oxide film side from the edge of the active region 1. The contact hole H _SF is included in the buried layer connection portion 8.

Gate electrode of the reset transistor _{T RS} is, the upper layer of the reset line RST via a contact hole _{H RST} is connected to (FIGS. 1, 2 (A) refer).
Of the active region 1, and the intersection of the gate electrode of the reset transistor T _RS, a source follower transistor T _SF drain region and a source follower transistor T _SF regions (the reset transistor T _RS between the intersection of the gate electrode of the The contact hole _HVR is disposed in the drain region). Drain region of the drain region and the source follower transistor T _SF of the reset transistor T _RS is connected to the upper layer of the reset voltage line VR (see FIG. 2 (A)) via the contact hole H _VR.

Of the active region 1D, contact holes H _SIG are arranged in the left area (the source region of the select transistor T _SL) than at the intersection with the gate electrode of the select transistor T _SL. A source region of the select transistor _{T SL,} via the contact hole _{H SIG,} the upper layer of the signal line SIG is connected to (FIGS. 1, 2 (A) refer).

  FIG. 3 is a cross-sectional view taken along one-dot chain line A3-A3 in FIG. A field oxide film 4 having a thickness of 250 to 350 nm is formed on the surface of the silicon substrate 2, and an active region 1 surrounded by the field oxide film 4 is defined. Of the surface layer portion of the P-type silicon substrate 2, a P-type well 3 is formed in a region other than the region where the photodiode PD is disposed in the active region 1 and a region where the field oxide film 4 is formed.

A P ⁺ -type layer 6 is formed in the surface layer portion of the region where the photodiode PD is disposed, and an N-type buried layer 5 is formed at a deeper position with a certain distance from the P ⁺ -type layer 6. Yes. The P ⁺ type layer 6 is in contact with a P type well 3 formed below the field oxide film 4.

N type buried layer 5 is disposed at a position where the depth from the surface of silicon substrate 2 is deeper than 0.5 μm, and the upper surface thereof is disposed at a position deeper than the bottom surface of field oxide film 4. When viewed with a line of sight parallel to the substrate normal direction, most of the N-type buried layer 5 overlaps with the P ⁺ -type layer 6. Immediately below the field oxide film 4, the upper surface of the N-type buried layer 5 is formed at a position shallower by 0.1 to 0.2 μm than the upper surface of the portion immediately below the active region. Also in this portion, an interval of about 0.2 μm is secured between the upper surface of the depletion layer extending from the N-type buried layer 5 and the bottom surface of the field oxide film 4. A depletion layer is formed between the N-type buried layer 5 and the P ⁺ -type layer 6 and below the N-type buried layer 5. The N type buried layer 5 becomes the cathode of the photodiode PD, and the P ⁺ type layer 6 and the silicon substrate 2 become the anode of the photodiode PD.

  When viewed in a line of sight parallel to the substrate normal, the end of the N-type buried layer 5 overlaps the field oxide film 4. Since the upper surface of the N-type buried layer 5 is disposed at a position deeper than the bottom surface of the field oxide film 4, even if the N-type buried layer 5 and the field oxide film 4 are partially overlapped, N The depletion layer extending from the mold buried layer 5 does not contact the field oxide film 4.

  The N type buried layer 5 is not disposed in the P type well. Since the P-type impurity concentration of the silicon substrate 2 below the N-type buried layer 5 is lower than the impurity concentration of the P-type well, the depletion layer extends below the N-type buried layer 5.

On the surface of the active region 1, a reset transistor T _RS , a source follower transistor T _SF , and a select transistor T _SL are formed. These are all N-channel MOSFETs. An N-type buried layer connection portion 8 extends upward from a portion of the N-type buried layer 5 that does not overlap the P ⁺ -type layer 6 and reaches the surface of the silicon substrate 2. The buried layer connecting portion 8 is in contact with the source region 10 of the reset transistor _TRS .

First impurity diffusion region 11 of the N type formed in the surface layer of the silicon substrate 2, also serves as a drain region of the drain region and the source follower transistor T _SF of the reset transistor T _RS. Second impurity diffusion regions 12 of the N type, also serves as a drain region of the source region and the select transistor T _SL of the source follower transistor T _SF. The N-type third impurity diffusion region 13 becomes the source region of the select transistor _TSL . The bottom surfaces of the first to third impurity diffusion regions 11 to 13 are disposed at a position shallower than the top surface of the N-type buried layer 5.

A gate oxide film 15 covers the surface of the silicon substrate 2 on which the photodiode PD is disposed. The gate oxide film 15 is also disposed between the gate electrode of the MOSFET and the silicon substrate 2. Mask film 16 made of silicon oxide, covering the photodiode PD arranged in that the surface of the silicon substrate 2, a portion of the upper surface of the gate electrode G of the reset transistor T source region 10 of the _RS, and the reset transistor T _RS continuously .

Reset transistor T region not covered with the mask film 16 of the top surface of the gate electrode G of the _RS, the upper surface of the gate electrode G of the source follower transistor T _SF, the upper surface of the gate electrode G of the select transistor T _SL, the first impurity diffusion A metal silicide film 18 made of, for example, titanium silicide or cobalt silicide is formed on the upper surfaces of the region 11, the second impurity diffusion region 12, and the third impurity diffusion region 13.

  A lower interlayer insulating film 20 made of silicon nitride or silicon oxynitride covers the mask film 16 and each transistor. A main interlayer insulating film 21 made of silicon oxide is formed on the lower interlayer insulating film 20.

A contact hole H _SF reaching from the upper surface of the main interlayer insulating film 21 to the surface of the silicon substrate 2 is formed at the position where the buried layer connection portion 8 is disposed. As shown in FIG. 2B, the contact hole H _SF is included in the buried layer connection portion 8 when viewed in a line of sight parallel to the normal of the substrate surface. Contact holes _HVR and _HSIG reaching from the upper surface of the main interlayer insulating film 21 to the upper surface of the metal silicide film 18 are formed at the positions where the first impurity diffusion region 11 and the third impurity diffusion region 13 are arranged. .

Plugs 23 made of tungsten are embedded in the contact holes H _SF , H _VR , and H _SIG . Note that the bottom and side surfaces of the contact holes H _SF , H _VR , and H _SIG are covered with a barrier metal layer made of TiN or the like.

Next, with reference to FIGS. 4 and 5, a method for manufacturing a CMOS solid-state imaging device according to the first reference example will be described.
As shown in FIG. 4A, a field oxide film 4 having a thickness of 250 to 350 nm (central condition 300 nm) is formed on the surface of a P-type silicon substrate 2 by a silicon local oxidation (LOCOS) method. An active region 1 is defined by the field oxide film 4. A P-type well 3 for forming an N-channel MOSFET is formed. The surface of the active region 1 is thermally oxidized to form a gate oxide film 15 having a thickness of 3 to 7 nm (center condition 5 nm).

Hereinafter, steps required until the state shown in FIG. A polycrystalline silicon film having a thickness of 150 to 250 nm (central condition: 180 nm) is deposited on the substrate surface by chemical vapor deposition (CVD). In this polycrystalline silicon film, an acceleration energy of 10 to 30 keV (center condition of 20 keV) and a dose of 2 × 10 ^{15 to} 6 × 10 ¹⁵ cm ⁻² (center condition of 4 × 10 10) are formed in a region that becomes the gate electrode of the N-channel MOSFET. Phosphorus (P) ions are implanted under the condition of ¹⁵ cm ⁻² . Thereafter, activation annealing is performed at about 800.degree.

  This polycrystalline silicon film is patterned to leave the gate electrode G of the MOSFET. Etching of the polycrystalline silicon film can be performed by reactive ion etching (RIE) using a chlorine-based etching gas.

Hereinafter, steps required until a state illustrated in FIG. Acceleration energy 360 to 500 keV (center condition 420 keV), dose amount 0.5 × 10 ¹² to 1 × 10 ¹³ cm ⁻² (center condition 3 × 10 ¹² cm ⁻² ), peak depth of impurity profile after ion implantation N-type buried layer 5 is formed by implanting phosphorus ions under the condition of Rp = 0.57 μm.

Next, the buried layer connection portion 8 is formed by implanting phosphorus ions. The buried layer connecting portion 8 is formed by three ion implantations with different implantation conditions. First, phosphorus ions are implanted under the conditions of acceleration energy 30 to 100 keV (center condition 30 keV) and dose 1 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² (center condition 2 × 10 ¹⁵ cm ⁻² ), and the shallowest portion Form. Next, phosphorus ions are applied under the conditions of acceleration energy 100 to 220 keV (center condition 160 keV), dose 1 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² (center condition 2 × 10 ¹³ cm ⁻² ), Rp = 0.21 μm. Inject to form the central portion. Finally, under the conditions of acceleration energy 200 to 360 keV (center condition 260 keV), dose amount 0.5 × 10 ¹² to 2 × 10 ¹³ cm ⁻² (center condition 1 × 10 ¹³ cm ⁻² ), Rp = 0.35 μm. Phosphorus ions are implanted to form the deepest part.

Ion implantation for forming a lightly doped region LDD of a source region and a drain region having a lightly doped drain (LDD) structure of an N channel type MOSFET is performed. The impurity to be implanted is phosphorus, the acceleration energy is 10 to 30 keV (center condition 20 keV), and the dose is 2 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² (center condition 4 × 10 ¹³ cm ⁻² ). .

Ion implantation for forming the P ⁺ -type layer 6 is performed. The impurity ions to be implanted are boron (B), the acceleration energy is 5 to 10 keV, and the dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . The impurity ions to be implanted may be BF ₂ and the acceleration energy may be 30 keV. This ion implantation also serves as ion implantation for forming the low concentration regions of the source and drain regions of the P-channel MOSFET in the peripheral circuit.

As described above, the ion implantation for forming the buried layer connection portion 8 is performed separately from the ion implantation for forming the source and drain regions of the reset transistor _TRS , thereby The impurity concentration can be set independently of the characteristics of the reset transistor _TRS .

Processes up to the state shown in FIG. A silicon oxide film having a thickness of 50 to 150 nm (center condition 100 nm) is deposited on the substrate by CVD. A region from where the photodiode PD is formed to a part of the upper surface of the gate electrode G of the reset transistor _TRS is continuously covered with a resist pattern. Using this resist pattern as a mask, the silicon oxide film is anisotropically etched by RIE using a fluorine-based gas. After the etching, the resist pattern is removed. The mask film 16 that continuously covers from the region where the photodiode PD is disposed to a part of the upper surface of the gate electrode G of the reset transistor _TRS remains, and the sidewall spacer SW remains on the side surface of the gate electrode G.

In the region where the N-channel MOSFET is formed, the acceleration energy is 10 to 30 keV (center condition 20 keV) and the dose is 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² (center condition 2 × 10 ¹⁵ cm ⁻² ). Phosphorus ions are implanted to form first to third impurity diffusion regions 11 to 13. Boron in the region where the P-channel MOSFET is formed under the conditions of acceleration energy 5 to 10 keV (center condition 7 keV) and dose 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² (center condition 2 × 10 ¹⁵ cm ⁻² ) Ions are implanted.

  Next, steps required until the state shown in FIG. By depositing a Ti or Co film on the substrate by sputtering and performing rapid thermal annealing (RTA), the metal silicide film 18 is formed on the upper surface of the gate electrode G and the first to third impurity diffusion regions 11 to 13. Form. After RTA, the unreacted Ti or Co film is removed. At this time, since the surface of the photodiode PD is covered with the mask film 16, a metal silicide film is not formed on this portion.

  A lower interlayer insulating film 20 made of silicon nitride and having a thickness of 50 to 100 nm is deposited on the substrate by plasma CVD. Note that a silicon oxynitride film having a thickness of 100 to 300 nm (center condition 200 nm) may be used as the lower interlayer insulating film 20. On the lower interlayer insulating film 20, a main interlayer insulating film 21 made of silicon oxide and having a thickness of 700 to 1500 nm (central condition 1000 nm) is deposited by plasma CVD. Chemical mechanical polishing (CMP) is performed to flatten the surface of the main interlayer insulating film 21.

After planarizing the surface of the main interlayer insulating film 21, contact holes H _SF , H _VR , and H _SIG are formed. Conductive plugs 23 are filled in the contact holes H _SF , H _VR , and H _SIG by depositing a barrier metal layer, a tungsten layer, and CMP.

The bottom surface of the low concentration region 10 of the drain of the reset transistor _TRS shown in FIG. 3 is disposed at a position shallower than the top surface of the N-type buried layer 5. By disposing the buried layer connection region 8 extending from the N-type buried layer 5 to the surface of the silicon substrate 2, it is possible to electrically connect the N-type buried layer 5 to the drain region 10 of the reset transistor T _RS .

  In the first reference example, since the N-type buried layer 5 is disposed at a deep position, the junction capacitance of the photodiode PD can be reduced. Thereby, the sensitivity of the photodiode PD can be improved.

Further, since the N-type buried layer 5 is arranged at a distance from the P ⁺ -type layer 6 in the depth direction, the depletion layer between the two becomes thick. When light is incident on the photodiode PD from the main interlayer insulating film 21 side, photoelectric conversion is mainly performed in a depletion layer at a position shallower than the N-type buried layer 5, which is caused by light absorption by the N-type buried layer 5. It is possible to suppress a decrease in sensitivity.

  Since the P-type well 3 having a higher concentration than the P-type impurity concentration of the silicon substrate 2 is formed below the field oxide film 4 adjacent to the photodiode PD, the depletion layer extending from the N-type buried layer 5 is subjected to field oxidation. Contact with the membrane 4 can be prevented. Thereby, an increase in leakage current can be prevented.

  Further, in the first reference example, the region near the outer periphery of the N-type buried layer 5 penetrates below the field oxide film 4. The effective light receiving region can be increased as compared with the conventional device in which the edge of the N-type layer of the photodiode is recessed from the edge of the field oxide film 4 into the active region.

A contact hole _HSF is formed immediately above the buried layer connecting portion 8, and the conductive plug 23 contacts the upper surface of the buried layer connecting portion 8. Thus, since the conductive plug 23 contacts the relatively deep buried layer connection portion 8, an increase in junction leakage current can be prevented.

  Next, a modification of the first reference example will be described with reference to FIG. In the first reference example, the buried layer connection unit 8 of FIG. 3 is applied to a three-transistor type solid-state imaging device. Structure is applied.

FIG. 6A shows an equivalent circuit diagram of one pixel of a general four-transistor solid-state imaging device. A transfer transistor _TTR is inserted between the reset transistor _TRS and the photodiode PD of the three-transistor solid-state imaging device shown in FIG. Cathode voltage of the photodiode PD is applied to the gate electrode of the source follower transistor T _SF via the transfer transistor T _TR. Other structures are the same as the structure of the three-transistor solid-state imaging device shown in FIG.

FIG. 6B shows a cross-sectional view of the photodiode PD and the transfer transistor _TTR . The following description will be given focusing on differences from the cross-sectional view of the three-transistor solid-state imaging device shown in FIG.

A transfer transistor _TTR is formed in the P-type well 3. The transfer transistor _TTR includes a source region 50 and a drain region 51 that are arranged with a channel region interposed therebetween, and a gate electrode G that is formed on the channel region via a gate insulating film. Source region 50 is connected to N type buried layer 5 via buried layer connecting portion 8A.

The buried layer connecting portion 8A is formed by two phosphorus ion implantations. The first ion implantation is performed under the conditions of an acceleration energy of 100 to 220 keV and a dose amount of 1 × 10 ^{12 to} 3 × 10 ¹³ cm ⁻² , and the second ion implantation is an acceleration energy of 200 to 360 keV and a dose amount. It is performed under conditions of 5 × 10 ^{11 to} 2 × 10 ¹³ cm ⁻² .

The P ⁺ type layer 6 overlaps a part of the source region 50 and extends to the vicinity of the gate electrode G of the transfer transistor _TTR . Thereby, a more complete embedded photodiode is formed. As in the case of the three-transistor solid-state imaging device, the N-type buried layer 5 can be enlarged to widen the light receiving part.

Next, a CMOS type solid-state imaging device according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a plan view of one pixel of the three-transistor solid-state imaging device according to the embodiment. Hereinafter, differences from the CMOS type solid-state imaging device according to the first reference example shown in FIG. 2B will be described.

An N-type layer 30 serving as a cathode of the photodiode PD is disposed inside the square portion 1A of the active region 1. An N-type frame region 31 is arranged along the boundary line between the rectangular portion 1A of the active region 1 and the field oxide film. N-type frame region 31 extends to the side of the gate electrode of the reset transistor T _RS, to form a high density portion D _RS of the source region of the reset transistor T _RS. Other configurations are the same as the configuration of the CMOS solid-state imaging device according to the first reference example shown in FIG.

FIG. 8 is a cross-sectional view taken along one-dot chain line A7-A7 in FIG. The structure from the gate electrode of the reset transistor _TRS to the select transistor _TSL is the same as the configuration of the CMOS solid-state imaging device according to the first reference example shown in FIG.

An N-type layer 30 is formed on the surface layer portion of the silicon substrate 2 in the region where the photodiode PD is disposed. An N-type frame region 31 is formed along the boundary line between the field oxide film and the active region around the photodiode PD. The N-type frame region 31 reaches a position deeper than the N-type layer 30. As shown in FIG. 7, N-type frame region 31, via a region not shown in cross section in FIG. 8, it is continuous in the high density portion D _RS of the source region of the reset transistor T _RS.

Next, a manufacturing method of the CMOS type solid-state imaging device according to the embodiment will be described with reference to FIG. The P-type well 3, the field oxide film 4, and the gate electrode G are formed by the same processes as those shown in FIGS. 4A to 4B referred to in the description of the first reference example. An acceleration energy of 10 to 30 keV (center condition 20 keV) and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² (center condition 4 ×) are formed in the region where the N-channel MOSFET is to be formed and the region where the photodiode PD is to be formed. Phosphorus ions are implanted under the condition of 10 ¹³ cm ⁻² . The lightly doped regions LDD of the source and drain regions having the LDD structure of the N channel type MOSFET are formed, and the N type layer 30 serving as the cathode of the photodiode PD is formed. The depth of the N-type layer 30 is less than 0.1 μm. Thus, by forming the N-type layer 30 in the center of the photodiode shallow, attenuation of short-wavelength light in the N-type layer can be suppressed and sensitivity can be improved.

Next, the injection of phosphorus ions for forming the high-concentration portion D _RS of the drain region of the N-type frame region 31 and the reset transistor T _RS. The acceleration energy is 70 to 180 keV (center condition 100 keV), and the dose is 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² (center condition 2 × 10 ¹³ cm ⁻² ). The N-type frame region 31 has a width of 0.3 to 0.5 μm and a depth of 0.1 to 0.25 μm.

The process from the formation of the mask film 16 and the side wall spacer SW shown in FIG. 8 to the formation of the conductive plug 23 is the same as the manufacturing process of the first reference example described with reference to FIGS. It is. A contact hole H _SF formed in the high density portion on D _RS of the source region of the reset transistor T _RS, when viewed in a parallel line of sight to the substrate normal, is included in the high density portion D _RS of the source region. Since the conductive plug 23 contacts the high-concentration portion _DRS in the relatively deep source region, an increase in junction leakage current due to contact with the conductive plug can be suppressed.

  A deep N-type frame region 31 is formed in a region where stress is concentrated near the edge of the field oxide film 4. For this reason, the depletion layer extending downward from the N-type layer 30 does not contact the region where stress is concentrated. This can prevent an increase in leakage current in a region where stress is concentrated.

In the above embodiment, the acceleration energy for ion implantation for forming the N-type frame region 31 is set higher than the acceleration energy for ion implantation for forming the N-type layer 30, but instead of increasing the acceleration energy, the dose is increased. The amount may be increased. For example, ion implantation may be performed under the conditions of acceleration energy of 10 to 30 keV (center condition 20 keV) and dose amount 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² (center condition 2 × 10 ¹⁵ cm ⁻² ). If the dose is increased, impurities are diffused deeper in the depth direction during activation annealing. Therefore, an N-type frame region 31 deeper than the N-type layer 30 can be formed.

By making the impurity concentration of the N-type layer 30 less than 1 × 10 ²⁰ cm ⁻³ and making the impurity concentration of the N-type frame region 31 higher than 1 × 10 ²⁰ cm ⁻³ , a sufficient effect of preventing increase in leakage current can be obtained. Obtainable.

FIG. 10 is a plan view of a CMOS type solid-state imaging device according to a modification of the embodiment. In the embodiment shown in FIG. 7, the N-type frame region 31 extends to the side of the gate electrode of the reset transistor _TRS . In a variation of the embodiment, as shown in FIG. 10, N-type frame region 31, hanging on a part of the gate electrode of the reset transistor T _RS. Thus, over the entire length of the edge of the field oxide film in contact with the reset transistor T active region 1 of the source region D _RS side than the gate electrode of the _RS, the deep N-type frame region 31 is disposed. For this reason, it is possible to reduce the leakage current flowing through the stress concentration portion near the edge of the field oxide film.

The ion implantation for forming the N-type frame region 31 is performed, for example, with an acceleration energy of 10 to 30 keV (center condition 20 keV) and a dose of 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² (center condition 2 × 10 ¹⁵ cm ^{− 2} ) Perform under the condition. Thus, when ions are implanted at a low acceleration energy condition, also the region where ions are implanted is applied to the gate electrode of the reset transistor T _RS, it does not affect the characteristics of the reset transistor T _RS.

  Next, a CMOS type solid-state imaging device according to a second reference example will be described with reference to FIGS. The CMOS type solid-state imaging device according to the first reference example and the example is of a three-transistor type, whereas the CMOS type solid-state imaging device according to the second reference example is of a four-transistor type.

FIG. 11A shows an equivalent circuit diagram of one pixel of the CMOS solid-state imaging device according to the second reference example. A transfer transistor _TTR is inserted between the reset transistor _TRS and the photodiode PD of the three-transistor type solid-state imaging device shown in FIG. Interconnection point between the reset transistor T _RS and transfer transistor T _TR is connected to the gate electrode of the source follower transistor T _SF. Gate electrode of the transfer transistor _{T TR} is connected to the select line SEL with the gate electrode of the select transistor _{T SL.}

  FIG. 11B is a plan view of one pixel portion of the CMOS solid-state imaging device according to the second reference example. Hereinafter, differences from the plan view of one pixel portion of the CMOS solid-state imaging device according to the first reference example shown in FIG. 2B will be described.

In the case of the first reference example shown in FIG. 2B, the photodiode PD is arranged on the extension of the gate electrode of the select transistor _TSL . In the second reference example of FIG. 11B, the photodiode PD is moved to the left of the figure, the gate electrode of the select transistor _TSL extends upward in the figure, and the square in which the photodiode PD is arranged. It intersects with a protruding portion 1B extending from the portion 1A to the right in the drawing. A transfer transistor _TTR is arranged at this intersection. Other configurations are the same as those of the first reference example shown in FIG.

12 is a cross-sectional view taken along one-dot chain line A11-A11 in FIG. A photodiode PD is constituted by a P-type layer 41 formed in the surface layer portion of the silicon substrate 2 and an N-type buried layer 40 formed at a deeper position. A transfer transistor T _TR , a reset transistor T _RS , a source follower transistor T _SF , and a selected transistor T _SL are formed in this order from the photodiode PD toward the right side of the drawing. The configurations of the source follower transistor T _SF and the select transistor T _SL are the same as the corresponding transistors shown in FIG.

In the first reference example, the source region 10 of the reset transistor T _RS was connected to the N-type buried layer 5 via the buried layer connection region 8, the second reference example, of the reset transistor T _RS fourth impurity diffusion regions 42 formed in the substrate surface layer portion between the gate electrodes of the transfer transistor T _TR is, also serves as a source region and a drain region of the transfer transistor T _TR of the reset transistor T _RS.

N-type buried layer 40 is below the gate electrode of the transfer transistor T _TR, it has penetrated only the depth, also serves as the source region of the transfer transistor T _TR. The P-type layer 15 is in contact with the P-type well 3 formed below the field oxide film 4 adjacent to the photodiode PD, and the edge of the N-type buried layer 40 is connected to the field oxide film 4 and the active region. It recedes to the active region side from the boundary line. For this reason, the depletion layer formed below the N-type buried layer 40 does not contact the vicinity of the end of the field oxide film 4. Thereby, it is possible to prevent the occurrence of leakage current at the interface between silicon and silicon oxide in the vicinity of the end of field oxide film 4.

Mask film 16 made of silicon oxide, from the region where the photodiode PD is disposed to a portion of the upper surface of the gate electrode of the transfer transistor T _TR and covers continuously. The lower interlayer insulating film 20 and the main interlayer insulating film 20 cover the mask film 16 and each transistor.

A position where the fourth impurity diffusion region 42 is disposed, and a contact hole H _SF penetrating the main interlayer insulating film 21 and the lower interlayer insulating film 20 is formed. Contact hole H _SF conductivity filled in the plug 23 is electrically connected to the fourth impurity diffusion region 42 through the metal silicide layer 18. Structure of the contact hole _{H VR} and _{H SIG} are the same as the corresponding contact hole _{H VR} and _{H SIG} of the first reference example shown in FIG. 3, respectively.

  With reference to FIG. 13, a method for manufacturing a CMOS solid-state imaging device according to the second reference example will be described. The process until the gate electrode G is formed is the same as the manufacturing method of the CMOS type solid-state imaging device of the first reference example described with reference to FIGS. 4 (A) and 4 (B). Thereafter, the low concentration portion LDD is formed by the same method as the formation of the low concentration portion LDD of the source and drain regions shown in FIG.

Next, phosphorus ions are implanted under the conditions of acceleration energy 30 to 50 keV (center condition 40 keV) and dose 1 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² (center condition 1 × 10 ¹³ cm ⁻² ). A mold buried layer 40 is formed. At this time, ion implantation is performed so that the end portion of the N-type buried layer 40 is recessed below the gate electrode. Next, BF ₂ ions are implanted under the conditions of an acceleration energy of 30 keV and a dose of 1 × 10 ¹³ cm ⁻² to form a P-type layer 41 in a region shallower than the N-type buried layer 40. Simultaneously with the formation of the P-type layer 41, low concentration portions of the source and drain of the P-channel MOSFET (not shown in FIG. 13) of the peripheral circuit are formed.

  The steps for forming the mask film 16, the impurity diffusion regions 11, 12, 13, 42, the lower interlayer insulating film 20, the main interlayer insulating film 21, and the conductive plug 23 shown in FIG. 12 are shown in the first reference example. It is the same as the process demonstrated with reference to 5 (D) and FIG.

FIG. 14 shows an operation timing chart of the CMOS solid-state imaging device of the second reference example. Waveforms RST, SEL, VPD, GSF, and VSIG in the figure are respectively a reset signal applied to the reset line RST in FIG. 11A, a select signal applied to the select line SEL, a cathode voltage of the photodiode PD, and a source. it represents the gate voltage of the follower transistor T _SF, and the signal voltage appearing on the signal line SIG. In the following description, a voltage drop corresponding to the threshold voltage of the MOSFET is not considered unless otherwise specified.

At time _{t 1,} the select signal SEL has become a high level, the reset signal RST rises. The reset transistor _TRS and the transfer transistor _TTR are turned on, and the cathode voltage VPD of the photodiode PD is initialized to the reset voltage VR.

Select signal SEL falls at time _{t 2, the} transfer transistor _{T TR} is nonconducting. Photoelectric conversion is performed according to the intensity of light incident on the photodiode PD, and electrons are accumulated in the cathode. As a result, the cathode voltage VPD of the photodiode PD decreases.

At time _{t 3,} the reset signal RST fall and the reset transistor _{T RS} nonconducting. At time _{t 4} immediately after that, the select signal SEL rises. Thereby, the transfer transistor _TTR and the select transistor _TSL are conducted.

Cathode voltage VPD of the photodiode PD is applied to the gate electrode of the source follower transistor _{T SF,} the cathode voltage VPD is applied to the source of the source follower transistor _{T SF.} The cathode voltage VPD is output to the signal line SIG via the select transistor _{T SL.} Note that the voltage VSIG of the signal line SIG is limited by the CR time constant and gradually increases. When the signal voltage VSIG appearing on the signal line SIG becomes constant, the reading circuit SNS shown in FIG. 1 detects the voltage.

At time _{t 5,} the reset signal RST rises. With cathode voltage VPD of the photodiode PD is initialized to the reset voltage VR, the reset voltage VR is applied to the gate electrode of the source follower transistor T _SF. Source follower transistor _{T SF} is brought into conduction, the reset voltage VR appearing on the signal line SIG. The read circuit SNS shown in FIG. 1 detects this reset voltage VR. The signal voltage VSIG detected immediately before the time t _5, the difference between the detected reset voltage VR determined.

Select signal SEL falls at time _{t 6,} in the same state as the time _{t 1.}
In the above description, but it did not consider the voltage drop of the threshold voltage of each MOSFET, in fact, is the signal voltage VSIG and reset voltage VR is output to the signal line SIG, by the threshold voltage of the source follower transistor T _SF descend. The threshold voltage of the MOSFET varies from pixel to pixel. As described above, by obtaining the difference between the signal voltage VSIG corresponding to the amount of received light and the detected reset voltage VR, it is possible to eliminate the influence of variations in threshold voltage and prevent the generation of a fixed noise pattern. .

  In the second reference example, as shown in FIG. 12, the conductive plug made of tungsten or the like is not in contact with the N-type buried layer 40 corresponding to the cathode of the photodiode PD. For this reason, an increase in junction leakage current due to contact of the conductive plug can be prevented.

Further, in the second reference example, the gate electrode of the select transistor T _SL, as shown in FIG. 11 (B) extends upward in the figure, constitute a gate electrode of the transfer transistor T _TR. In the conventional four-transistor type solid-state imaging device, it is necessary to arrange a control line for controlling the gate electrode of the transfer transistor _TTR and a contact hole for connecting the gate electrode and the control line. In the second reference example, since it is not necessary to arrange these, the area ratio occupied by the photodiode PD in one pixel can be increased.

Further, as described in FIG. 14, the time t ₃ when lowers the reset signal RST, it is preferable to immediately before time t ₄ when starting up the select signal SEL. With such a timing, it is possible to shorten the period interconnection point is in a floating state between the reset transistor T _RS and transfer transistor T _TR shown in Figure 11 (A).

This interconnection point corresponds to the fourth impurity diffusion region 42 shown in FIG. When the fourth impurity diffusion region 42 is in a floating state, a voltage that varies by junction leakage current, the signal voltage applied to the gate electrode of the source follower transistor T _SF is affected by the voltage variation . By shortening the period during which the fourth impurity diffusion region 42 is in the floating state, the influence of the junction leakage current can be reduced. For example, time from time t ₂ to time t ₄ is, as will become more than 300 times the time from time t ₃ to time t _4, by the timing control, it is possible to reduce the influence of junction leak current .

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

1 is an equivalent circuit diagram of a CMOS type solid-state imaging device according to an embodiment of the present invention. (A) is an equivalent circuit diagram of one pixel of the CMOS type solid-state imaging device according to the first reference example, and (B) is a plan view of one pixel. It is sectional drawing of the principal part of 1 pixel of the CMOS type solid-state imaging device by a 1st reference example. It is sectional drawing (the 1) of the board | substrate for demonstrating the manufacturing method of the CMOS type solid-state imaging device by a 1st reference example. It is sectional drawing (the 2) of the board | substrate for demonstrating the manufacturing method of the CMOS type solid-state imaging device by a 1st reference example. It is the equivalent circuit schematic and fragmentary sectional view of the CMOS type solid-state imaging device by the modification of the 1st reference example. It is a top view of 1 pixel of the CMOS type solid-state imaging device by an Example. It is sectional drawing of the principal part of 1 pixel of the CMOS type solid-state imaging device by an Example. It is sectional drawing of the board | substrate for demonstrating the manufacturing method of the CMOS type solid-state imaging device by an Example. It is a top view of 1 pixel of the CMOS type solid-state imaging device by the modification of an Example. (A) is an equivalent circuit diagram of one pixel of the CMOS solid-state imaging device according to the second reference example, and (B) is a plan view of one pixel. It is sectional drawing of the principal part of 1 pixel of the CMOS type solid-state imaging device by a 2nd reference example. It is sectional drawing of the board | substrate for demonstrating the manufacturing method of the CMOS type solid-state imaging device by the 2nd reference example. It is an operation | movement timing chart of the CMOS type solid-state imaging device by the 2nd reference example. It is sectional drawing of the principal part of the solid-state imaging device using the conventional N ⁺ P type photodiode. It is sectional drawing and the top view of the principal part of the solid-state imaging device using the conventional P ⁺ NP type photodiode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active region 2 Silicon substrate 3 P type well 4 Field oxide film 5 N type buried layer 6 P ⁺ type layer 8 Buried layer connection part 10 Source region 11, 12, 13 Impurity diffusion region 15 Gate oxide film 16 Mask film 18 Metal silicide film 20 Lower interlayer insulating film 21 Main interlayer insulating film 23 Conductive plug 30 N-type layer 31 N-type frame region 40 N-type buried layer 41 P ⁺ -type layer RST Reset line SEL Select line SIG Signal line DRV Drive circuit SNS readout circuit PXL pixel T _RS reset transistor T _SF source follower transistor T _SL select transistor T _TR transfer transistor PD photodiode

Claims (4)

An element isolation insulating region formed in a surface layer portion of the semiconductor substrate and defining an active region including a photodiode inside ;
A first layer of a first conductivity type formed in a part of a surface layer portion of the active region and serving as a cathode of the photodiode, and defining a depletion layer below the first layer When,
The first layer and the element isolation insulating region are disposed along a boundary between the active region and the element isolation insulating region, and when viewed from above the surface of the semiconductor substrate, the first layer A first conductivity type first region having a layer and a portion overlapping with the element isolation insulating region and reaching a region deeper than the first layer;
A MISFET formed in a region of the active region where the first layer is not disposed, the MISFET having a second conductivity type disposed on a surface layer portion of the semiconductor substrate with a channel region interposed therebetween. First and second impurity diffusion regions and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, and the first impurity diffusion region is electrically connected to the first layer A semiconductor light receiving device comprising the MISFET.   The depth from the surface of the semiconductor substrate to the bottom surface of the first layer is less than 0.1 μm, and the depth from the surface of the semiconductor substrate to the bottom surface of the first region is deeper than 0.1 μm. The semiconductor light-receiving device according to 1. 3. The semiconductor light receiving device according to claim 1, wherein the impurity concentration of the first layer is less than 1 × 10 ²⁰ cm ⁻³ and the impurity concentration of the first region is higher than 1 × 10 ²⁰ cm ^−3. . Furthermore, an interlayer insulating film formed on the semiconductor substrate so as to cover the first layer and the MISFET,
A second region formed in a part of a surface layer portion of the active region, in contact with the first layer, and having the same impurity concentration as the first region;
A contact hole disposed so as to be included in the second region when viewed in a line of sight parallel to a normal line of the surface of the semiconductor substrate, and penetrating the interlayer insulating film;
The semiconductor light-receiving device according to claim 1, further comprising a conductive member embedded in the contact hole.

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