JP3118889B2 - CCD image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD image pickup device and, more particularly, to a structure of an output section of the CCD image pickup device.

[0002]

2. Description of the Related Art As shown in FIG. 2, a CCD image pickup device, particularly an output portion thereof, has a floating diffusion region FD, a reset gate A discharge element 2 including an RG and a reset drain region RD; and a source follower circuit 5 including a driving MOS transistor 3 and a load MOS transistor 4 at a stage subsequent to the discharge element 2.
Is provided.

In the charge transfer section 1, the signal charge transferred from the transfer section 7 in the last stage is temporarily stored in the floating diffusion region FD, and a voltage change based on the stored charge is transferred to the source follower circuit 5 in the subsequent stage. To the output terminal Tout of the source follower circuit 5
As an output voltage Vout. After removal of the output voltage Vout from the output terminal Tout, the supplies a reset pulse P _R to the reset gate RG and floating diffusion region FD is reset to the initial voltage Vdd, the charge accumulated in the floating diffusion region FD Reset drain region R
It is designed to sweep out to the D side.

Conventionally, a source follower circuit 5 comprising a driving MOS transistor 3 and a load MOS transistor 4 is specifically configured as shown in FIG. That is, N-type diffusion layers 13 and 14 are formed in a second conductivity type, that is, a P-type well region 12 formed on a semiconductor substrate 11 of a first conductivity type, for example, an N-type.
And 15 are formed, and a gate electrode 16 is formed on the surface of the well region in the N-type diffusion layers 13 and 14 via a gate insulating film. Is formed, and a gate electrode 17 is formed on the surface of the well region between the N-type diffusion layers 14 and 15 via a gate insulating film. The N-type diffusion layers 14 and 15 are respectively A source follower circuit 5 is formed by forming an N-channel load MOS transistor 4 as a source.

On the other hand, N
Diffusion region FD due to diffusion layer
Is formed, and this floating diffusion region F
D is connected to the gate electrode 16 of the driving MOS transistor 3.

Normally, a ground potential is applied to the P-type well region 12 through the P-type high-concentration region 18, and a positive potential is applied to the N-type semiconductor substrate 11. The source (diffusion layer) 15 of the load MOS transistor 4 is at the ground potential. Therefore, when the P-type well region 12 is depleted, there is a possibility that the source (diffusion layer) 15 and the P-type well region 12 become forward biased, and cannot function as an output circuit. Therefore, conventionally, the impurity concentration of the P-type well region 12 is set so as not to be depleted.

[0007]

In the conventional output section described above, the driving MOS transistor 3 and the load MOS transistor 4 constituting the source follower circuit 5 are located in the P-type well region 12 having the same concentration. As a result, optimum IV characteristics cannot be obtained for each of the driving MOS transistor 3 and the load MOS transistor 4, and the gain of the output circuit is disadvantageously reduced.

That is, the load MOS transistor 4 does not have the ideal IV characteristics shown in FIG. 3, but has the sloped IV characteristics shown in FIG. On the other hand, in the driving MOS transistor 3, the P-type well region 12 is not depleted, and the well region under the gate is fixed to the ground potential. And the output voltage Vout decreases accordingly. Because of this, the input voltage Vin
, That is, the gain of the output voltage Vout.

In the case of the source follower circuit 5 in the first stage, not only the gain of the output circuit but also the charge-voltage conversion efficiency decreases. That is, in order to avoid a decrease in the drain current Id of the driving MOS transistor 3, the ratio of the gate width W / length L may be increased, but if the transistor size is increased by increasing the width W, the result is In general, the capacity of the floating diffusion increases, and the charge-voltage conversion efficiency decreases. Therefore, the gain is double deteriorated. As the gain decreases, the sensitivity as a CCD image sensor also decreases.

The present invention has been made in view of the above circumstances, and provides a CCD image pickup device in which the gain of an output circuit is improved and the sensitivity is improved.

[0011]

According to the present invention, a charge transfer unit is provided.
From the floating diffusion F
D, and a voltage change based on the accumulated charge is supplied to a source follower circuit 5 including a driving transistor element 3 and a load transistor element 4 so as to be extracted as an output voltage from an output terminal Tout of the source follower circuit 5. In a CCD image pickup device having an output section formed as described above, a driving transistor element 3 of a source follower circuit 5 is provided.
And the load transistor element 4 is formed in the well regions 21 and 22 of the semiconductor substrate 1 and the impurity concentrations of the well region 21 corresponding to the drive transistor element 3 and the well region 22 corresponding to the load transistor element 4 are mutually Set differently.

That is, the well region 21 forming the driving transistor element 3 has a low concentration capable of being depleted, and the well region 22 forming the load transistor element 4 has a high concentration which is not depleted and is so-called neutral. Set.

[0013]

In the present invention, the load transistor element 4
By differentiating the concentrations of the well region 22 corresponding to the above and the well region 21 corresponding to the driving transistor element 3, the respective IV characteristics can be optimized.

That is, in the load transistor element 4, since the corresponding well region 22 is set to a high concentration not to be depleted, the well region below the gate is fixed to the ground potential and is so-called neutral, so that the drain region is drained. An almost ideal IV characteristic shown in FIG. 3 without current fluctuation is obtained.

On the other hand, in the driving transistor element 3, the corresponding well region 21 is set to a low concentration at which the well region 21 is depleted, so that the above-mentioned back gate effect is eliminated and a decrease in drain current is avoided. Therefore, the gain of the source follower circuit 5 is improved, and the sensitivity as a CCD image pickup device is improved.

[0016]

An embodiment of the present invention will be described below with reference to FIG.

The CCD image pickup device according to the present embodiment is the same as that shown in FIG.
Similarly to the above, a discharge element 2 including a floating diffusion region FD, a reset gate RG, and a reset drain region RD is provided at the next stage of the charge transfer unit 1 composed of a CCD with an output gate OG interposed therebetween. A driving MOS transistor 3 and a load M
An output buffer 66 having a source follower circuit 5 including the OS transistor 4 is provided.

Thus, in the present embodiment, the source follower circuit 5 is configured as shown in FIG. That is, a first conductivity type, for example, an N-type semiconductor substrate 1 serving as a substrate constituting a CCD image pickup device, and a second conductivity type having a different concentration, that is, a P-type first substrate.
The well region 21 and the second well region 22 are formed so as to be in contact with each other. In this case, the first well region 21 is formed at a low concentration that is depleted, and the second well region 22 is formed at a higher concentration than the first well region 21 so as not to be depleted.

The driving MOS transistor 3 is formed in the low-concentration first well region 21 and the load MOS transistor 4 is formed in the high-concentration second well region 22 to form the source follower circuit 5.

In this case, an N-type first diffusion layer 13 is formed in the first well region 21 and the first and second well regions 21 are formed.
, 22 is formed, and an N-type third diffusion layer 15 is formed in the second well region 22.
Then, a gate electrode 16 is formed on the surface of the first well region between the first and second diffusion layers 13 and 14 via a gate insulating film to form the driving MOS transistor 3. Also,
A gate electrode 17 is formed on the surface of the second well region between the second and third diffusion layers 14 and 15 via a gate insulating film to form the load MOS transistor 4.

The floating diffusion region FD formed in the first well region 21 and the driving MOS
The gate electrode 16 of the transistor 3 is connected, and the driving M
The voltage V is applied to the drain (diffusion layer) 13 of the OS transistor 3.
dd is applied, and an output terminal Tout is derived from the diffusion layer 14. Further, a predetermined gate voltage Vgg is applied to the gate electrode 17 of the load MOS transistor 4, and its source (diffusion layer) 15 is at the ground potential. First and second
The ground potential is applied to the well regions 21 and 22 through the P-type high-concentration region 18 provided in the second well region 22.

According to the above configuration, the second well region 22 is formed at a high concentration on the side of the load MOS transistor 4 of the source follower circuit 5, so that the well region below the gate is not depleted. It is fixed at the ground potential, and is so-called neutralized. Therefore, the IV characteristic of the load MOS transistor 4 becomes the ideal characteristic shown in FIG.

On the other hand, on the driving MOS transistor 3 side, the first well region 21 is formed at a low concentration, so that the first well region 21 is depleted. Therefore, the back gate effect is suppressed, and a decrease in the drain current Id is avoided. Therefore, it is not necessary to increase the size of the transistor, the gain of the source follower circuit 5 can be improved, and the charge-voltage conversion efficiency can be improved. Therefore, the sensitivity as a CCD image sensor can be improved.

Further, according to this configuration, the variation in the operation with respect to the variation in the semiconductor manufacturing process, that is, the manufacturing variation is reduced.

In the above example, the first, second and third diffusion layers 1
The source follower circuit 5 was formed using 3, 14, and 15. However, although not shown, a first well region and a second well region were formed, and a pair of diffusion layers were formed in the first well region. The present invention can also be applied to a configuration in which the driving MOS transistor 3 is formed, a pair of diffusion layers are formed in the second well region to form the load MOS transistor 4, and the ground potential is applied to each well region.

[0026]

According to the present invention, both the driving transistor element and the load transistor element of the source follower circuit in the output section of the CCD image pickup element are optimally connected to an IV.
Characteristics, the gain of the source follower circuit can be improved, and the charge-voltage conversion efficiency can be improved.
Therefore, the sensitivity of the CCD imaging device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of an output unit of a CCD image pickup device according to the present invention.

FIG. 2 is a configuration diagram of an output unit of the CCD image sensor.

FIG. 3 is an ideal IV characteristic diagram required for a load MOS transistor of a source follower circuit constituting an output unit.

FIG. 4 is an IV characteristic diagram of a load MOS transistor in an output section in a conventional CCD image sensor.

FIG. 5 is a cross-sectional view of a main part of an output unit of a conventional CCD image sensor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Charge transfer part 2 Discharge element OG Output gate FD Floating diffusion region RG Reset gate RD Reset drain region 3 Driving MOS transistor 4 Load MOS transistor 5 Source follower circuit 11 N type semiconductor substrate 12, 21, 22 P well Regions 13, 14, 15 Diffusion layer 18 P-type high concentration region

Claims (1)

(57) [Claims] A signal charge from a charge transfer section is temporarily stored in a floating diffusion, and a voltage change based on the stored charge is supplied to a source follower circuit including a driving transistor element and a load transistor element. In a CCD image pickup device having an output section adapted to take out an output voltage from an output terminal of the source follower circuit, a driving transistor element and a load transistor element of the source follower circuit are formed in a well region of a semiconductor substrate, A CCD image pickup device wherein a well region corresponding to a driving transistor element and a well region corresponding to the load transistor element are set to have different impurity concentrations.