JP2866329B2 - Structure of solid-state image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD solid-state image pickup device, and more particularly to a CCD solid-state imaging device, in which a potential step (PotentialStep) is formed at an interface between a vertical charge transfer area VCCD and a horizontal charge transfer area HCCD to thereby improve charge transfer efficiency. The present invention relates to a structure of a solid-state imaging device in which is improved.

[0002]

2. Description of the Related Art An ordinary CCD is arranged between a plurality of photodiode regions PD arranged in a matrix and outputting light signals as electrical video signals, and the photodiode regions PD arranged in a matrix. A plurality of vertical charge transfer areas VCCD which are formed in the vertical direction and transfer the video signal charges generated from the respective photodiodes PD in the vertical direction; and a plurality of vertical charge transfer areas VCCD which are formed on one end side of the vertical charge transfer area VCCD. Horizontal charge transfer area HCC for transferring video signal charges transferred to the charge transfer area in the horizontal direction
D, and a sense amplifier formed at the output end of the horizontal charge transfer area HCCD to detect the transferred video signal charges and output them as electrical signals.

Hereinafter, a conventional solid-state imaging device will be described in more detail with reference to the accompanying drawings. FIG. 1A is a layout diagram of a conventional CCD, and FIG. 1B is a cross-sectional structure and a potential profile of the conventional CCD. First,
As shown in FIG. 1A, a plurality of photodiode regions PD, a plurality of vertical charge transfer regions VCCD for vertically transferring video signal charges generated from each photodiode region PD, and the vertical charge The respective gates are configured as follows on a substrate including the horizontal charge transfer area HCCD provided at one end of the transfer area VCCD.

On the vertical charge transfer region, a plurality of gates 1 and 2 for sequentially transferring video signal charges generated from each photodiode region in the vertical direction are repeatedly formed. At this time, the poly gate 1 is configured such that one side overlaps the photodiode region and is used as a transfer gate.

The gate electrodes 1 and 2 formed on the vertical charge transfer region have VΦ _{1 for} the first gate 1, VΦ 2 for the first poly gate ₂ , VΦ ₃ for the second gate 1, and VΦ ₃ for the second gate 1. the gate 2 is applied clock V.phi _4, sequentially transferring the image signal charges in the vertical direction. That is, the transfer operation of the video signal charge is performed by the four-phase clock.

Gates 3 and 4 are provided on the horizontal charge transfer area for transferring the image signal charges transferred from the vertical charge transfer area by a two-phase clock to an electric image signal and transferring the same to a sense amplifier. Is configured. That is, a plurality of gates 3 and 4 formed on the horizontal charge transfer region have H level.
The clocks of Φ ₁ and HΦ ₂ are alternately applied to sequentially transfer the video signal charges.

As shown in FIG. 1B, in the conventional solid-state imaging device configured as described above, the video signal charges generated in the respective pixel regions are VΦ ₁ , VΦ ₂ , VΦ ₃ , and VΦ _4.
The transfer changes the potential level in the vertical direction by the clock, the video signal charge yet H.phi ₁ of the, H
Is transferred to the floating gate region by the [Phi ₂ clock is output after being converted into analog signals through the sense amplifier.

[0008]

However, in the above-mentioned conventional solid-state imaging device, the charge transfer efficiency is caused by potential barriers, potential pockets, and the like generated in overlapping wells at the interface between the vertical charge transfer region and the horizontal charge transfer region. However, there is a problem that the temperature is reduced.
The channel stop layer C of the HV interface section
There is a problem that a video signal charge is not efficiently transferred due to the narrow channel effect due to the ST and a defect such as a black line appears on the screen.

An object of the present invention is to solve the above-mentioned problems of the conventional solid-state imaging device, and an object of the invention is to provide a solid-state imaging device having improved charge transfer efficiency (CTE).

[0010]

In order to achieve the above object, the structure of the solid-state imaging device according to the present invention comprises a vertical charge transfer region V
A barrier gate controlled by an external DC bias is disposed at an interface between the CCD and the horizontal charge transfer area HCCD so that a potential step is formed at the interface.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a solid-state imaging device according to the present invention will be described below in detail with reference to the drawings. FIG. 2 (a)
2 is a layout diagram of the CCD of the present invention, and FIG. 2B is a cross-sectional structure and potential profile of the CCD of the present invention.

First, as shown in FIG. 2A, a plurality of photodiode regions PD arranged in a matrix on a semiconductor substrate to convert light signals into electric video signals and output the electric video signals, Four-phase clocks VΦ ₁ , VΦ applied to a plurality of gate electrodes 21, 20 formed vertically between diode regions and repeatedly formed on the upper side
₂ , a plurality of vertical charge transfer regions VCCD for transferring charges generated from the photodiode region by VΦ ₃ and VΦ ₄ in a vertical direction, and formed at one end of the vertical charge transfer regions and vertically transferred. The two-phase clock HΦ ₁ applied to the gate electrodes 24 and 25 by applying the video signal charges thus obtained,
Horizontal charge transfer area HC for transferring horizontally by HΦ ₂
A gate electrode to which HΦ ₁ is applied to the interface between the CD and the vertical charge transfer area VCCD and the horizontal charge transfer area HCCD (in the embodiment of the present invention, a final voltage to which VΦ ₄ on the vertical charge transfer area VCCD is applied). since the gate electrode a gate electrode end are overlapped, the gate electrode H.phi ₁ on the horizontal charge transfer region HCCD is applied partially be overlapped to must electrode overlapping), V.phi ₄ is applied And a barrier gate formed horizontally adjacent to the rearmost gate electrode and forming a potential step in the interface section by an external DC bias.

The barrier gate is a first barrier gate 2
2. Double gate structure of the second barrier gate 23.
A vertical charge transfer region VCCD and a horizontal charge transfer region HCCD are formed in one of the lower regions of the first and second barrier gates 22 and 23 by an ion implantation process.
And a barrier layer having an intermediate potential level between them.

In the solid-state imaging device of the present invention having the above structure, the potential profile under each gate is shown in FIG.
It is formed as shown in FIG.

[0015]

That is, an intermediate level potential step is formed by an external DC bias below the interface between the horizontal charge transfer area HCCD and the vertical charge transfer area VCCD, and a potential barrier or a potential barrier generated at the HV interface is formed. There is an effect that the potential pocket is removed, the charge transfer efficiency is improved, and the black line defect generated at low illuminance is eliminated.

[Brief description of the drawings]

FIG. 1A is a layout diagram of a conventional CCD,
(B) is a cross-sectional structure and a potential profile of a conventional CCD.

FIG. 2A is a layout diagram of a CCD of the present invention,
(B) is a sectional structure and a potential profile of the CCD of the present invention.

[Explanation of symbols]

20, 24 ... gate electrode, 21, 25 ... gate electrode, 2
2 ... first barrier gate, 23 ... second barrier gate.

Continuation of the front page (56) References JP-A-60-160658 (JP, A) JP-A-4-167470 (JP, A) JP-A-60-160657 (JP, A) JP-A-2-96730 (JP) , U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/148 H04N 5/335

Claims (1)

(57) [Claims] 1. A plurality of photodiode regions (PD) which are arranged in a matrix on a semiconductor substrate and convert optical signals into electric video signals and output the signals, and a vertical direction between the photodiode regions. Formed,
4-phase clocks applied to the gate electrode _{(20,21) (VΦ 1, VΦ} 2, VΦ 3, VΦ 4) a plurality of vertical charge transfer region for transferring electric charges generated by the photodiode region in the vertical direction by (VCCD ), And two-phase clocks (HΦ ₁ , HΦ) formed at one end of the vertical charge transfer region and applied to the gate electrodes (24, 25).
Φ ₂ ) a horizontal charge transfer region (HCCD) for transferring video signal charges transferred in the vertical direction in the horizontal direction, wherein the vertical charge transfer region (VCCD) and the horizontal charge transfer region (VCCD) interface, VCC
A barrier gate for forming a potential step in the interface section by an external DC bias between the last gate electrode of D and the first gate electrode of the HCCD, wherein the barrier gate is a first barrier gate and a second barrier gate Double gate structure, vertical charge transfer
The lowest potential level of the VCCD during transmission
HCCD at the time of horizontal charge transfer.
Potential higher than the lowest potential level of
A structure of a solid-state imaging device , wherein a barrier layer having a level is formed by ion implantation in a lower region of one of the first barrier gate and the second barrier gate.