JP2827327B2 - Charge transfer device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a charge transfer device having a charge transfer unit using a charge-coupled device.

[Summary of the Invention]

According to the present invention, in a charge transfer device in which element isolation is performed by an oxide film thicker than a gate oxide film, a transistor of an output unit to which an output extraction unit that terminates a charge transfer unit and a wiring from the output extraction unit are connected is provided. By forming it in a single element formation region surrounded by the same element isolation region, or by arranging a conductor layer having a source potential of the transistor between the transistor and the output extraction portion, The purpose is to reduce the parasitic capacitance of the device.

[Conventional technology]

In general, a CCD has an output extraction unit for extracting an output of a floating diffusion or the like at an end of a charge transfer unit (register), and an output signal is output from the floating diffusion via a buffer or the like having a source follower configuration. Is done. Also, such a CC
D forms a thick field oxide film (LOCOS) by selective oxidation on the surface of a silicon substrate in order to isolate each element.

FIG. 5 is a plan view of the terminal portion of such a conventional CCD register. As shown in FIG. 5, a buried channel layer 102 is formed so as to be surrounded by a field oxide film 101 formed on a silicon substrate, and a floating diffusion region 103 is formed at a terminal portion where the buried channel layer 102 is narrowed. Have been. A precharge gate 104 for precharge (reset) is adjacent to the floating diffusion region 103, and a precharge drain 105 is formed adjacent to the precharge gate 104. A polysilicon layer 106 is extracted from the floating diffusion region 103 through a contact hole 108, and this polysilicon layer 106 is used as a gate electrode of a first-stage MOS transistor 107 in an output section.

FIG. 6 is a sectional view taken along line VI-VI of FIG. As shown in FIG. 6, a thick field oxide film 101 is formed on the surface of a silicon substrate 100 by selective oxidation. The floating diffusion region 103 and the MOS transistor 107 are each surrounded by a separate field oxide film 101 on a plane, and a channel stopper region 109 is provided below the field oxide film 101.

[Problems to be solved by the invention]

By the way, in order to improve the output gain of a CCD having such a structure, it is necessary to reduce the capacitance (parasitic capacitance) of the output section as a whole. The capacitance includes the capacitance of the floating diffusion region 103, the capacitance between the precharge gate 104, the wiring capacitance of the polysilicon layer 106, and the capacitance between the polysilicon layer 106 and the source / drain of the transistor. Although included, the overall parasitic capacitance can be reduced by reducing the sizes of the floating diffusion region 103 and the MOS transistor 107.

However, the wiring capacitance of the polysilicon layer 106 is formed over the tapered portion 110 of the field oxide film 101, and the tapered portion 110 cannot be removed even when the area of the field oxide film 101 is reduced. For this reason, the polysilicon layer 106 prevents the wiring capacitance from improving the output gain.

In view of the above technical problem, an object of the present invention is to provide a charge transfer device that reduces a parasitic capacitance at a terminal portion of a charge transfer unit.

[Means for solving the problem]

In order to achieve the above object, a charge transfer device according to a first aspect of the present invention is a charge transfer device in which an element isolation region is formed on a semiconductor substrate by an oxide film having a thickness larger than a gate oxide film. An output extraction unit that terminates the transfer unit and a transistor of an output unit to which a wiring from the output extraction unit is connected are formed in a single element formation region surrounded by the same element isolation region. And

Further, according to the charge transfer device of the second invention of the present application, in a charge transfer device in which an element isolation region is formed on a semiconductor substrate by an oxide film having a thickness larger than a gate oxide film, an output extraction terminating a charge transfer portion is provided. Unit and the MIS transistor of the output unit to which the wiring from the output extraction unit is connected,
A conductor layer is formed on a semiconductor substrate between the output extraction portion and the MIS transistor via an insulating film, and is formed in a single element formation region surrounded by the same element isolation region. The conductor layer is set at the source potential of the MIS transistor.

The output take-out unit is, for example, a structural unit such as a floating diffusion region or a floating gate.

[Action]

In the charge transfer device of the present invention, instead of using an oxide film thicker than the gate oxide film to separate all elements,
By forming the output transistor and the output extraction section that terminates the charge transfer section in an element formation region surrounded by an element isolation region that draws a single closed curve, the output section transistor and the output extraction section are separated. Has no thick oxide film. Therefore, the parasitic capacitance of the wiring does not increase in a portion such as a tapered portion of a thick oxide film, and the overall capacitance can be reduced.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example of a CCD in which a wiring layer made of a polysilicon layer is formed on a transistor of an output unit from a floating diffusion region as an output extraction unit.

First, FIG. 1 shows a plan view of a main part of the CCD of this embodiment. As shown in FIG. 1, the CCD 1 has a thick field oxide film 2 formed on a silicon substrate, and is surrounded by the field oxide film 2 so that a buried channel layer 4, a floating diffusion region 5, MOS transistor 6, precharge gate 7, precharge drain 8
Are formed. The field oxide film 2 is a thick oxide film formed by a selective oxidation method, and has a tapered portion 3 around the thick oxide film. Although this taper portion 3 is cut off at the buried channel layer 4 in the figure, it draws a single closed curve. In particular, the MOS transistor 6, floating diffusion region 5, buried channel layer 4, precharge drain 8, etc. It is surrounded by one continuous tapered portion 3 so as to have the same element formation region.

Here, the buried channel layer 4 is a region to which charges are transferred, and although not shown in the figure, a transfer electrode driven by a required transfer clock signal is formed thereon. Further, an output gate for controlling timing for transferring electric charges to the floating diffusion region 5, for example, is formed at the terminal portion.

In addition, the floating diffusion region 5 is a region for taking out charges transferred in the H direction in the figure, and is composed of an n-type impurity region. The floating diffusion region 5 has a substantially square pattern, and a polysilicon layer 10 is connected to a substantially center of the floating diffusion region 5 through a contact hole 9.

The precharge gate 7 formed adjacent to the floating diffusion region 5 is an electrode for controlling the timing of performing precharge. This precharge gate 7 is also formed of a polysilicon layer. The precharge drain 8 is an impurity region to which a precharge voltage is applied.

The polysilicon layer 10 extracted from the floating diffusion region 5 extends in the V direction in the figure,
It is used as it is as the gate electrode of the MOS transistor 6. The MOS transistor 6 has source / drain regions 11, 11 on both sides of the polysilicon layer 10. This M
The OS transistor 6 has a source follower configuration and functions as a first-stage element of an output buffer. And this MO
The field oxide film 2 surrounds the S transistor 6, but only partially surrounds the MOS transistor 6. , The field oxide film 2 is not formed.
There is no tapered portion 3 between the transistor 6 and the buried channel layer 4 and the floating diffusion region 5.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. As shown in FIG. 2, the n-type impurity region formed on the surface of the silicon substrate 12 is a floating diffusion region 5. is there. A gate oxide film 13 is formed on the surface of the silicon substrate 12, and the gate oxide film 13 has a contact hole 9 on the floating diffusion region 5. A polysilicon layer 10 is formed from the contact hole 9 over the gate oxide film 13.
This polysilicon layer 10 becomes the gate electrode of the MOS transistor 6.

Then, the floating diffusion region 5 and the MO
In the region between the S transistors 6, only the channel stopper region 14 made of a relatively low concentration p-type impurity region is formed on the surface of the silicon substrate 12, and the thick field oxide film 2 is formed. Therefore, the taper portion 3 is not formed in the region between the floating diffusion region 5 and the MOS transistor 6. For this reason, the polysilicon layer 10 serving as the gate electrode of the MOS transistor 6 does not need to be wired up and down the slope of the tapered portion at the end of the field oxide film, and the parasitic capacitance is reduced accordingly. Become.

Second Embodiment This embodiment is an example in which a MOS transistor of an output section and a floating diffusion region are formed in an element formation region surrounded by the same field oxide film, and a source potential is provided around the MOS transistor. This is an example in which a conductive layer is formed.

First, FIG. 3 shows a plan view of a main part of the CCD of this embodiment. As shown in FIG. 3, the CCD 21 has a thick field oxide film 22 formed on a silicon substrate,
A buried channel layer 24, a floating diffusion region 25, a MOS transistor 26, a precharge gate 27, and a precharge drain 28 are formed surrounded by the field oxide film 22. The field oxide film 22 is a thick oxide film formed by a selective oxidation method, and has a tapered portion 23 around its periphery. This tapered portion 23
Formed at the end of the field oxide film 22, especially the MOS transistor 26, the floating diffusion region 25,
Buried channel layer 24 and precharge drain 28,
The precharge gate 27 is surrounded by the tapered portion 23 so as to be in the same element formation region.

Here, the floating diffusion region 25, the buried channel layer 24, the precharge drain 28, and the precharge gate 27 are respectively the floating diffusion region 5, the buried channel layer 4, the precharge drain 8, and the precharge gate 7 in the first embodiment. Are used in the same manner.

MOS transistor 26 uses polysilicon layer 30 extended from contact hole 29 formed on floating diffusion region 25 as a gate electrode. A source region 31s is formed on the buried channel layer 24 side of the polysilicon layer 30, and a drain region 31d is formed on the opposite side. Then, a polysilicon layer 34 as a conductive layer is formed surrounding the MOS transistor 26. The polysilicon layer 34 is formed in a pattern surrounding the substantially rectangular MOS transistor 26 on a plane, and a part of the polysilicon layer 34 surrounds the regions of the precharge drain 28 and the precharge gate 27, and is opposite to the floating diffusion region 25. It extends to the side. The source potential of the MOS transistor 26 is applied to the polysilicon layer 34. Therefore, formation of a channel below the polysilicon layer 34 is prevented. In the figure, the wiring 35 schematically shown is
Source region 31s of MOS transistor 26 and polysilicon layer 34
Are electrically connected. The wiring 35 may be formed of the second polysilicon layer. Alternatively, a contact hole may be formed on the source region 31s, and the polysilicon layer 34 may be overlapped with the contact hole.

FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 3, and shows a polysilicon layer 30 serving as a gate electrode of a MOS transistor 26 along a gate oxide film 33 formed on a silicon substrate 32. Are formed. Then, a polysilicon layer 34 is formed adjacent to the floating diffusion region 25 formed of an n-type impurity region, for applying a source potential to prevent channel formation. The polysilicon layer 30 and the polysilicon layer 34 are insulated by an interlayer insulating film 36 covering the polysilicon layer 34.

Since the source potential is applied to the polysilicon layer 34, the floating diffusion region 25 is electrically separated from the channel formation region below the gate of the MOS transistor 26. For this reason, it is possible to perform element isolation without having to dispose the field oxide film 22 between the floating diffusion region 25 and the MOS transistor 26.Since the field oxide film 22 is not formed in that region, a polysilicon layer formed by a tapered portion is formed. An increase in the wiring capacity of 30 can be suppressed. Therefore, the output gain can be improved.

〔The invention's effect〕

As described above, in the charge transfer device of the present invention, the transistor of the output unit and the output extraction unit such as the floating diffusion region are formed in a single element isolation region that draws one closed curve. For this reason, the parasitic capacitance of the wiring from the output extraction portion can be reduced, and as a result, the conversion efficiency from charges to the output voltage increases, and the output gain can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of an essential part of an example of the charge transfer device of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. FIG. 4 is a sectional view taken along the line IV-IV of FIG. 3 showing another example of the above, and FIG. 5 is a plan view of an essential part of an example of a conventional charge transfer device. FIG. 6 shows an example of the prior art, and FIG.
FIG. 6 is a cross-sectional view along the line VI. 1,21 ... CCD 2,22 ... Field oxide film 3,23 ... Tapered part 4,24 ... Buried channel layer 5,25 ... Floating diffusion region 6,26 ... MOS transistor 10,30,34 ... … Polysilicon layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/339 H01L 27/14-27/148 H01L 29/762-29/768 H01L 21/76-21 / 765

Claims (2)

(57) [Claims] In an electric charge transfer device in which an element isolation region is formed on a semiconductor substrate by an oxide film having a thickness larger than a gate oxide film, an output extraction portion for terminating the charge transfer portion, and an output extraction portion from the output extraction portion. A charge transfer device, wherein a transistor of an output portion to which a wiring is connected is formed in a single element formation region surrounded by the same element isolation region. 2. An output extraction unit for terminating a charge transfer unit;
A conductor layer is formed via an insulating film on a semiconductor substrate between a wiring from the output extraction portion and an MIS transistor of the output portion connected to the gate, and the conductor layer is set to a source potential of the MIS transistor. The charge transfer device according to claim 1, wherein: